run_ctrl.vhd

--*********************************************************************************
-- Indiana University
-- Center for Exploration of Energy and Matter (CEEM)
-- Project: Belle-II
-- Author:  Brandon Kunkler
-- Date:    06/09/2014
--*********************************************************************************
-- ### run_ctrl.vhd
-- ##### Description:
-- Run control interface. Shifts in 16 bit run-ctrl words when rx_src_rdy_n is asserted.
-- rx_src_rdy_n is asserted by rx_ll_pdu_datapath.vhd "when there is data in storage and
-- incomiming data or the end of a frame."

--
-- Change Log:
-- 2020/07/29 Linting code. Added documentation. Commented out unused ports. (CK)
--            Fixed Xst:638 - Conflict on KEEP property on signal tmp48 and rcl_fifo_din_32.
--            
--
-- Deficiencies/Issues:
-- 1. rx_sof_n, rx_eof_n, and rx_dst_rdy_n are useless at this time. All are wired
--    through klm_intfc.vhd, to FFs conc_intfc.vhd, then back to klm_intfc.vhd. The first two
--    originate in rx_ll_pdu_datapath.vhd as part of the Aurora core. Perhaps intention
--    was to verify integrity of run-ctrl words. For now, the integrity check involves
--    matching our own SOF/EOF before writting to rcl_fifo. Further, we count the number
--    of received words and report it to a status register. This is then checked in software
--    for a match to number of words sent. Standard practice thus far has been to just resend
--    if there is a mismatch between nubmer of sent and received words. 
--*********************************************************************************
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_misc.all;
library work;
    use work.conc_intfc_pkg.all;
    use work.klm_scint_pkg.all;
entity run_ctrl is
    port(
        clk                     : in  std_logic;
        -- rx_dst_rdy_n            : out std_logic; --goes to FF in conc_intfc then back one level and nothing . . . 
        -- rx_sof_n                : in  std_logic; --which means that this is useless
        -- rx_eof_n                : in  std_logic; --and this
        rx_src_rdy_n            : in  std_logic;
        rx_data                 : in  std_logic_vector(15 downto 0);
        rcl_fifo_rd_clk         : in  std_logic;
        rcl_fifo_rd_en          : in  std_logic;
        rcl_fifo_data           : out std_logic_vector(31 downto 0);
        rcl_fifo_empty          : out std_logic
    );
end run_ctrl;


architecture behave of run_ctrl is

    -- signal intfc_bit               : std_logic;
    signal rcl_fifo_frame_set_q    : std_logic_vector(1 downto 0) := "10";
    signal rcl_fifo_frame_set      : std_logic := '0';

    signal rx_data_sr              : std_logic_vector(47 downto 0);
    alias  ic                      : std_logic_vector(7 downto 0) is rx_data_sr(35 downto 28);
    alias  addr                    : std_logic_vector(7 downto 0) is rx_data_sr(27 downto 20);
    alias  val                     : std_logic_vector(15 downto 0) is rx_data_sr(19 downto 4);
    signal rcl_fifo_din_32         : std_logic_vector(31 downto 0);
    
    
    signal rcl_fifo_wr_en_32   : std_logic := '0';
    signal rcl_fifo_rst        : std_logic;


begin

---------------------------------------------------------------------------------------------------------



  
    u_runctrl_fifo : entity work.fifo_cc -- 1024 depth
    generic map(
        DATA_WIDTH => 32,
        DEPTH => 10 -- bit
    )
    PORT MAP (
        clk    => clk,
        rst    => '0',
        din    => rcl_fifo_din_32,
        wen    => rcl_fifo_wr_en_32,
        ren    => rcl_fifo_rd_en,
        dout   => rcl_fifo_data,
        full   => open,
        empty  => rcl_fifo_empty
    );
    
    -- Run control(RCL) data format: 
    -- | SOF(4)=0xF | TYPE(3) | LANE(4) | IC(8) | ADDR(8) | VALUE(16) | EOF(4)=0x8 |

    -- Type and Lane parsed by Data concentrator.

    -- 32-bit run-ctrl word is (IC & ADDR & VALUE)
    -- |--------------------------------------|----|------|------|
    -- | Description                          | IC | Addr | Val  |
    -- |--------------------------------------|----|------|------|
    -- | set SCROD reg=XX to val=YYYY         | AF | XX   | YYYY |
    -- | set ASIC=X reg=YY to val=ZZZ         | BX | YY   | 0ZZZ |
    -- | set HV DAC for ASIC=X ch=Y to val=ZZ | C0 | XY   | 00ZZ |
    -- | pause rcl fsm for XXXX00 clocks      | AE | 00   | XXXX |
    -- |--------------------------------------|----|------|------|

    rcl_fifo_din_32    <= ic & addr & val;
    rcl_fifo_frame_set <= '1' when rx_data_sr(47 downto 44) = "1111" and rx_data_sr(3 downto 0)= "1000" else '0'; -- we have a full frame with start and end bits in place- data driven, not ideal really
    rcl_fifo_wr_en_32  <= '1' when rcl_fifo_frame_set_q = "01" else '0';
    
    shift_pcs : process(clk)
    begin
        if (clk'event and clk = '1') then
        
            rcl_fifo_frame_set_q <= rcl_fifo_frame_set_q(0) & rcl_fifo_frame_set;
   
            if rx_src_rdy_n = '0' then
                rx_data_sr   <= rx_data_sr(31 downto 0) & rx_data;
            end if;
                                
            -- intfc_bit <= rx_sof_n xor rx_eof_n xor rx_src_rdy_n;
            -- rx_dst_rdy_n <= intfc_bit;
        end if;
    end process;





end behave;