behave Architecture Reference

Processes
shift_pcs	( clk )

Signals
rcl_fifo_frame_set_q	std_logic_vector ( 1 downto 0 ) := " 10 "
rcl_fifo_frame_set	std_logic := ' 0 '
rx_data_sr	std_logic_vector ( 47 downto 0 )
rcl_fifo_din_32	std_logic_vector ( 31 downto 0 )
rcl_fifo_wr_en_32	std_logic := ' 0 '
rcl_fifo_rst	std_logic

Instantiations
u_runctrl_fifo	fifo_cc <Entity fifo_cc>

Aliases
ic	std_logic_vector ( 7 downto 0 ) is rx_data_sr ( 35 downto 28 )
addr	std_logic_vector ( 7 downto 0 ) is rx_data_sr ( 27 downto 20 )
val	std_logic_vector ( 15 downto 0 ) is rx_data_sr ( 19 downto 4 )

Detailed Description

Definition at line 52 of file run_ctrl.vhd.

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The documentation for this class was generated from the following file:

• klm_scrod/source/run_ctrl.vhd