Behavioral Architecture Reference

Processes
fifo_dout_mux	( clk , i_fifo_rd_asic , wave_fifo_dout_q1 , fifo_drdy_q1 , ped_fifo_dout_q1 )
dout_concatenation	( clk , fifo_drdy_q2 , wave_fifo_dout_q2 , ped_fifo_dout_q2 )
dout_buf	( clk , wave_fifo_dout_q0 , ped_fifo_dout_q0 , fifo_drdy_q0 )
chk_all_empty_fan_in_1	( clk , ped_fifos_empty , wave_fifos_empty )
chk_all_empty_fan_in_2	( clk , all_ped_fifos_empty , all_wave_fifos_empty )
reset_fanout_1	( clk , reset )
reset_fanout_2	( clk , reset_q1 )
sync_rdy_sig	( clk , i_fifo_rd_ena )
mode_mux	( clk , summing_ena , wave_fifo_wr_ena , fifo_rd_ena , pedcalc_dual_fifo_wr_ena , pedcalc_dual_fifo_din , pedcalc_dual_fifo_rd_ena , wave_fifo_wr_asic , fifo_rd_asic , main_samp_in )
cp_samp	( clk , wave_fifo_wr_ena , main_samp_in )
add_peds	( clk , start_adder , prime_fifos , wave_fifo_wr_asic , main_samp_in_copy , ped_fifo_dout_q2 , wave_fifo_dout_q2 )

Types
ped_navg_adder	( IDLE , WAIT_FIFO_READ_LAG , ADD_SAMPLE_AND_WRITE_FIFOS , PRIME_FIFOS_WITH_ZEROS )

Signals
add_peds_state	ped_navg_adder := IDLE
i_ped_fifo_wr_ena	std_logic_vector ( 4 downto 0 ) := " 00000 "
i_ped_fifo_din	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
i_wave_fifo_wr_ena	slv5 ( FIFO_DIN_SHIFT_DEPTH_g- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
wave_fifo_wr_asic_copy	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
i_fifo_rd_ena	std_logic_vector ( 4 downto 0 ) := " 00000 "
i_fifo_rd_asic	std_logic_vector ( 4 downto 0 ) := " 00001 "
i_wave_fifo_din	slv12 ( FIFO_DIN_SHIFT_DEPTH_g- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
main_samp_in_copy	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
wave_fifo_dout_q0	slv12 ( 4 downto 0 ) := ( others = > " 000000000000 " )
wave_fifo_dout_q1	slv12 ( 4 downto 0 ) := ( others = > " 000000000000 " )
wave_fifo_dout_q2	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
fifo_drdy_q0	std_logic := ' 0 '
fifo_drdy_q1	std_logic := ' 0 '
fifo_drdy_q2	std_logic := ' 0 '
ped_fifo_dout_q0	slv12 ( 4 downto 0 ) := ( others = > " 000000000000 " )
ped_fifo_dout_q1	slv12 ( 4 downto 0 ) := ( others = > " 000000000000 " )
ped_fifo_dout_q2	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
start_adder	std_logic := ' 0 '
pedcalc_dual_fifo_wr_asic	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
pedcalc_dual_fifo_wr_ena	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
pedcalc_dual_fifo_din	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
pedcalc_dual_fifo_rd_asic	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
pedcalc_dual_fifo_rd_ena	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ped_fifos_empty	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
wave_fifos_empty	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
all_ped_fifos_empty	std_logic := ' 0 '
all_wave_fifos_empty	std_logic := ' 0 '
i_ped_reset	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
i_wave_reset	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
reset_q1	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
ped_i	fifo_cc <Entity fifo_cc>
wave_i	fifo_cc <Entity fifo_cc>

Detailed Description

Definition at line 53 of file WaveAndPedStaging.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/WaveAndPedStaging.vhd