implementation Architecture Reference

Processes
PROCESS_172	( clock )

Signals
sig_i	std_logic := ' 0 '
sig_q	std_logic := ' 0 '
sig_inc	std_logic := ' 0 '
clr_inc	std_logic := ' 0 '
sig_islip	std_logic := ' 0 '
clr_islip	std_logic := ' 0 '
sig_bit2	std_logic_vector ( 1 downto 0 ) := " 00 "
sig_raw2	std_logic_vector ( 1 downto 0 ) := " 00 "
sta_slip	std_logic := ' 0 '
buf_bit	std_logic := ' 0 '
open_do	std_logic := ' 0 '
open_to	std_logic := ' 0 '
sig_busy	std_logic := ' 0 '
sig_caldelay	std_logic := ' 0 '
seq_caldelay	std_logic_vector ( 1 downto 0 ) := " 01 "
sig_invclock	std_logic := ' 0 '

Instantiations
map_ibufds	ibufds
map_idelay	iodelay2
map_id	iddr2
map_iscan	b2tt_iscan <Entity b2tt_iscan>

Detailed Description

Definition at line 78 of file b2tt_ddr_s6.vhd.

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The documentation for this class was generated from the following file:

• b2tt/b2tt/b2tt_ddr_s6.vhd