b2tt_iddr Entity Reference

Inheritance diagram for b2tt_iddr:

Entities
implementation	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
numeric_std
vcomponents

Generics
FLIPIN	std_logic := ' 0 '
REFFREQ	real := 203 . 546
SLIPBIT	integer := 0
WRAPCOUNT	integer := 170
FULLCOUNT	integer := 340
SIM_SPEEDUP	std_logic := ' 0 '

Ports
clock	in std_logic
invclock	in std_logic
dblclock	in std_logic
dblclockb	in std_logic
inp	in std_logic
inn	in std_logic
staoctet	in std_logic
stacrc8ok	in std_logic
manual	in std_logic
incdelay	in std_logic
clrdelay	in std_logic
caldelay	in std_logic
staiddr	out std_logic_vector ( 1 downto 0 )
bitddr	out std_logic
bit2	out std_logic_vector ( 1 downto 0 )
cntdelay	out std_logic_vector ( 6 downto 0 )
cntwidth	out std_logic_vector ( 5 downto 0 )
iddrdbg	out std_logic_vector ( 9 downto 0 )

Detailed Description

Definition at line 38 of file b2tt_ddr_s6.vhd.

---

The documentation for this class was generated from the following file:

• b2tt/b2tt/b2tt_ddr_s6.vhd