Behavioral Architecture Reference

Processes
PROCESS_38	( clk , ena , ena_i )
PROCESS_39	( clk , ena_i , sr_asic_sel )
PROCESS_40	( clk , shift_out_fsm_ena , sample_data_i , BUS_DO )

Types
sr_state_machine	( IDLE , WAIT_FOR_SAMPLE_ADDRESSING_TO_FINISH , WAIT_t_sr_clk_strobe , WAIT_SAMPLESEL_ANY_AND_FIRST_BIT , WAIT_T_SR_CLK_STROBE_HIGH , WAIT_T_SR_CLK_STROBE_LOW , HOLD_EVERYTHING_LOW_BEFORE_SHIFTING_OUT , WAIT_T_SR_CLK_HIGH , WAIT_T_SR_CLK_LOW )
shift_out_fsm	( IDLE , WAITING , SHIFTING )

Signals
sr_state	sr_state_machine := IDLE
shift_out_state	shift_out_fsm := IDLE
shift_out_fsm_ena	std_logic := ' 0 '
sample_data_i	slv11 ( 14 downto 0 ) := ( others = > " 00000000000 " )
samplesel_any_i	std_logic := ' 0 '
sr_clk_i	std_logic := ' 0 '
ena_i	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
asic_sel_i	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )

Detailed Description

Definition at line 65 of file ShiftOutSample.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/ShiftOutSample.vhd