RTL Architecture Reference

Processes
PROCESS_93	( USER_CLK )
PROCESS_94	( USER_CLK )
PROCESS_95	( USER_CLK )
PROCESS_96	( USER_CLK )
PROCESS_97	( USER_CLK )
PROCESS_98	( USER_CLK )
PROCESS_99	( USER_CLK )
PROCESS_100	( USER_CLK )
PROCESS_101	( USER_CLK )
PROCESS_102	( USER_CLK )
PROCESS_103	( USER_CLK )

Constants
DLY	time := 1 ns

Signals
RX_D_Buffer	std_logic_vector ( 0 to 15 )
RX_REM_Buffer	std_logic
RX_SRC_RDY_N_Buffer	std_logic
RX_SOF_N_Buffer	std_logic
RX_EOF_N_Buffer	std_logic
FRAME_ERR_Buffer	std_logic
storage_r	std_logic_vector ( 0 to 15 )
storage_v_r	std_logic
in_frame_r	std_logic
sof_in_storage_r	std_logic
pad_in_storage_r	std_logic
src_rdy_n_c	std_logic
storage_ce_c	std_logic

Detailed Description

Definition at line 89 of file rx_ll_pdu_datapath.vhd.

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The documentation for this class was generated from the following file:

• klm_aurora/source/rx_ll_pdu_datapath.vhd