Workshop will be held in
the Vince Peterson Library
on the 4th floor of Watanabe Hall (WAT417A)
located at the University of Hawai'i at Manoa
Agenda [link]
The goal of this workshop
is to explore calibration and design methods that both improve
the realized, pico-second timing performance of the current
generation of Giga-sample/s Switch Capacitor Array waveform
sampling ASICs, as well as brainstorm about next generation
architectures to explore future directions in which this
technology could evolve.
