behave Architecture Reference

Processes
mux_pcs	( clk )
valid_pcs	( clk )

Components
DSP48A1

Constants
OPMODE	std_logic_vector ( 7 downto 0 ) := " 01011101 "
ONE18	std_logic_vector ( 17 downto 0 ) := " 000000000000000001 "
SIX18	std_logic_vector ( 17 downto 0 ) := " 000000000000000110 "
ZERO48	std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
PIPEDLY	integer := 3

Signals
a	std_logic_vector ( 17 downto 0 )
b	std_logic_vector ( 17 downto 0 )
c	std_logic_vector ( 47 downto 0 )
d	std_logic_vector ( 17 downto 0 )
p	std_logic_vector ( 47 downto 0 )
b_d0	std_logic_vector ( 17 downto 0 )
lane_cval	std_logic_vector ( LANEIW- 1 downto 0 )
valid_shift	std_logic_vector ( PIPEDLY- 1 downto 0 )

Instantiations
dsp48a1_inst	dsp48a1

Detailed Description

Definition at line 61 of file trig_chan_calc.vhd.

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The documentation for this class was generated from the following file:

• conc_intfc/source/trig_chan_calc.vhd