behave Architecture Reference

Processes
trst_proc	( tdc_sync , clk2x )
rrst_proc	( clk2x )
tce_proc	( clk2x )
tdly_proc	( clk2x )

Signals
tdcrst_shift	std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' )
tdcrst_i	std_logic_vector ( tdcrst ' length downto 0 ) := ( others = > ' 1 ' )
runreset_q0	std_logic
runreset_q1	std_logic_vector ( 1 to 3 )
tce_cnt	std_logic_vector ( TC_CCNT_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
tce_2x_d	std_logic
tce_2x_q0	std_logic := ' 0 '
tce_2x_r	std_logic := ' 1 '
tce_2x_i	std_logic_vector ( tdcce_2x ' length- 1 downto 0 ) := ( others = > ' 0 ' )

Attributes
ASYNC_REG	string
ASYNC_REG	tdcrst_shift : signal is " TRUE "
ASYNC_REG	runreset_q0 : signal is " TRUE "
ASYNC_REG	runreset_q1 : signal is " TRUE "

Detailed Description

Definition at line 34 of file timing_ctrl.vhd.

Member Function Documentation

trst_proc()

trst_proc (   tdc_sync ,   clk2x   )

Process

This process aligns the RPC and Sctintillato TDC counters. Part of the shift register should be an SRL to reduce resource usage.

Definition at line 85 of file timing_ctrl.vhd.

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The documentation for this class was generated from the following file:

• klm_scrod/source/timing_ctrl.vhd