Belle II KLM Scint Firmware  1
implementation Architecture Reference

Signals

sig_o  std_logic := ' 0 '
sig_oq  std_logic := ' 0 '
sig_bit2  std_logic_vector ( 1 downto 0 ) := " 00 "
sig_invclock  std_logic := ' 0 '

Instantiations

map_obufds  obuftds
map_odelay  iodelay2
map_od  oddr2

Detailed Description

Definition at line 226 of file b2tt_ddr_s6.vhd.


The documentation for this class was generated from the following file: