implementation Architecture Reference

Processes
PROCESS_169	( clock )

Signals
eout6	std_logic_vector ( 5 downto 0 ) := " 111111 "
eout6m	std_logic_vector ( 5 downto 0 ) := " 111111 "
eout6p	std_logic_vector ( 5 downto 0 ) := " 111111 "
eout4	std_logic_vector ( 3 downto 0 ) := " 1111 "
eout4m	std_logic_vector ( 3 downto 0 ) := " 1111 "
eout4p	std_logic_vector ( 3 downto 0 ) := " 1111 "
rd6p	std_logic := ' 0 '
rd4p	std_logic := ' 0 '
rdplus	std_logic := ' 1 '

Aliases
din5	std_logic_vector ( 4 downto 0 ) is din ( 4 downto 0 )
din3	std_logic_vector ( 2 downto 0 ) is din ( 7 downto 5 )

Detailed Description

Definition at line 39 of file b2tt_8b10b.vhd.

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The documentation for this class was generated from the following file:

• b2tt/b2tt/b2tt_8b10b.vhd