implementation Architecture Reference

Processes
proc	( clock )

Constants
CNTLIMIT	std_logic_vector ( 7 downto 0 ) := ( not SIM_SPEEDUP ) & ( not SIM_SPEEDUP ) & ( not SIM_SPEEDUP ) & " 11111 "

Signals
sta_ttup	std_logic := ' 0 '
cnt_packet	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
buf_bcast	std_logic := ' 0 '
buf_ttpkt	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
buf_bdata	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
buf_adata	std_logic_vector ( 43 downto 0 ) := ( others = > ' 0 ' )
buf_addr	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
sig_frame	std_logic := ' 0 '
sig_frame3	std_logic := ' 0 '
sig_frame9	std_logic := ' 0 '
sta_dismask	std_logic := ' 0 '
buf_utime	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
buf_ctime	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
buf_clkfreq	std_logic_vector ( 23 downto 0 ) := x " 952980 "
cnt_utime	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
cnt_ctime	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
cnt_timer	std_logic_vector ( 3 downto 0 ) := " 0000 "
cnt_frameloc	std_logic_vector ( 10 downto 0 ) := " 10100000000 "
sig_runreset	std_logic := ' 0 '
sig_errreset	std_logic := ' 0 '
sta_running	std_logic := ' 0 '
cnt_divseq1	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
cnt_divseq2	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
buf_myaddr	std_logic_vector ( 19 downto 0 ) := DEFADDR
buf_cmd	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
reg_clkfreq	std_logic_vector ( 26 downto 0 ) := " 111 " & x " 95297f "
seq_runreset	std_logic := ' 0 '
sig_payload	std_logic := ' 0 '
sta_trgmask	std_logic := ' 0 '
buf_trgmask	std_logic := ' 0 '
sta_rstmask	std_logic := ' 0 '
buf_rstmask	std_logic := ' 0 '
sta_notagerr	std_logic := ' 0 '
buf_notagerr	std_logic := ' 0 '
sta_badver	std_logic := ' 0 '

Detailed Description

Definition at line 698 of file b2tt_decode.vhd.

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The documentation for this class was generated from the following file:

• b2tt/b2tt/b2tt_decode.vhd