implementation Architecture Reference

Processes
PROCESS_170	( clock )

Signals
rdplus	std_logic := ' 1 '
dout3	std_logic_vector ( 2 downto 0 ) := " 000 "
dout5	std_logic_vector ( 4 downto 0 ) := " 00000 "
rd_defined	std_logic := ' 0 '
bad_ein4	std_logic := ' 0 '
bad_ein6	std_logic := ' 0 '
bad_rd4	std_logic := ' 0 '
bad_rd6	std_logic := ' 0 '
expect_rd4m	std_logic := ' 0 '
expect_rd4p	std_logic := ' 0 '
expect_rd6m	std_logic := ' 0 '
expect_rd6p	std_logic := ' 0 '
rd6flip	std_logic := ' 0 '
rd4flip	std_logic := ' 0 '
rd4p	std_logic := ' 0 '

Aliases
ein4	std_logic_vector ( 3 downto 0 ) is ein ( 3 downto 0 )
ein6	std_logic_vector ( 5 downto 0 ) is ein ( 9 downto 4 )

Detailed Description

Definition at line 215 of file b2tt_8b10b.vhd.

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The documentation for this class was generated from the following file:

• b2tt/b2tt/b2tt_8b10b.vhd