RTL Architecture Reference

Processes
PROCESS_154	( USER_CLK )
PROCESS_155	( USER_CLK )
PROCESS_156	( USER_CLK )
PROCESS_157	( USER_CLK )
PROCESS_158	( USER_CLK )

Components
FDR

Constants
DLY	time := 1 ns

Signals
TX_DST_RDY_N_Buffer	std_logic
HALT_C_Buffer	std_logic
GEN_SCP_Buffer	std_logic
GEN_ECP_Buffer	std_logic
GEN_CC_Buffer	std_logic
do_cc_r	std_logic
idle_r	std_logic
sof_r	std_logic
sof_data_eof_1_r	std_logic
sof_data_eof_2_r	std_logic
sof_data_eof_3_r	std_logic
data_r	std_logic
data_eof_1_r	std_logic
data_eof_2_r	std_logic
data_eof_3_r	std_logic
next_idle_c	std_logic
next_sof_c	std_logic
next_sof_data_eof_1_c	std_logic
next_sof_data_eof_2_c	std_logic
next_sof_data_eof_3_c	std_logic
next_data_c	std_logic
next_data_eof_1_c	std_logic
next_data_eof_2_c	std_logic
next_data_eof_3_c	std_logic
tx_dst_rdy_n_c	std_logic
do_sof_c	std_logic
do_eof_c	std_logic
pdu_ok_c	std_logic
reset_i	std_logic

Instantiations
gen_cc_flop_0_i	fdr

Detailed Description

Definition at line 91 of file tx_ll_control.vhd.

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The documentation for this class was generated from the following file:

• klm_aurora/source/tx_ll_control.vhd