TrigBitsMux.vhd

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use ieee.std_logic_unsigned.all;
   use ieee.std_logic_misc.all;
library work;
   use work.conc_intfc_pkg.all;
   use work.klm_scint_pkg.all;
   use work.klm_scrod_pkg.all;
   use work.tdc_pkg.all;


entity TrigBitsMux is
   port (
      clk     : in std_logic;
      -- rst     : in std_logic;

      mode    : in std_logic_vector(3 downto 0);
      period  : in std_logic_vector(31 downto 0);
      tb_in   : in tb_vec_type; 
      
      tb_out  : out tb_vec_type
   );
end entity TrigBitsMux;

architecture behav of TrigBitsMux is

   signal i_mode  : std_logic_vector (3 downto 0);
   signal i_period : std_logic_vector (31 downto 0);
   -- counter to generate test pattern
   signal i_tst_cnt    : std_logic_vector(31 downto 0) := (others => '0');
   signal i_tst_done   : std_logic := '0';

   signal i_vectrgbits   : tb_vec_type := (others => (others => '0'));
   signal i_testtrgbits : tb_vec_type;

begin

   ------------------------------------------------
   -- generate test trg bits pattern
   ------------------------------------------------
   TEST_PROC : process(clk)
   begin
      if rising_edge(clk) then
         
         i_period <= period;

         if i_tst_cnt < i_period then
            i_tst_cnt <= i_tst_cnt + '1';
         else
            i_tst_cnt <= (others => '0');
         end if;

         if i_tst_cnt = i_period then
            i_testtrgbits <= (others => B"00001"); 
         else
            i_testtrgbits <= (others => B"00000");
         end if;
         
      end if;
   end process TEST_PROC;
   ------------------------------------------------

   ------------------------------------------------
   -- MUX for trg bits
   ------------------------------------------------
   process(clk)
   begin
      if rising_edge(clk) then
         i_mode <= mode;
         case i_mode is
            when X"1" =>
               i_vectrgbits <= tb_in;    -- daq mode
            when X"2" =>
               i_vectrgbits <= i_testtrgbits; -- test mode
            when X"3" =>
               i_vectrgbits <= tb_in; -- test mode
            when others =>
               i_vectrgbits <= tb_in; 
         end case;
      end if;
   end process;
   ------------------------------------------------

   tb_out <= i_vectrgbits;
   
end behav;