Belle II KLM Scint Firmware  1
TBScalersMux.vhd
1 library ieee;
2  use ieee.std_logic_1164.all;
3  use ieee.numeric_std.all;
4  use ieee.std_logic_unsigned.all;
5  use ieee.std_logic_misc.all;
6 library work;
7  use work.conc_intfc_pkg.all;
8  use work.klm_scint_pkg.all;
9  use work.klm_scrod_pkg.all;
10 
11 entity TBScalersMux is
12  port (
13  clk : in std_logic;
14  -- rst : in std_logic;
15  all_sca_bsy : in std_logic_vector(9 downto 0);
16  all_scalers : in scalers32_all_type;
17  chn : in std_logic_vector(3 downto 0);
18 
19  sca_busy : out std_logic;
20  scalers_chn : out slv32(9 downto 0)
21 
22  );
23 end entity TBScalersMux;
24 
25 architecture behav of TBScalersMux is
26 
27  signal i_scalers_all : scalers32_all_type;
28  signal i_scalers_all_r : scalers32_all_type;
29  signal i_scalers_all_2r : scalers32_all_type;
30  signal i_scalers_all_3r : scalers32_all_type;
31  signal i_scalers32_ch : slv32(9 downto 0);
32  signal i_scalers32_ch_r : slv32(9 downto 0);
33  signal i_scalers32_ch_2r : slv32(9 downto 0);
34 
35  signal i_chn : std_logic_vector (3 downto 0);
36 
37 
38 begin
39 
40  process (clk)
41  begin
42  if rising_edge (clk) then
43  i_chn <= chn;
44  sca_busy <= OR_REDUCE(all_sca_bsy);
45  end if;
46  end process;
47 
48  process(clk)
49  begin
50  if rising_edge(clk) then
51  i_scalers_all_r <= all_scalers;
52  i_scalers_all_2r <= i_scalers_all_r;
53  end if;
54  end process;
55 
56 
57  ASICSCA_GEN : for iasic in 0 to 9 generate
58  process(clk)
59  variable asic_sca_chn : natural range 0 to 15;
60  begin
61  if rising_edge(clk) then
62  asic_sca_chn := to_integer(unsigned(i_chn));
63  i_scalers32_ch(iasic) <= i_scalers_all_2r(iasic)(asic_sca_chn+1);
64  end if;
65  end process;
66  end generate ASICSCA_GEN;
67 
68  process(clk)
69  begin
70  if rising_edge(clk) then
71  i_scalers32_ch_r <= i_scalers32_ch;
72  i_scalers32_ch_2r <= i_scalers32_ch_r;
73  scalers_chn <= i_scalers32_ch_2r;
74  end if;
75  end process;
76  ------------------------------------------------
77 
78 end behav;