2 use IEEE.STD_LOGIC_1164.
ALL;
3 use IEEE.NUMERIC_STD.
ALL;
4 use IEEE.STD_LOGIC_MISC.
ALL;
5 use IEEE.STD_LOGIC_UNSIGNED.
ALL;
29 ch_mask : in slv15(4 downto 0) := (others=> (others=>'0'));
30 new_mask : in slv15(4 downto 0) := (others=> (others=>'0'));
31 thr_chk_busy : in := '0';
33 -- wires to PedestalFetcher 34 fetch_ena : out := '0';
35 fetch_ack : in := '0';
36 asic_addr : out (2 downto 0) := (others => '0');
37 chan_addr : out (3 downto 0) := (others => '0')--; 38 -- ped_win_samp_start : out std_logic_vector(13 downto 0) 45 type pedestal_queue_state_machine is ( 53 signal ped_queue_state : pedestal_queue_state_machine := IDLE;
55 signal ena_i : (1 downto 0) := "00";
56 signal thr_chk_busy_i : (1 downto 0) := "00";
57 -- signal asic_mask_i : std_logic_vector(4 downto 0) := (others => '0'); 58 signal not_done : := '0';
59 signal not_done_v : (4 downto 0) := (others=>'0');
60 signal ch_mask_i : slv15(4 downto 0) := (others=> (others=>'0'));
61 signal new_mask_rdy : := '0';
65 process(clk, ch_mask_i, ena_i)
67 if rising_edge(clk) then 68 for asic in 0 to 4 loop 69 not_done_v(asic) <= or_reduce(ch_mask_i(asic));
71 not_done <= or_reduce(not_done_v) or or_reduce(ena_i);
76 edge_det:
process(clk, ena, thr_chk_busy)
78 if rising_edge(clk) then 79 ena_i <= ena_i(0) & ena;
80 thr_chk_busy_i <= thr_chk_busy_i(0) & thr_chk_busy;
85 process(clk, thr_chk_busy_i, ch_mask, new_mask, ped_queue_state)
87 if rising_edge(clk) then 88 if thr_chk_busy_i = "10" then 90 elsif ped_queue_state = IDLE then 93 new_mask_rdy <= new_mask_rdy;
99 pedestal_fetching_queue :
process(clk, ena_i, ch_mask_i, not_done, ch_mask, new_mask)
100 variable int_asic : range 0 to 4;
101 variable int_chan : range 0 to 14;
103 if (rising_edge(clk)) then 105 ped_queue_state <= IDLE;
107 case ped_queue_state is 110 ch_mask_i <= ch_mask;
111 if (ena_i = "01") then 113 ped_queue_state <= ASIC_LOOP;
116 ped_queue_state <= IDLE;
120 if new_mask_rdy = '1' then 121 update_ch_mask : for i in 0 to 4 loop 122 ch_mask_i(i) <= ch_mask_i(i) and new_mask(i);
125 ped_queue_state <= ASIC_LOOP;
128 if not_done = '1' then 130 if or_reduce(ch_mask_i(i)) = '1' then 131 asic_addr <= (to_unsigned(i, 3));
136 ped_queue_state <= CHAN_LOOP;
139 ped_queue_state <= IDLE;
144 if not_done = '1' then 145 for j in 0 to 14 loop 146 if ch_mask_i(int_asic)(j) = '1' then 147 chan_addr <= (to_unsigned(j, 4));
152 ped_queue_state <= WAIT_ACKNOWLEDGE;
155 ped_queue_state <= IDLE;
159 when WAIT_ACKNOWLEDGE => 160 if not_done = '1' then 162 if fetch_ack = '1' then 164 ped_queue_state <= WAIT_DONE;
166 ped_queue_state <= WAIT_ACKNOWLEDGE;
170 ped_queue_state <= IDLE;
175 if not_done = '1' then 176 if fetch_ack = '1' then 177 ped_queue_state <= WAIT_DONE;
179 ch_mask_i(int_asic)(int_chan) <= '0';
180 ped_queue_state <= CHECK_UPDATE;
184 ped_queue_state <= IDLE;
### PedFetchQueue Begins pedestal fetching with same asic/chan priority as ShiftOutWindow. If other bus us using PedestalFetcher, this module waits for it's turn. If ThresholdCheck is finished, the internal channel mask is updated with the new channel mask.If this happens while this module is waiting for it's turn to use PedestalFetcher, then it goes back and checks the mask again so as to not fetch pedestals for an unhit channel.