KLMHitBuilder.vhd

----------------------------------------------------------------------------------
-- The module to build hits in the "simple" mode.
-- Simple mode is a mode when only trigger bits from TargerX are processed without feature extraction.
-- 
-- 
-- * DAQ data format:
-- * ------------------------------------------------------
-- * word1 : | type(2:0) | lane(4:0) | axis(0) | chnl(6:0) |
-- * word2 : |              ctime(15 : 0)                  |
-- * word3 : | TRGBITS(4:0)      |      TDC(10:0)          |
-- * word4 : | TBD(3:0)    | chg(11:0)                     |
-- * ------------------------------------------------------
--
-- In the simple mode chg = 0, TDC = ctime(10:0)
----------------------------------------------------------------------------------

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use ieee.std_logic_unsigned.all;
library unisim;
   use unisim.vcomponents.all;
library work;
   use work.conc_intfc_pkg.all;
   use work.klm_scint_pkg.all;
   use work.klm_scrod_pkg.all;
   use work.tdc_pkg.all;


entity KlmHitBuilderSimple is 
   port (
      clk         : in std_logic;
      rst         : in std_logic;
      
      enable      : in std_logic;                      -- enable to switch between different readout modes (dummy, simple, full) 

      hit_num_max : in std_logic_vector(15 downto 0);  -- maximum number of hits to be processed

      trgbit_hit_arr  : in slv41(9 downto 0);           -- timestamped hit data from KLMTrigBitsProc
      hits_valid   : in std_logic_vector(9 downto 0);  -- corresponding ASIC has valid hits
      tbfifo_drdy   : in std_logic_vector(9 downto 0);  -- data is ready on the tb processing side

      localtrg     : in std_logic;                     -- trigger after trigger buffering
      ctime_trg    : in std_logic_vector(15 downto 0); -- trigger timestamp

      ser_busy     : in std_logic;  -- serialization is in progress
      nxt          : in std_logic;  -- input from serializer which say that it's ready to accept next hit

      ser_run      : out std_logic; -- start serialization

      hit_read     : out std_logic_vector(9 downto 0); -- read enable to KLMTrigBitProc
      
      -- hit data out
      HitData      : out KlmScrodHitDataType;          -- hit data in DAQ data format

      occ_err_cnt  : out std_logic_vector(15 downto 0); -- number of hits overflow counter


      evt_rdy      : out std_logic;                     -- event is ready to be sent to the DAQ
      trg_proc_cnt : out std_logic_vector(15 downto 0); 

      busy         : out std_logic                      -- event is being processed 
   );
end KlmHitBuilderSimple;

architecture behavioral of KlmHitBuilderSimple is

   type ro_states is 
   (
      IDLE, WAIT_VALID, PREPARE, SEND_HITS, NEXT_HIT, WAIT_SENT, STOP
   );
   signal ro_state : ro_states := idle;

   type modes_t is 
   (
      DUMMY, DAQ_OR_TEST, NONE
   );


   signal hit_num           : natural;
                            
   signal run               : std_logic;

   --number of asic being analyzed
   signal i_asic            : integer range 0 to 9 := 0;
   signal i_asic_next       : integer range 0 to 9 := 0;

   -- all asics are processed
   -- signal i_asic_finished   : std_logic;

   -- maximum number of hits in the event
   signal i_hit_num_max     : std_logic_vector(15 downto 0) := (others => '0');
   signal hit_num_max_dummy : std_logic_vector(15 downto 0) := (others => '0');

   signal i_hit_ren         : std_logic_vector(9 downto 0) := (others => '0');

   signal axis              : std_logic;
   signal chn               : integer;
   -- signal chn_r             : integer;
   signal asic_chn          : integer;
                            
   -- hit data words        
   signal null_hit_daq      : std_logic := '0';
   signal last_hit_daq      : std_logic := '0';
   signal word1_daq         : std_logic_vector(15 downto 0);
   signal word2_daq         : std_logic_vector(15 downto 0);
   signal word3_daq         : std_logic_vector(15 downto 0);
   signal word4_daq         : std_logic_vector(15 downto 0);
      
   signal i_trg_proc_cnt    : std_logic_vector(15 downto 0) := (others => '0');
                            
   signal i_occ_err_cnt     : std_logic_vector(15 downto 0) := (others => '0');
   signal i_ro_mode         : std_logic_vector(3 downto 0)  := (others => '0');
      
begin

   process (clk)
   begin
      if rising_edge(clk) then
         i_hit_num_max <= hit_num_max;
      end if;
   end process;

   ------------------------------------------------
   -- determine asic number to process next
   ------------------------------------------------
   process(clk)
   begin
      if rising_edge(clk) then
          i_asic_next_loop : for i in 0 to 9 loop
              if i /= i_asic and hits_valid(i) = '1' then
                  i_asic_next <= i;
                  exit i_asic_next_loop;
              end if;
          end loop;
         -- if i_asic < 9 and hits_valid(i_asic + 1) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 1;
         -- elsif i_asic < 8 and hits_valid(i_asic+2) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 2;
         -- elsif i_asic < 7 and hits_valid(i_asic+3) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 3;
         -- elsif i_asic < 6 and hits_valid(i_asic+4) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 4;
         -- elsif i_asic < 5 and hits_valid(i_asic+5) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 5;
         -- elsif i_asic < 4 and hits_valid(i_asic+6) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 6;
         -- elsif i_asic < 3 and hits_valid(i_asic+7) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 7;
         -- elsif i_asic < 2 and hits_valid(i_asic+8) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 8;
         -- elsif i_asic < 1 and hits_valid(i_asic+9) = '1' then
         --    i_asic_finished <= '0';
         --    i_asic_next <= i_asic + 9;
         -- else 
         --    i_asic_next <= i_asic;
         --    i_asic_finished <= '1';
         -- end if;
      end if;
   end process;
   ------------------------------------------------


   ------------------------------------------------
   -- read enable for trg bit hits
   ------------------------------------------------
   process(nxt, i_asic, localtrg)
   begin
      i_hit_ren <= (others => '0');
      i_hit_ren(i_asic) <= nxt; 
   end process;
   hit_read <= i_hit_ren;
   ------------------------------------------------


   ------------------------------------------------
   --- state machine for readout
   ------------------------------------------------
   process(clk)
   begin
      if rst = '1' then
         ro_state <= IDLE;
         i_trg_proc_cnt <= (others => '0');
         hit_num <= 0;
         run <= '0';
         evt_rdy <= '0';
         i_asic <= 0;
         i_occ_err_cnt <= (others => '0');
      elsif rising_edge(clk) then
         

         case ro_state is

            when IDLE =>
               hit_num <= 0;
               run <= '0';
               evt_rdy <= '0';
               busy <= '0';
               i_asic <= 0;

               -- check trg fifo empty flag
               if enable = '1' and localtrg = '1' then
                  busy <= '1';
                  -- increment counter for processed triggers
                  i_trg_proc_cnt <= i_trg_proc_cnt + '1';
                  -- change state 
                  ro_state <= WAIT_VALID;
               end if;

            -- wait until event data is valid
            when WAIT_VALID =>
                  if tbfifo_drdy = B"1111111111" then
                     ro_state <= PREPARE;
                  end if;

            when PREPARE =>
               -- determine first asic to be processed
               set_i_asic_loop : for i in 0 to 9 loop
                   if hits_valid(i) = '1' then
                       i_asic <= i;
                       exit set_i_asic_loop;
                   end if;
               end loop;
               -- if hits_valid(0) = '1' then
               --    i_asic <= 0;
               -- elsif hits_valid(1) = '1' then
               --    i_asic <= 1;
               -- elsif hits_valid(2) = '1' then
               --    i_asic <= 2;
               -- elsif hits_valid(3) = '1' then
               --    i_asic <= 3;
               -- elsif hits_valid(4) = '1' then
               --    i_asic <= 4;
               -- elsif hits_valid(5) = '1' then
               --    i_asic <= 5;
               -- elsif hits_valid(6) = '1' then
               --    i_asic <= 6;
               -- elsif hits_valid(7) = '1' then
               --    i_asic <= 7;
               -- elsif hits_valid(8) = '1' then
               --    i_asic <= 8;
               -- elsif hits_valid(9) = '1' then
               --    i_asic <= 9;
               -- end if;
               ro_state <= SEND_HITS;
            
            when SEND_HITS =>
               -- initiate transaction
               run <= '1';
               ro_state <= WAIT_SENT;
               evt_rdy <= '1';

            when NEXT_HIT =>
               ro_state <= WAIT_SENT;

           -- wait until hit data is sent  
            when WAIT_SENT =>
               evt_rdy <= '0';

               -- ready to serialize next hit data
               if hits_valid(i_asic) = '0' then
                  i_asic <= i_asic_next;
               end if;
               if nxt = '1' then
                  hit_num <= hit_num + 1;
                  --if last_hit_daq = '0' then
                     --ro_state <= NEXT_HIT;
                  --end if;
               end if;

               if last_hit_daq = '1'  then
                  ro_state <= STOP;
               end if;

            when STOP =>
                  run <= '0';
                  evt_rdy <= '0';
                  if ser_busy = '0' then
                     ro_state <= idle;
                     if hit_num = i_hit_num_max then
                        i_occ_err_cnt <= i_occ_err_cnt + 1;
                     end if;
                  end if;
         end case;
         
      end if;

   end process;
   
   trg_proc_cnt <= i_trg_proc_cnt;
   
   ser_run <= run;

   -- hit data
   axis <= '0' when i_asic <= 4 else '1';
   asic_chn <= to_integer(unsigned(trgbit_hit_arr(i_asic)(30 downto 27)));

   -- calculate channel number
   with i_asic select chn <=
      -- axis = 0
      asic_chn when 0,
      asic_chn + 15*1 when 1,
      asic_chn + 15*2 when 2,
      asic_chn + 15*3 when 3,
      asic_chn + 15*4 when 4,
      -- axis = 1
      asic_chn + 0 when 5,
      asic_chn + 15*1 when 6,
      asic_chn + 15*2 when 7,
      asic_chn + 15*3 when 8,
      asic_chn + 15*4 when 9;

   -- process(clk)
   -- begin
   --    if rising_edge(clk) then
   --       chn_r <= chn;
   --    end if;
   -- end process;

   -- mark first hit in the packet
   HitData.first_hit <= '1' when hit_num = 0 else '0';

   word1_daq <= X"80" & axis & std_logic_vector(to_unsigned(chn,7)); -- X"80" marks scintillators hits for DataConcentrator
   -------------------------------------------------------------------------
   -- make hit data for DAQ/TEST modes  
   -------------------------------------------------------------------------
   process(trgbit_hit_arr, hits_valid, ctime_trg, hit_num, i_asic, null_hit_daq, last_hit_daq)
   begin
      word2_daq <= trgbit_hit_arr(i_asic)(15 downto 0); -- ctime
      word3_daq <= trgbit_hit_arr(i_asic)(31 downto 27) & trgbit_hit_arr(i_asic)(10 downto 0); -- trg bits & ctime
      word4_daq <= B"0000_0000_0000_0000"; 

      -- send null hit if there is no triggered channels
      if hits_valid = B"0000_0000_0000_00" then
         null_hit_daq <= '1';
      else 
         null_hit_daq <= '0';
      end if;

      -- mark last hit in the packet
      if hits_valid = B"0000_0000_00" or hit_num = i_hit_num_max then
         last_hit_daq <= '1';
      else 
         last_hit_daq <= '0';
      end if;


   end process;
   occ_err_cnt <= i_occ_err_cnt;
   -------------------------------------------------------------------------

   HitData.word1 <= word1_daq;
   HitData.word2 <= word2_daq;
   HitData.word3 <= word3_daq;
   HitData.word4 <= word4_daq;
           
   HitData.null_hit <= null_hit_daq;
   HitData.last_hit <= last_hit_daq;



end behavioral;