my notes on using the zynq in no particular order:

obsolete / for reference:

• fattest kintex draws 1.4 A @ 1 V quiescent
• kurtis wants the XC7Z045-1FFG900C (ARM + Kintex-7 version), which are $1600 each on digikey; equivalent kintex is ~$1000-$1200, equivalent virtex is ~$2500
• PS = processing system
• PL = programmable logic
• HR (high range, no DCI; ug471 page 15)
• HP (high performance, 1.2-1.8V only, includes DCI); ug585 page 585 says only the HP banks have odelays
• ODELAY in 7-series HP banks only (probably want this for SST and other critical signals)
• need 1V and 1.8V supplies
• Global CLK max speed is 625 MHz (ds191, page 55)
• Region CLK max speed is 450 MHz
• ug470 page 13 says the artix 100 needs 31Mbits for configuration
• don't have to connect VCCO for unused banks... http://www.xilinx.com/support/answers/11906.htm

things that have been taken into consideration:

• power supply sequencing info is in ds191 page 8 - SCROD revB "voltage regulators" sheet
• power-on surges listed in ds191 page 9 - SCROD revB "voltage regulators" sheet
• VccPLL from same reg as VccPAUX (ds191 page 8) - SCROD revB "voltage regulators" sheet
• might have to boot just PS first, and then let the PL get powered on in stages
• ug933 pages 13-14 say what caps to use
• PS supply ordering:
  1. vcc_pint (1V; 192 mA at boot; LTC3025)
  2. vcc_pll and vcc_paux (1.8V; 53 mA at boot; should be from same regulator; LT3025)
  3. vcco_mio0 and vcco_mio1 and vcco_ddr (mio=1.8V to 3.3V; ddr=1.2V to 1.8V; 524+ mA at boot)
• PL supply ordering:
  1. Vcc_int (1V; 2011 mA at boot; LT3083)
  2. Vcc_bram (1V; 113 mA at boot; LT3025)
  3. Vcc_aux (1.8V; 191 mA at boot; LT3025)
  4. Vcc_auxio (1.8V; 402 mA at boot; LT3025?)
  5. Vcc_o (1.2V, 1.8V, 2.5V, 3.3V; 940 mA at boot; could be split between HP and HR, or further as necessary)
  6. Vcc_mgta (1V; ?; LT3025?)
  7. Vtt_mgta (1.2V; ?; must be after Vcc_mgta is up; LT3025?)
  8. Vcc_mgtaux (1.8V; ?; order doesn't matter; LT3025?)
• the 5 VCC_PINT + 5 VCC_INTs draw 7.555 A at power-on, so if we deliver 1.3V to the boardstack for the 1V regulators, we waste 2W (in the boardstack); if we deliver 3V for this purpose, we waste 15W (in the boardstack)
• need ISE 14.3 for kintex (ds182 page 12) - install vivado
• need ISE 14.5 for the zynq 7Z045 (or vivado 2013.1) (ds191 page 15) - install vivado
• FPGA choice:
  • 127.21 MHz is acceptable for all kintexes for the gtp (pdf page 48) (ug476 page 47 says cpll can go up to 127.21 MHz * 5 * 5 / 1 / 1 = 3180.25 MHz) (coregen allows putting in 3.1802 Gpbs and getting 127.208 MHz as the refclock) (ug476 page 54 says qpll can go up to 6.3 Gbps)
  • can use oserdes in each single-ended signal for 8 bit high-speed shift register (or 14 bits for a differential pair?!?) to write to WR_ADDR replacement (950 MHz; ds191 page 33)
  • should use iserdes for each ASIC data out LVDS pair
  • need 30 to 60 MHz clock input for ARM (ds191 page 18)
  • I2C and SPI built-in to zynq, as is SD
  • PLLs need 19-800 MHz input (fine with FTSW clock; ds191 page 58)
  • PS MIO source/sink current listed in ds191 page 10 (8 mA both)
  • PL source/sink currents by IO type is in ds191 page 11
• SCROD revB:
  • use vertical JTAG connector and assume it won't be used unless outside the detector
  • use vertical USB connector
  • need to find an inductor that works at 1.5T - use a 5 Ohm resistor
  • the zynq temp monitoring pins should be connected to the built-in ADC
  • the internal voltages can be monitored by the internal ADC directly without using dedicated analog inputs
  • ug865 says "Some FB/FBG packages include VCCAUX_IO pins, but they are not utilized by the I/O. These pins are placeholders to ensure pin compatibility with FF/FFG packages. In the FF/FFG packages, if the high-performance option is chosen for the HP I/O, the VCCAUX_IO pins must be connected to a power supply separate from VCCAUX. Therefore, if there are plans to migrate to FF/FFG packages, VCCAUX_IO must be connected to the appropriate voltage regulator."
  • can we get a diff pair in between FPGA balls? (with 4 mil trace/space?)
  • add a connector for the HV board temp monitoring (i2c)
  • ug476 page 37 suggests we can't use a GTP clock generated from internal logic without driving the diff_pair onto the PCB first
  • ug476 page 307 has good tips on GTP power supply and AC coupling and termination resistor choices/placement
• ds191 page 58 has the PLL jitter spec, but it doesn't give a number... Apparently, the coregen spits that out for you.
• ARM software: ug585 page 677 suggests using 128 bit aligned data in memory for best throughput
• ug821 page 29 says the PS FSBL must program the PL
• ug585 page 183-185 says that the PS need not be booted to use PL in JTAG mode
• ug585 page 187 says the zynq PL behaves like a 7 series FPGA if JTAG split mode is enabled
• ug585 page 315 shows a schematic of how to hook up the QSPIs in parallel
• http://www.wiki.xilinx.com/Prepare+Boot+Medium says there's a dip switch setting to use the digilent jtag programmer
• http://www.xilinx.com/support/answers/47500.html says to use 128Mb QSPI devices (2 in parallel is okay)
• ug470 page 20 says what pins to use for Master SPI x4 mode
• ug470 page 101 says the deviceDNA is not necessarily unique
• ug585 page 144: When the system boots in non-secure JTAG mode, the primary CPU halts execution by executing a WFE instruction. The JTAG connections are explained in Chapter27, JTAG and DAP Subsystem.
• ug146 page 146: configuration via JTAG requires the PL is powered but the flowchart on page 150 says that it never checks that unless secure boot mode is selected
• steps to power zynq in benchtop mode:
  1. provide a 30-60 MHz clock
  2. assert mode[4:0] and vmode[1:0] signals as desired (ug585 page 147)
  3. de-assert PLL enable
  4. release PS_SRST_B
  5. provide vcc_pint
  6. provide vcc_pll and vcc_paux
  7. wait ? ms, but not more than 500 ms
  8. provide vcco_mio0 and vcco_mio1 and vcco_ddr
  9. release PS_POR_B to allow it to POR (ug585 page 146)
  10. init_b goes low if there is a problem executing the internal bootrom
• steps to power zynq in remote JTAG programming mode (ug585 page 182 has a flowchart for JTAG cascaded boot):
  1. power both PS and PL
  2. ...
• if one of the Vcc_o (or Vcc_mio) banks is at 3.3V, there can be no more than 500 ms between the _aux power and the _o power being provided, or there will be blood (ds191 page 8) - a good (?) reason to stay away from 3.3V?
• zc706 schematic page 49 has the power controller - perhaps its worth scoping out the board upon power up?; the regulators are on page 50-57