interconnect revD
already done or obsolete:
carrier13 revD
already done or obsolete:
carrier02 revD
already done or obsolete:
- re-check each GPIO to make sure we're not assuming a weak pullup (since none exists in the 9534) (none of the inputs to GPIO0 or GPIO1 are relying on a pullup; the inputs to the demux, samp_sel_any and the column select lines will be undefined until GPIO2 gets programmed, which is okay; amp_disable has its own pullup; the regulator shutdowns have their own pulldowns)
- use 16 bit DAC in 20 pin package (ltc2657) [seems to be the same digital guts as the ltc2637]
- plate the edges of the mmcx slot so it can be held more securely, and maybe put exposed pads on the bottom so the solder joint can be stronger
- add more signals that go up the boardstack
- put 3V 4V 5V on silkscreen for power connector
- add at least 4 GPIO pins to each carrier level
- fix two 3V offpages on J7 (either get rid of them, or if have new interconnect board in-hand, add more in): added more in, also 5V
- replace all SMA connectors with MMCX
- determine best filter for VadjN and VadjP for next version of carrier (external DAC pin to 10 Ohm series to ASIC pin to 200pF+47nF+1uF in parallel to GND seems pretty good)
- shrink the cutouts for the 16 pin connectors' nubs by about a factor of 2. shrink the gap for the plastic housing as well, and extend the board forward if necessary on sides (back if necessary for SMA connector bodies in middle) [perhaps skip this and put pogo pins down instead? - can land on front-back rectangular landing pads and front-back can omit connectors, but need mounting bracket to hold them together]
- put keepout on top/bottom for traces underneath/above 100/120 pin connectors to help autorouter (and manually fix routes on top/bottom)
- put more copper planes everywhere to help with thermal conduction to the sidewalls
- make soldermask strips 2.5 mm wide (wider boards modify this change, but keep 0.5 mm extra soldermask relative to thermal contact)
- get rid of MON1 and MON2 (they are no longer connected as of interconnect revC; exchange one for SPARE/R25; already used for \LDAC but overloaded anyway - one spare mon pin: connect this to some signal we want to see?)
- use shutdown-able regulator for ASIC and wire the shutdown to a GPIO pin (and pull it to active)
- minor changes from current version / old183 (relative to shipped version) - no idea what this meant... - perhaps it was the assembly drawing...
- don't ask them to plate the mmcx cutouts completely next time
- ensure there's soldermask between ASIC pins, 100/120 pin connectors and the DAC, and the multiplexers (use 0.0508 (2 mil) soldermask oversize relative to pad)
- cutout for power connector nub
- for a later incarnation, the board-to-board connectors can be closer together (since they will be machine-assembled) - or perhaps further apart
- extend board width to 110 mm (from 100 mm) and add through-holes to accept new integrated thermal wall concept
- put 5V regulator down?
- rename nets as follows:
- original names on carrier02/carrier13:
- J4_097_AC26.J4_101_AA26
- J4_101_AA26.J4_097_AC26
- J4_091_AF23.J4_099_AB26
- J4_099_AB26.J4_091_AF23
- new names for carrier02/carrier13:
- J4_097_AC26.J4_091_AF23
- J4_101_AA26.J4_099_AB26
- J4_091_AF23.J4_097_AC26
- J4_099_AB26.J4_101_AA26
SCROD
already done or obsolete:
- needs insulating tape placed under the interconnect connectors (remember this when asking for PCB assembly) - get rid of vias under 100 pin connectors
- overload LEDs with cypress data bus (with firmware that leaves the state of the bus in the desired LED state unless a USB transaction is being performed) - obsolete if using zynq
- doublecheck that all cypress IOs are needed (against Xin's reference design) - maybe obsolete
- use cypress fx3 for usb3 (arm9) - skip it and use a zynq
- make soldermask/thermal wall thing be 7.5 mm (like on the c02/c13 revsD) because thermal wall holes are clearance holes
- move configuration mode pins to separate schematic symbol (HSWAP, M0, M1, SPI, JTAG, suspend, fuse, batt, program, done, init, etc) - moved to top of each gate
- use ENIG plating
- find more robust dip switches (and make it a bank of 5 instead of three that are 2-pins each)
- add test points for power via USB (need a custom jumper wire to accomplish this, as it is bad to do so normally)
- add at least one lemo connector for trig in/out
- reduce power consumption everywhere possible (this may conflict with some of the above) - obsolete (BURN IT!)
- add LEMO-00 connector on SCROD or somewhere on boardstack to allow generic in/out (perhaps for trigger in/out) (behind/on top of mini-usb connector?)
- ensure there's soldermask between ASIC pins, 100/120 pin connectors and the DAC, and the multiplexers (use 0.0508 (2 mil) soldermask oversize relative to pad)
- two more DIP switches - one for remote/local clock, and the other for removing the eeprom data line from being connected to the cypress on power up (or at least throw the jumper back into this position)
- add a GPIO and some DIP switches for general purpose (mode select) inputs - this would potentially recover the ability to drive the oscillator enables if it's a 2.5V GPIO
- add silkscreen for board # sticker
- add a power input connector so there can be SCROD sans interconnect / _MB (not sure about this one - interconnect revC has a jumper to disable the voltage regulators for SCROD, so this is potentially not a conflict)
- CJ7 is way too close to the fiber cage (fix fiber cage silkscreen to show conflict and move cap)
- should delete the silkscreen for the mounting holes - PCB universe moved it from the center of the hole to just outside
- move reset button 0.2 mm closer to edge of board, or use side-entry model (SW1022CT-ND)
- fix the FET controlling the LEDs
- extend boards to be 110 mm * 86 mm and put 16mil thermal vias everywhere and #6 clearance holes with same pattern as carrier02 revC (doublecheck position of holes before submitting board)
flaws in SCROD revA / features to add for revA2/revB
still to do (flaws in SCROD revA / features to add for SCROD revA2 / revB):
- the wrong cypress eeprom package was installed on SCROD revA2 #13-#26; it is effectively wired wrong (took pinout from x-rotated package on datasheet, but installed normal part) - on SCROD #13, rotated part 90 degrees and soldered flying wires and it is capable of being programmed and booting up as the correct USB device VID/PID
- the correct component corresponding to the layout of the board is available from many distributors: octopart 24lc64x
- flood over stitching vias on all gnd layers (use pad stack thermal "flood over vias" instead of adding copper rectangles to the layers)
- add grooves so boards can be captured by set screws in aluminum walls
- verify it's okay to have both fibers on the same dual before shipping the board and that they don't each need a separate clock input
- put Geometry.Height, Cost, digikey part #, size / package, and Part Number in attributes for each part to make BOM generation smoother
there is more information on SCROD here and here.
already implemented on SCROD revA2 or are otherwise no longer problems (2012-03-26 to 2012-05-01):
remote jtag does not seem to work - a strangely wired cable is required to rectify this (TMS=3,6 are wired straight through; 1,2 4,5 7,8 must be wired as crossover) (pretty sure this is wrong, depending on the source of the JTAG signals - for FTSW, a regular ethernet cable is right)
as of 2012-03-26:
- the FPGA configuration PROM is grossly undersized for holding the full potential of configurability (ug380 page 69 says it needs 33,761,696 bits and ug161 page 21 says the spartan6 150T needs a 32M + an 08M PROM) - a temporary workaround is to use compression when generating the .mcs file - however, SCROD revA is not wired to allow that to happen (CLKOUT from the PROM goes nowhere)
- determine best way to store/load FPGA program - this is likely not the way we've been doing it (64Mbit SPI in nibble mode)
- the TPS3828 is wired wrong, so that it shorts power to ground - removed
- add through-hole test point for ground
as of 2012-03-27:
- add pull-ups / downs to M0 and M1 just in case
- rewire IFCLK to cypress to go to a GCLK so synchronous mode will work
- the FAN1112S has a minimum load requirement of 10mA, so a 105 Ohm resistor should be placed in parallel with CG13 to guarantee this (it is also not recommended for new designs, so we should pick a new part - TI TLV70212DBVT)
- power A1.2 for MGT a different way (right now, it's from the D3.3V from interconnect) now it's from D2.5V (regulator needs 2V min)
as of 2012-03-28:
- revA has the wrong interconnect connector part names (we need the +5mm version of the same connector - the schematic was annotated before batch 2 was submitted to indicate which connecters were to be used) - unclear whether to change the part name in the schematic, as the assembled part might be different based on project - done by making part # visible and not part name
- might want to use a shielded RJ45 connector pair next time
- renumber capacitors and resistors so RP1-15 are all 10k, etc
- the hole pattern in the middle of the double-wide fiber transceiver has holes that are too small
as of 2012-04-30:
- the above fixes for revB were backported to the revA2. Additionally, the following fixes were made:
- the 100uF caps on the bottom of SCROD are 2.58mm tall; should look for shorter caps (1.5mm-ish?) or place them on the top side
- the LEDs should have a jumper to activate them (so that accidental FPGA deprogramming while in Belle II will not damage the PMT photocathodes)
- wire oscillator enable pins to FPGA to allow for sense, along with possibility for control (done for 156, but not 250)
- maybe add mounting holes and standoffs so it won't short out when on a metal table (2 out of 4 placed so far)
- it might be better to use dip switches instead of jumpers in some places
- there should be a reset button to reprogram the FPGA (PROG_B)
- the edges should be plated to assist in thermal coupling to the aluminum walls
- JTAG signals are referenced to VCCAUX (2.5V on SCROD revA; S3=3.3V and V5=2.5V on FTSW), but the SN65LVDT14 runs on 3.3V, so ??? (-1L devices require 2.5V on VCCAUX ds162 page 10) (differential termination is a well-controlled 100 Ohms when vccaux=3.3V ug381 page 14, but will still work for 2.5V) (ucf should have 'config vccaux = "<2.5/3.3>"' ug381 page 37) (2.5V or 3.3V okay for vccaux for lvds_25 and lvds_33 ug381 page 41) (DSP_cPCI's JTAG signals (FPGA, PROM, Header) are all 2.5V) (spartan-3a digilent board has all 3.3V JTAG/VCCAUX) - fixed with a level converting quad 2 input multiplexer (74VHC157)
- maybe swap the two RJ45 connections so JTAG is next to JTAG?
- consolidate i2c for spare EEPROM with temperature sensors
- there should be a temperature sensor on SCROD, near the FPGA
- pick a better temperature sensor that's easier to solder and put some on SCROD
- add surface mount test points for all other voltages
- there should be better indication of which RJ45 connector is which for the next revision
- renumber capacitors and resistors so RP1-15 are all 10k, etc
- make cutout for fiber transceiver smaller / more appropriate
after a design review on 2012-05-01, the following changes were also made:
- doublecheck i2c address conflicts for temperature sensor vs e2prom
- add warning on schematic about not driving CSO_B (AF3) low during normal operation
- wire event output on temperature sensor to FPGA pin
- protect osc enable pins from getting full 3.3V (resistive divider)
- test QSPI mode with modified revA SCROD (successful)
- remove all top layer traces from fiber cage region where the soldermask might eventually fail (added keepout, too)
- reroute CLKOUT to a GCLK
boardstack
to be done still for interconnect revC:
- make the thermal spokes beefier on the power connector
- add the same mechanical accordion mitigation mounting holes as on the new carrier levels and the interconnect board
- doublecheck the silkscreen for the voltage test points
already implemented on carrier0 revB (2012-05-03 to 2012-05-14; but still need to be implemented for other carrier levels):
- carrier0: short analog and digital grounds together
- add shielding around and in between RF signals (attempt to make traces 50 Ohms impedance)
- the edges should be plated to assist in thermal coupling to the aluminum walls (along with appropriate stitching vias that are flooded over)
- add thermal holes and big rectangle of missing soldermask on all carriers (top and bottom layers)
- thicker traces for power (11.81 mils instead of 5)
- shrink pad size for 16 pin connectors
- add mechanical support so the boardstack is no longer an accordion (added some holes; problem shipped to the future)
- carrier0: add monitor header pins (from carrier3 that never got fabbed; remove them from carrier3 and include CAL signal that now goes nowhere J2_031_AA15)
- add board notches for 16 pin 2mm connectors for positive registration
- there should be one temperature sensor per carrier level (and it should be well thermally coupled to the heat generators)
- add voltage test points on carrier levels for raw voltage
- change silkscreen on 100/120 pin connectors so it's very clear where pin 1 is
- properly label carrier level numbers (0-3)
- place voltmeter on each carrier level to allow for automatic sense/adjust of Vraw on whole stack (make sure to get one that has 4 possible addresses, since they will all be on the same bus) (ug381 page 44 and ds162 page 2 say that any pin can handle 3.95V)
already implemented on IRS2_DC revB2 (the one without amplifiers):
- the AP7333-25SAG-7 (a 300mA 2.5V regulator) on the revB was responsible for providing approximately 414mA... (replaced with an ADP3888-25, which is capable of providing an amp)
- remove the amplifiers and associated nonsense from the front-end, and reroute the RF traces so they have isolation
- merge powers and grounds
- add thermal holes where possible (the nine, as well as the four)
- add SMA connection pads for bench testing / calibration
- added test points for all voltages
- there should be one temperature sensor per ASIC (the same one as on SCROD and carrier0)
- replace R1-R4 with solder blobs
- add a gnd test point for the scope probe
- add the option to use a resistor to set Isel current instead of a DAC output
- reduced size of extra soldermask past pad from 2.5 mils from 5 mils (to help isolate nets when soldering blobs, etc)
- fabricating 256 boards as tab-routed panels of 4x4 boards (with a 1cm border on all sides)
- asking for an 8 mil thick stainless steel stencil that has no holes for the test points, the SMA pads nor the solder blobs (except for S5, which we want shorted)
other
other: