mza's notes on cadence

These instructions were written 2010-2012 for Cadence with the IBM 130nm design kit "cmrf8sf" / MOSIS "8rf-dm". These instructions assume you're using bash as your shell. This was last updated 2012-07-30 and is known to be valid for Cadence Virtuoso version IC6.1.4-64b.500.11.

setting up microsoft windows to run cadence remotely:

install xming
install xming-fonts (otherwise the help browser will be wingdings-ish)
install putty (make sure you forward X sessions)

setting up cadence:

copy the design kit setup files to your local dir (recommend something like ~/asic/design-kits):
```
cp -ar /opt/cadence/designKits/setupFiles/IBM_Latest_IC614/ .
			
```
where Latest refers to the IBM design kit number and IC614 refers to Cadence version 6.

create a script in ~/bin along the lines of this:

#!/bin/bash -e
cd ~/asic/design-kits/IBM_Latest_IC614/
. bashrc-64
virtuoso &

and add that path to your PATH by adding the following lines to ~/.bash_profile:
```
PATH=$PATH:$HOME/bin
export PATH
		
```

import old libraries from previous design kit versions (if applicable):

cp ~/asic/design-kits/old_design_kit_dir/cds.lib ~/asic/design-kits/IBM_Latest_IC614/

remove any old locks on the design files (if applicable) - make sure nobody's running cadence on designs in your library before doing this:
```
cd location_of_my_libraries
find -type f -name "*cdslck*" -exec rm {} \;
			
```

running simulations:

to set up a new simulation:
- load a schematic and go to menu "Launch" / "ADE GXL"
- select "create new" based on the (already selected?) schematic from the list
- go to the "data view" / "tests" and click "click to add test" to add test
- the buttons on the right of the "test editor" are useful - click the second one down to choose an analysis (DC/AC/Transient/etc)
- for transient analysis, set a "stop time" in seconds (remember to include the order of magnitude - 100n for nanoseconds, for instance)
- for "accuracy default" chose conservative
- the next button down is to "edit variables" - choose "copy from" schematic and then set each to some nominal value (these can be swept later, but need a nominal value initially)
- the next button is "setup outputs" so you can display something in a waveform (click "from schematic" and then click on nets you'd like to see)
- go to menu "setup" / "model libraries"
- make sure it says, "design.scs" on one line, and "allModels.scs" / section "tt" on the next line
- (alternately, you can add the following lines to your ~/.cdsenv file:
```
spectre.envOpts  includePath  string "/home/mza/asic/design-kits/IBM_Latest_IC614/models"
spectre.envOpts  modelFiles   string "design.scs allModels.scs"
					
```
  - but you must restart Cadence after making this change. Also, it won't change simulation test setups that have already been saved.)
- close the "test editor" window, hit save on the "analog design environment" project
if you get the following message:
```
19: Illegal library definition found in netlist
			
```
it is because you need to specify a section in the allModels.scs column ("tt" works)
to use parasitic extraction to improve the quality of the simulation, perform the following steps:
- in the ADEGXL window, the parasitics menu -> "Setup Parasitics" - switch Cell to the one that has an extraction associated with it, then "av_extracted" should automatically be selected on the right.
- on the left of the ADEGXL window, it says "no parasitics" - change this to "extracted"

if you get:

ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the instance 'I31' in cell 'single_cell_test'. Either add one of these views to the library 'mza_test5', cell 'single_cell' or modify the view list to contain an existing view.

right-click on the test in ADE's data view, select "environment" and add one of the view names that exists for your design (in my case, this was "schematic_alternate_FF") to the view list.

running Calibre DRC:

IBM_PDK menu -> "Checking" -> "Calibre" -> "DRC"
Environmental Variable Setup:
- BEOL_STACK: 3_2_3
- CHECK_RECOMMENDED: ON
- DENSITY_LOCAL: OFF
- DESIGN_TYPE: CELL
- LASTMETAL: MA
- don't show this dialog again: check
Calibre DRC: "view" -> "tree options" -> deselect "empty checks"

sometimes, Calibre DRC refuses to work with a message along the lines of:

ibmPdkrunCalibre("DRC")
Starting DRC on top cell in window:2...
nil
				and the solution is to associate a new library TECH reference with it (a step that is sometimes forgotten when creating a library):
		
			right-click on library in "library manager"
			
select "library properties"
			
if there is no "TECH" (or "techLibName") item at the bottom, click the "add" button and add a "TECH" item that is a string and make it equal to "cmrf8sf"
		
		"((20*M3) + (Pfet S/D not over T3)) / (union[NW,PI]) ratio >= 0.20" means one needs to connect some spare M3 to the substrate contact for the buried p-well, even if it doesn't do anything (for some reason)

running Assura DRC:

find drc.rul file (usually in ${path_to_my_design_kit}/Assura/DRC/drc.rul as long as the Assura symbolic link has been created)
set the following switches:
- BEOL_STACK_323
- Ext_Latchup
- GridCheck

running Assura LVS (VLDB):

the extract rules file is set to:

/opt/cadence/designKits/IBM_PDK/cmrf8sf/V1.8.0.1DM/Assura/LVS/extract323.rul

but it should be set to:

/opt/cadence/designKits/IBM_PDK/cmrf8sf/V1.8.0.1DM/Assura/LVS/extract32.rul

running QRC parasitic extraction:

create a symbolic link to the assura directory from within your copy of the design kit setup dir:

cd ${path_to_my_design_kit}
ln -s /opt/cadence/designKits/IBM_PDK/cmrf8sf/relDM/Assura Assura

layout menu item QRC / setup QRC:
- setup tab / set as default: extracted view
- extraction tab / set as default: RC, ref node="/gnd" (or whatever your ground net is)
- run details tab / enable multi processing, number of processors=4
QRC menu -> "run Assura-QRC"
this will not work until Assura LVS (VLDB) has been run on the design
a "no technology directory found" messagebox will appear for some reason, but it can be ignored
be sure "Enable CellView Check" is unchecked or it won't work
Setup Dir: ${path_to_my_design_kit}/Assura/QRC/32

references:

keyboard shortcuts:

general (both schematic and layout):
- f = fit to screen
- w = wire
- c = copy
- m = move
- s = stretch
- ctrl-left-click = deselect all (alternately, ctrl-D does the same)
- esc = go up one level in mode heirarchy
- E = descend into heirarchy
- ctrl-E = go back up
- middle-click = info/properties
schematic only:
- = = switch between schematic and symbol view
layout only:
- ctrl-r create ruler
- shift-b to return to editing normally after editing in place

useful things to remember:

general:
- "exceeds nestability limit of 5" means there's another window open somewhere that has too many commands stacked up
- Derek Loves Quark (DRC, then LVS, then QRC)
- to re-associate an old layout with a new schematic, from the schematic, do file menu -> "launch layout", then do "open existing" layout and "create new" configuration
- CIW (main cadence/virtuoso) window options menu -> "file preferences" -> "prompt on exit" = no
- CIW options menu -> "log filter" -> disable all but \e and \w (errors and warnings)
schematic only:
layout only:
- to make a cell border, from the create menu -> "P&R objects" -> "area boundary"
- view menu -> "background" to select another layout to copy from (onion skin)
- "Generate All From Source" to get items from schematic to appear in layout
- "edit in place" a group, then select an item, then "edit menu" -> group -> "remove from group" becomes active
- "create" menu -> "group" to group items together
- "Place as in Schematic" to do a rough move
- use "align" to align things
- if you replace a component in schematic, you can update it in layout by right-clicking on the object in the navigator and selecting "update" -> "from source"