For waveform sampling ASIC control with an FPGA, there is a series of steps that must be taken before any data can be read out that is of any interest. A brief list is sketched out on this page.

To get trigger bits out (1 bit time-ordered values), you need to perform all the steps in the trigger path. To get waveform data out (12 bit time-ordered values), you need to perform all the steps in the waveform path. If you're using the trigger bits for selective readout, then you need to complete both paths before you should expect any data.

Please remember that a chain is only as strong as its weakest link: if any one of these steps skipped, or if you've verified that step N works, and then break step N while implementing step N+1, then you shouldn't expect any (good) data out of the ASIC.

This page uses the IRS3B ASIC as an example. Your ASIC maywill be different. All the waveform sampling ASICs need the same general things done, but the specifics of what the names of the signals are, what the names of the DACs/bias voltages are that correspond to which sub-block will be different. If you look at the list of DACs/bias voltages for your ASIC and some of them aren't being set (because you followed this example too closely), then you should make sure you know for sure that they're not needed for what you're trying to do (hint: they're all needed).

advice:

• If you aren't given a block diagram of how the ASIC works, then make one. You can't make firmware work to control something complicated if you don't understand how the complicated thing works.
• Make something simple that works and verify it before going on to the next step.

1. set trigger-related DACs (internal to the ASIC or external DACs on the PCB) to needed values:
   • TRGthreshref (trigger test channel threshold)
   • TRGbias2 (trigger test channel comparator bias)
   • trg_sign (trigger on rising edge)
   • TRGbias (trigger comparator bias)
   • trig_thresh[7:0] (trigger threshold)
   • Wbias (comparator output width)
   • [also set DACs corresponding to registers #17, #18, #19, #15, #13 for buffer biases appropriately]
2. verify with a voltmeter that each is being set to the desired voltage (this is only possible on the 8 trig_thresh channels for IRS3B, but should be done everywhere possible on your ASIC)
3. send pulse in to ASIC RF input
4. trigger outputs should toggle (if not, verify steps above)

1. set sampling-control-related DACs (internal to the ASIC or external DACs on the PCB) to needed values:
   • VadjP (sampling rate adjustment PFET)
   • VadjN (sampling rate adjustment NFET)
   • [also set DACs corresponding to registers #43, #45 for buffer biases appropriately]
2. verify with a voltmeter that each is being set to the desired voltage (there will be no sampling timebase if these are not set)
3. apply small amplitude sine wave to ASIC RF input
4. send SST_IN pulse to have the ASIC sample 128 cells worth of analog signal
5. congratulations, the ASIC has now sampled a waveform (if you've done all the steps correctly)! However, there are still 3 major sets of steps to perform before you can have any data.
6. TO BE CONTINUED...