27-JAN-09 Punch List

Critical items -- see Larry's task list!

ARA

  1. o      Assemble 2x IRS_eval (Larry – waiting for IRS ASIC)
  2. o      IRS_eval  firmware development (Larry – waiting for ASIC read timing diagram from Gary)


Belle II

- COPPER Development

- DSP_FINv1[fixed point] Development

- DSP_FINv2[floating point] Development

          - TRIG_FIN Development

          - DATA_FIN Development

o      DATA_FIN_revB firmware development (Larry)

- SL10 4x4 Developments

o      Assemble 10x SL10_4x4 base board (Jim)

o      Assemble 2x TOP_FRONT_SL10_Nagoya (Larry –waiting for digikey order)

o      Mechanical fit check for SL10 Nagoya readout (Larry - waiting for assembly)

o      Assemble 2x Nagoya_SCAN_BASE (Larry –waiting for digikey order)

- Planacon Development

o      Assemble 2x TOP_BOTTOM_Planacon (Larry – waiting for Newark order)

o      Mechanical fit check for SL10 Nagoya readout (Larry – waiting for Planacon tube and assembly)

- BLAB3 Development

o      Assemble 2x TOP_MAIN (Larry – waiting for FPGAs and BGA assembly)


CREAM TEA

  1. Design new R5900 break board with protection diodes (Larry)
  2. Design TOP_IRS (Larry)

fDIRC (SLAC)

  1. o      Put together the NIM module w/ faceplate of  2x NIM_CLK (Jim)
  2. o      Put together the NIM module w/ faceplate of  1x NIM_3P3V_PWR (Jim)
  3. o      Update GEANT4 MC simulation (Larry/Kurtis)
  4. o      Mechanical fit check for new H8500 readout (Larry - waiting for H8500 from HI-TIDE setup)
  5. o      Assemble 1x NIM_3P3V_PWR (Larry –waiting for digikey order)
  6. o      Test NIM_3P3V_PWR module (Larry - waiting for assembly)
  7. o      NIM_CLK firmware development (Larry – waiting for NIM casing)

iTOP (Nagoya)

  1. Included above -- deliverables here?

iTOP (KEK)

  1. Included above -- deliverables here?

LAPPD

  1. Stud bond from CV Inc (meeting this morning) [Gary/Larry]
  2. Wire bond board testing status [Larry]
  3. o      Assemble 2x psTDC_eval_revCv2 (Jim – waiting for fabrication) [AC main board]

    o      Assemble 2x psTDC_eval_revDv2 (Jim – waiting for fabrication) [DC main board]

    o      psTDC_eval_revCv2 [DC card] firmware development (Larry - waiting for assembly)

    o      psTDC_eval_revDv2 [DC card] firmware development (Larry - waiting for assembly)


STURM-II

  1. Design STURM2_eval (Larry – wiring bond pin out)
    1. This is going to be the wire-bonded version for DC verification from Jim
  2. STURM2_eval firmware development (Gary)
  3.  

xFEL -- detailed schedule

  1. Beamline simulations [Gary]
  2. Laser pulse test of MPPCs [Gary]
  3. Beamline detector config/layout [Gary/Larry]
  4. 3 technical reports on Detector, ASIC, DAQ [Gary, all]
  5. additional software help [Gary]

Misc ID Lab

  1. Purchase additional scissors, staplers, tape dispensers [Jim]
  2. 2x new student job postings (software, assy/test) [Jim/all]
  3. Status of repairing broken power supply? [Jim]
  4. Status of fixing the chemical hood air flow? [Jim]
  5. Production assembly help [Larry]


Pending:

Inactive:





Last modified: 1/10/2010 -- GSV