{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 23 01:44:11 2010 " "Info: Processing started: Thu Dec 23 01:44:11 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "aurora_8b10b_v5_2_example_design EP4SGX230KF40C2 " "Info: Selected device EP4SGX230KF40C2 for design \"aurora_8b10b_v5_2_example_design\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 0.9V " "Info: Core supply voltage is 0.9V" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4SGX180KF40C2 " "Info: Device EP4SGX180KF40C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4SGX290KF40C2 " "Info: Device EP4SGX290KF40C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4SGX360KF40C2 " "Info: Device EP4SGX360KF40C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4SGX530KH40C2 " "Info: Device EP4SGX530KH40C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ W30 " "Info: Pin ~ALTERA_DATA0~ is reserved at location W30" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 22847 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Warning" "WFSAC_FSAC_COMPLEMENT_PIN_CREATED_GROUP" "3 " "Warning: Following 3 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins." { { "Warning" "WFSAC_FSAC_COMPLEMENT_PIN_CREATED" "TXP TXP(n) " "Warning: Pin \"TXP\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"TXP(n)\"" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { TXP } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "TXP" } { 0 "TXP(n)" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 100 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18033 3016 4146 0} { 0 { 0 ""} 0 18242 3016 4146 0}  }  } } { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { TXP(n) } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXP(n) } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"%2!s!\"" 0 0 "" 0 -1} { "Warning" "WFSAC_FSAC_COMPLEMENT_PIN_CREATED" "RXP RXP(n) " "Warning: Pin \"RXP\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"RXP(n)\"" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { RXP } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "RXP" } { 0 "RXP(n)" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 98 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18031 3016 4146 0} { 0 { 0 ""} 0 18241 3016 4146 0}  }  } } { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { RXP(n) } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXP(n) } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"%2!s!\"" 0 0 "" 0 -1} { "Warning" "WFSAC_FSAC_COMPLEMENT_PIN_CREATED" "GTXQ4 GTXQ4(n) " "Warning: Pin \"GTXQ4\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"GTXQ4(n)\"" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { GTXQ4 } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "GTXQ4" } { 0 "GTXQ4(n)" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 94 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { GTXQ4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18030 3016 4146 0} { 0 { 0 ""} 0 18240 3016 4146 0}  }  } } { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { GTXQ4(n) } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { GTXQ4(n) } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"%2!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins." 0 0 "" 0 -1}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "14 25 " "Critical Warning: No exact pin location assignment(s) for 14 pins of 25 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIS_USER_CLK " "Info: Pin DIS_USER_CLK not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { DIS_USER_CLK } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 78 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIS_USER_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18018 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "HARD_ERR " "Info: Pin HARD_ERR not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { HARD_ERR } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 83 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { HARD_ERR } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18023 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SOFT_ERR " "Info: Pin SOFT_ERR not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { SOFT_ERR } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 84 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { SOFT_ERR } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18024 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FRAME_ERR " "Info: Pin FRAME_ERR not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { FRAME_ERR } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 85 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { FRAME_ERR } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18025 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[7\] " "Info: Pin ERR_COUNT\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ERR_COUNT[7] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18010 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[6\] " "Info: Pin ERR_COUNT\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ERR_COUNT[6] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18011 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[5\] " "Info: Pin ERR_COUNT\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ERR_COUNT[5] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18012 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[4\] " "Info: Pin ERR_COUNT\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ERR_COUNT[4] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18013 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[3\] " "Info: Pin ERR_COUNT\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ERR_COUNT[3] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18014 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[2\] " "Info: Pin ERR_COUNT\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ERR_COUNT[2] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18015 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[1\] " "Info: Pin ERR_COUNT\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ERR_COUNT[1] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18016 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[0\] " "Info: Pin ERR_COUNT\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { ERR_COUNT[0] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18017 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RXN " "Info: Pin RXN not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { RXN } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 99 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18032 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TXN " "Info: Pin TXN not assigned to an exact location on the device" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { TXN } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 101 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18034 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Critical Warning" "WFHSSI_FHSSI_CMU_MUST_HAVE_RECONFIG" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 RX offset cancellation " "Critical Warning: GXB Central Management Unit (CMU) aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 is not connected to a GXB reconfig logic block, but the RX offset cancellation feature requires that it must be" {  } {  } 1 0 "GXB Central Management Unit (CMU) %1!s! is not connected to a GXB reconfig logic block, but the %2!s! feature requires that it must be" 0 0 "" 0 -1}
{ "Info" "IFHSSI_FHSSI_PLL_COMP_CAL_CLK_IN_PERIOD_RANGE_INFO" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0 10.0 MHz 125.0 MHz " "Info: Clock input frequency of GXB Calibration block atom \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0\" must be in the frequency range of 10.0 MHz to 125.0 MHz" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1520 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|cal_blk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 3959 3016 4146 0}  }  } }  } 0 0 "Clock input frequency of GXB Calibration block atom \"%1!s!\" must be in the frequency range of %2!s! to %3!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\|pll1 Top/Bottom PLL " "Info: Implemented PLL \"PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\|pll1\" as Top/Bottom PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\|wire_pll1_clk\[0\] 16 5 0 0 " "Info: Implementing clock multiplication of 16, clock division of 5, and phase shift of 0 degrees (0 ps) for PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\|wire_pll1_clk\[0\] port" {  } { { "db/pll_la_altpll.v" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/pll_la_altpll.v" 43 -1 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "db/pll_la_altpll.v" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/pll_la_altpll.v" 77 -1 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "IFHSSI_FHSSI_MERGING_COMPLETE" "" "Info: GXB Quad Optimizer operation is complete" {  } {  } 0 0 "GXB Quad Optimizer operation is complete" 0 0 "" 0 -1}
{ "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Current transceiver placement " "Info: Current transceiver placement" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "QUAD_SIDE_LEFT " "Info: QUAD_SIDE_LEFT" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PCIEHIP_X0_Y3_N134            " "Info: PCIEHIP_X0_Y3_N134           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CALIBRATIONBLOCK_X0_Y2_N135  aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0 " "Info: CALIBRATIONBLOCK_X0_Y2_N135  aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1520 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|cal_blk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 3959 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CALIBRATIONBLOCK_X0_Y89_N135   " "Info: CALIBRATIONBLOCK_X0_Y89_N135  " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "ATX LCTANK_X0_Y25_N135 " "Info: ATX LCTANK_X0_Y25_N135" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X0_Y25_N137               " "Info: CMU_X0_Y25_N137              " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y25_N135           " "Info: HSSIPLL_X0_Y25_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y25_N136      " "Info: CLOCKDIVIDER_X0_Y25_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QL0 " "Info: Atoms placed to IOBANK_QL0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X0_Y10_N139               " "Info: CMU_X0_Y10_N139              " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 0 " "Info: Regular Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y4_N145              " "Info: IOPAD_X0_Y4_N145             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y4_N146             " "Info: IOIBUF_X0_Y4_N146            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y4_N137              " "Info: RXPMA_X0_Y4_N137             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y4_N139              " "Info: RXPCS_X0_Y4_N139             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y4_N135            " "Info: HSSIPLL_X0_Y4_N135           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y4_N136       " "Info: CLOCKDIVIDER_X0_Y4_N136      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y4_N140              " "Info: TXPCS_X0_Y4_N140             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y4_N138              " "Info: TXPMA_X0_Y4_N138             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y4_N141              " "Info: IOPAD_X0_Y4_N141             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y4_N142             " "Info: IOOBUF_X0_Y4_N142            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 1 " "Info: Regular Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y7_N145              " "Info: IOPAD_X0_Y7_N145             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y7_N146             " "Info: IOIBUF_X0_Y7_N146            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y7_N137              " "Info: RXPMA_X0_Y7_N137             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y7_N139              " "Info: RXPCS_X0_Y7_N139             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y7_N135            " "Info: HSSIPLL_X0_Y7_N135           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y7_N136       " "Info: CLOCKDIVIDER_X0_Y7_N136      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y7_N140              " "Info: TXPCS_X0_Y7_N140             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y7_N138              " "Info: TXPMA_X0_Y7_N138             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y7_N141              " "Info: IOPAD_X0_Y7_N141             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y7_N142             " "Info: IOOBUF_X0_Y7_N142            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 0 " "Info: Central Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y10_N145             " "Info: IOPAD_X0_Y10_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y10_N146            " "Info: IOIBUF_X0_Y10_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y10_N137             " "Info: RXPMA_X0_Y10_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y10_N135           " "Info: HSSIPLL_X0_Y10_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y10_N136      " "Info: CLOCKDIVIDER_X0_Y10_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y10_N138             " "Info: TXPMA_X0_Y10_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y10_N141             " "Info: IOPAD_X0_Y10_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y10_N142            " "Info: IOOBUF_X0_Y10_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 1 " "Info: Central Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y13_N145             " "Info: IOPAD_X0_Y13_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y13_N146            " "Info: IOIBUF_X0_Y13_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y13_N137             " "Info: RXPMA_X0_Y13_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y13_N135           " "Info: HSSIPLL_X0_Y13_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y13_N136      " "Info: CLOCKDIVIDER_X0_Y13_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y13_N138             " "Info: TXPMA_X0_Y13_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y13_N141             " "Info: IOPAD_X0_Y13_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y13_N142            " "Info: IOOBUF_X0_Y13_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 2 " "Info: Regular Channel 2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y16_N145             " "Info: IOPAD_X0_Y16_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y16_N146            " "Info: IOIBUF_X0_Y16_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y16_N137             " "Info: RXPMA_X0_Y16_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y16_N139             " "Info: RXPCS_X0_Y16_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y16_N135           " "Info: HSSIPLL_X0_Y16_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y16_N136      " "Info: CLOCKDIVIDER_X0_Y16_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y16_N140             " "Info: TXPCS_X0_Y16_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y16_N138             " "Info: TXPMA_X0_Y16_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y16_N141             " "Info: IOPAD_X0_Y16_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y16_N142            " "Info: IOOBUF_X0_Y16_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 3 " "Info: Regular Channel 3" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y19_N145             " "Info: IOPAD_X0_Y19_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y19_N146            " "Info: IOIBUF_X0_Y19_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y19_N137             " "Info: RXPMA_X0_Y19_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y19_N139             " "Info: RXPCS_X0_Y19_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y19_N135           " "Info: HSSIPLL_X0_Y19_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y19_N136      " "Info: CLOCKDIVIDER_X0_Y19_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y19_N140             " "Info: TXPCS_X0_Y19_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y19_N138             " "Info: TXPMA_X0_Y19_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y19_N141             " "Info: IOPAD_X0_Y19_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y19_N142            " "Info: IOOBUF_X0_Y19_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QL1 " "Info: Atoms placed to IOBANK_QL1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X0_Y41_N139              aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 " "Info: CMU_X0_Y41_N139              aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1577 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_cent_unit0_dprioout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 3975 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 0 " "Info: Regular Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y35_N145            RXP " "Info: IOPAD_X0_Y35_N145            RXP" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { RXP } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "RXP" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 98 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18031 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y35_N146           RXP~input " "Info: IOIBUF_X0_Y35_N146           RXP~input" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 98 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXP~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 22831 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y35_N137            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pma0 " "Info: RXPMA_X0_Y35_N137            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pma0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1873 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|rx_pma_dataout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 3161 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y35_N139            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pcs0 " "Info: RXPCS_X0_Y35_N139            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pcs0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1727 -1 0 } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_dataout\[0\]" } } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 2732 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y35_N135          aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_cdr_pll0 " "Info: HSSIPLL_X0_Y35_N135          aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_cdr_pll0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1662 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|pll_ch_dataout_wire[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 2124 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y35_N136     aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|ch_clk_div0 " "Info: CLOCKDIVIDER_X0_Y35_N136     aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|ch_clk_div0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1527 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|ch_clk_div0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 3964 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y35_N140            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pcs0 " "Info: TXPCS_X0_Y35_N140            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pcs0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1938 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_transmit_pma0_datain[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 3488 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y35_N138            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pma0 " "Info: TXPMA_X0_Y35_N138            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pma0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 2018 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_transmit_pma0_dataout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 17924 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y35_N141            TXP " "Info: IOPAD_X0_Y35_N141            TXP" {  } { { "c:/altera/91/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91/quartus/bin/pin_planner.ppl" { TXP } } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "TXP" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 100 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18033 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y35_N142           TXP~output " "Info: IOOBUF_X0_Y35_N142           TXP~output" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 100 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXP~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 22827 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 1 " "Info: Regular Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y38_N145             " "Info: IOPAD_X0_Y38_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y38_N146            " "Info: IOIBUF_X0_Y38_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y38_N137             " "Info: RXPMA_X0_Y38_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y38_N139             " "Info: RXPCS_X0_Y38_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y38_N135           " "Info: HSSIPLL_X0_Y38_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y38_N136      " "Info: CLOCKDIVIDER_X0_Y38_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y38_N140             " "Info: TXPCS_X0_Y38_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y38_N138             " "Info: TXPMA_X0_Y38_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y38_N141             " "Info: IOPAD_X0_Y38_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y38_N142            " "Info: IOOBUF_X0_Y38_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 0 " "Info: Central Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y41_N145             " "Info: IOPAD_X0_Y41_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y41_N146            " "Info: IOIBUF_X0_Y41_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y41_N137             " "Info: RXPMA_X0_Y41_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y41_N135          aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_pll0 " "Info: HSSIPLL_X0_Y41_N135          aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_pll0" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1694 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|tx_pll0~DATAOUT0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 17529 3016 4146 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y41_N136      " "Info: CLOCKDIVIDER_X0_Y41_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y41_N138             " "Info: TXPMA_X0_Y41_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y41_N141             " "Info: IOPAD_X0_Y41_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y41_N142            " "Info: IOOBUF_X0_Y41_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 1 " "Info: Central Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y44_N145             " "Info: IOPAD_X0_Y44_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y44_N146            " "Info: IOIBUF_X0_Y44_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y44_N137             " "Info: RXPMA_X0_Y44_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y44_N135           " "Info: HSSIPLL_X0_Y44_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y44_N136      " "Info: CLOCKDIVIDER_X0_Y44_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y44_N138             " "Info: TXPMA_X0_Y44_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y44_N141             " "Info: IOPAD_X0_Y44_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y44_N142            " "Info: IOOBUF_X0_Y44_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 2 " "Info: Regular Channel 2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y47_N145             " "Info: IOPAD_X0_Y47_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y47_N146            " "Info: IOIBUF_X0_Y47_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y47_N137             " "Info: RXPMA_X0_Y47_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y47_N139             " "Info: RXPCS_X0_Y47_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y47_N135           " "Info: HSSIPLL_X0_Y47_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y47_N136      " "Info: CLOCKDIVIDER_X0_Y47_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y47_N140             " "Info: TXPCS_X0_Y47_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y47_N138             " "Info: TXPMA_X0_Y47_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y47_N141             " "Info: IOPAD_X0_Y47_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y47_N142            " "Info: IOOBUF_X0_Y47_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 3 " "Info: Regular Channel 3" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y50_N145             " "Info: IOPAD_X0_Y50_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y50_N146            " "Info: IOIBUF_X0_Y50_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y50_N137             " "Info: RXPMA_X0_Y50_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y50_N139             " "Info: RXPCS_X0_Y50_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y50_N135           " "Info: HSSIPLL_X0_Y50_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y50_N136      " "Info: CLOCKDIVIDER_X0_Y50_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y50_N140             " "Info: TXPCS_X0_Y50_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y50_N138             " "Info: TXPMA_X0_Y50_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y50_N141             " "Info: IOPAD_X0_Y50_N141            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X0_Y50_N142            " "Info: IOOBUF_X0_Y50_N142           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QL2 " "Info: Atoms placed to IOBANK_QL2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X0_Y69_N139               " "Info: CMU_X0_Y69_N139              " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 0 " "Info: Regular Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X0_Y63_N145             " "Info: IOPAD_X0_Y63_N145            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOIBUF_X0_Y63_N146            " "Info: IOIBUF_X0_Y63_N146           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y63_N137             " "Info: RXPMA_X0_Y63_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y63_N139             " "Info: RXPCS_X0_Y63_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y63_N135           " "Info: HSSIPLL_X0_Y63_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y63_N136      " "Info: CLOCKDIVIDER_X0_Y63_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y63_N140             " "Info: TXPCS_X0_Y63_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { 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"Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y78_N140           " "Info: TXPCS_X119_Y78_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y78_N138           " "Info: TXPMA_X119_Y78_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOPAD_X119_Y78_N141           " "Info: IOPAD_X119_Y78_N141          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "IOOBUF_X119_Y78_N142          " "Info: IOOBUF_X119_Y78_N142         " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Warning: Overwriting existing clock: altera_reserved_tck" {  } {  } 0 0 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "aurora_8b10b_v5_2_example_design.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'aurora_8b10b_v5_2_example_design.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "INIT_CLK " "Warning: Node: INIT_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "Info: The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a0\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a0~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a0\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a0~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a10\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a10~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a10\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a10~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a11\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a11~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a11\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a11~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a12\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a12~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a12\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a12~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a13\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a13~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a13\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a13~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a14\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a14~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a14\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a14~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a15\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a15~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a15\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a15~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a16\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a16~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a16\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a16~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a17\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a17~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a17\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a17~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a18\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a18~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a18\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a18~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a19\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a19~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a19\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a19~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a1\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a1~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a1\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a1~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a20\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a20~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a20\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a20~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a21\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a21~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a21\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a21~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a22\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a22~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a22\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a22~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a23\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a23~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a23\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a23~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a24\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a24~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a24\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a24~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a25\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a25~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a25\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a25~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a26\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a26~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a26\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a26~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a27\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a27~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a27\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a27~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a28\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a28~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a28\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a28~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a29\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a29~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a29\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a29~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a2\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a2~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a2\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a2~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a30\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a30~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a30\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a30~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a31\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a31~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a31\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a31~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a32\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a32~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a32\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a32~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a33\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a33~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a33\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a33~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a34\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a34~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a34\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a34~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a35\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a35~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a35\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a35~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a36\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a36~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a36\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a36~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a37\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a37~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a37\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a37~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a38\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a38~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a38\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a38~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a39\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a39~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a39\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a39~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a3\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a3~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a3\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a3~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a40\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a40~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a40\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a40~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a41\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a41~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a41\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a41~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a42\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a42~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a42\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a42~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a43\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a43~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a43\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a43~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a44\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a44~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a44\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a44~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a45\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a45~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a45\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a45~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a46\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a46~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a46\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a46~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a47\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a47~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a47\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a47~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a48\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a48~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a48\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a48~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a49\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a49~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a49\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a49~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a4\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a4~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a4\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a4~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a50\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a50~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a50\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a50~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a51\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a51~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a51\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a51~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a52\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a52~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a52\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a52~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a53\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a53~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a53\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a53~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a54\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a54~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a54\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a54~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a55\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a55~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a55\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a55~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a56\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a56~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a56\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a56~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a57\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a57~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a57\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a57~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a58\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a58~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a58\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a58~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a59\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a59~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a59\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a59~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a5\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a5~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a5\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a5~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a60\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a60~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a60\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a60~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a61\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a61~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a61\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a61~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a62\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a62~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a62\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a62~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a63\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a63~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a63\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a63~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a64\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a64~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a64\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a64~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a65\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a65~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a65\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a65~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a66\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a66~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a66\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a66~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a67\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a67~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a67\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a67~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a68\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a68~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a68\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a68~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a69\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a69~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a69\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a69~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a6\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a6~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a6\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a6~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a70\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a70~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a70\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a70~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a71\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a71~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a71\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a71~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a72\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a72~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a72\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a72~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a73\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a73~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a73\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a73~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a74\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a74~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a74\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a74~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a7\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a7~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a7\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a7~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a8\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a8~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a8\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a8~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a9\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a9~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a9\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a9~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "" 0 -1}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "Info: No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 0 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_CLOCK_UNCERTAINTY_NUMBERS_ARE_PRELIMINARY" "Stratix IV " "Warning: Clock uncertainty characteristics of the Stratix IV device family are preliminary" {  } {  } 0 0 "Clock uncertainty characteristics of the %1!s! device family are preliminary" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 0 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: LA_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 6.400 " "Warning: Node: LA_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 6.400" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Info: Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " "Info:  100.000 altera_reserved_tck" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\] (placed in RXPCS_X0_Y35_N139) " "Info: Automatically promoted node aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\] (placed in RXPCS_X0_Y35_N139)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1727 -1 0 } } { "c:/altera/91/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin/Assignment Editor.qase" 1 { { 0 "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_dataout\[0\]" } } } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 2732 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\] (placed in TXPCS_X0_Y35_N140) " "Info: Automatically promoted node aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\] (placed in TXPCS_X0_Y35_N140)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1938 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_transmit_pma0_datain[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 3488 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_B1) " "Info: Automatically promoted node PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_B1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "db/pll_la_altpll.v" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/pll_la_altpll.v" 77 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL_LA:LA_PLL|altpll:altpll_component|PLL_LA_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 17983 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18250 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G12 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G12" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|status_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|status_buf_read_reset" {  } { { "sld_buffer_manager.vhd" "" { Text "c:/altera/91/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 629 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|status_buf_read_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18548 3016 4146 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "sld_buffer_manager.vhd" "" { Text "c:/altera/91/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 627 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 18544 3016 4146 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "sld_signaltap.vhd" "" { Text "c:/altera/91/quartus/libraries/megafunctions/sld_signaltap.vhd" 831 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 19599 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "14 unused 2.5V 1 13 0 " "Info: Number of I/O pins in group: 14 (unused VREF, 2.5V VCCIO, 1 input, 13 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "Info: I/O standards used: 2.5 V." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 5 48 " "Info: I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1C does not use undetermined 1 41 " "Info: I/O bank number 1C does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  41 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2C does not use undetermined 0 42 " "Info: I/O bank number 2C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2A does not use 2.5V 2 46 " "Info: I/O bank number 2A does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  46 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 3 37 " "Info: I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used --  37 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3B does not use undetermined 0 24 " "Info: I/O bank number 3B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3C does not use undetermined 1 31 " "Info: I/O bank number 3C does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  31 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4C does not use undetermined 0 32 " "Info: I/O bank number 4C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  32 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4B does not use undetermined 0 24 " "Info: I/O bank number 4B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4A does not use undetermined 0 40 " "Info: I/O bank number 4A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5A does not use undetermined 0 48 " "Info: I/O bank number 5A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5C does not use undetermined 0 42 " "Info: I/O bank number 5C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6C does not use undetermined 0 42 " "Info: I/O bank number 6C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6A does not use undetermined 0 48 " "Info: I/O bank number 6A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7A does not use undetermined 0 40 " "Info: I/O bank number 7A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7B does not use undetermined 0 24 " "Info: I/O bank number 7B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7C does not use undetermined 0 32 " "Info: I/O bank number 7C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  32 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8C does not use 2.5V 2 30 " "Info: I/O bank number 8C does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8B does not use undetermined 0 24 " "Info: I/O bank number 8B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 40 " "Info: I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL11 does not use undetermined 0 0 " "Info: I/O bank number QL11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL2 does not use undetermined 2 0 " "Info: I/O bank number QL2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL1 does not use 1.4V 4 0 " "Info: I/O bank number QL1 does not use VREF pins and has 1.4V VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "Info: I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL10 does not use undetermined 0 0 " "Info: I/O bank number QL10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR10 does not use undetermined 0 0 " "Info: I/O bank number QR10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR0 does not use undetermined 0 0 " "Info: I/O bank number QR0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR1 does not use undetermined 0 0 " "Info: I/O bank number QR1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR2 does not use undetermined 0 0 " "Info: I/O bank number QR2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR11 does not use undetermined 0 0 " "Info: I/O bank number QR11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Critical Warning" "WFHSSI_FHSSI_CMU_MUST_HAVE_RECONFIG" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 RX offset cancellation " "Critical Warning: GXB Central Management Unit (CMU) aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 is not connected to a GXB reconfig logic block, but the RX offset cancellation feature requires that it must be" {  } {  } 1 0 "GXB Central Management Unit (CMU) %1!s! is not connected to a GXB reconfig logic block, but the %2!s! feature requires that it must be" 0 0 "" 0 -1}
{ "Info" "IFHSSI_FHSSI_PLL_COMP_CAL_CLK_IN_PERIOD_RANGE_INFO" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0 10.0 MHz 125.0 MHz " "Info: Clock input frequency of GXB Calibration block atom \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0\" must be in the frequency range of 10.0 MHz to 125.0 MHz" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 1520 -1 0 } } { "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|cal_blk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/" 0 { } { { 0 { 0 ""} 0 3959 3016 4146 0}  }  } }  } 0 0 "Clock input frequency of GXB Calibration block atom \"%1!s!\" must be in the frequency range of %2!s! to %3!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:37 " "Info: Fitter preparation operations ending: elapsed time is 00:00:37" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:04 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:21 " "Info: Fitter placement operations ending: elapsed time is 00:00:21" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "12 X36_Y48 X47_Y59 " "Info: Peak interconnect usage is 12% of the available device resources in the region that extends from location X36_Y48 to location X47_Y59" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Info: Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP4SGX230KF40C2 " "Warning: Timing characteristics of device EP4SGX230KF40C2 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2_example_design.fit.smsg " "Info: Generated suppressed messages file D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2_example_design.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 17 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "562 " "Info: Peak virtual memory: 562 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 23 01:46:56 2010 " "Info: Processing ended: Thu Dec 23 01:46:56 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:02:45 " "Info: Elapsed time: 00:02:45" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:02:55 " "Info: Total CPU time (on all processors): 00:02:55" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
