library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FDR is
	generic (INIT : std_ulogic := '0');
    port (
            Q : out std_ulogic := INIT;
            C : in  std_ulogic;
            D : in  std_ulogic;
            R : in  std_ulogic
         );	
end FDR;

architecture MAIN of FDR is

begin

	process (C) 
	begin 
		if (C' event and C = '1') then 
			if (R = '1') then 
				Q <= '0'; 
			else 
				Q <= D; 
			end if; 
		end if; 
	end process;

end MAIN;