# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 222 10/21/2009 SJ Full Version
# Date created = 02:19:38  December 07, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		aurora_8b10b_v5_2_example_design_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Stratix IV"
set_global_assignment -name DEVICE EP4SGX230KF40C2
set_global_assignment -name TOP_LEVEL_ENTITY aurora_8b10b_v5_2_example_design
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:19:38  DECEMBER 07, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_AN30 -to CHANNEL_UP
set_location_assignment PIN_AP30 -to LANE_UP
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to TXP
set_global_assignment -name MISC_FILE "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2_example_design.dpf"
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to RXP
set_instance_assignment -name IO_STANDARD LVDS -to GTXQ4
set_location_assignment PIN_AD36 -to TXP
set_location_assignment PIN_AD37 -to "TXP(n)"
set_location_assignment PIN_AE38 -to RXP
set_location_assignment PIN_AE39 -to "RXP(n)"
set_location_assignment PIN_AR22 -to INIT_CLK
set_location_assignment PIN_G38 -to GTXQ4
set_location_assignment PIN_G39 -to "GTXQ4(n)"
set_location_assignment PIN_AP28 -to RESET
set_location_assignment PIN_AR28 -to GT_RESET_IN
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=M9K" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name VCCA_L_USER_VOLTAGE 2.5V
set_global_assignment -name VCCA_R_USER_VOLTAGE 2.5V
set_global_assignment -name VCCH_GXBL_USER_VOLTAGE 1.4V
set_global_assignment -name VCCH_GXBR_USER_VOLTAGE 1.4V
set_global_assignment -name POWER_HSSI_VCCHIP_LEFT "Opportunistically power off"
set_global_assignment -name POWER_HSSI_VCCHIP_RIGHT "Opportunistically power off"
set_global_assignment -name POWER_HSSI_LEFT "Opportunistically power off"
set_global_assignment -name POWER_HSSI_RIGHT "Opportunistically power off"
set_location_assignment PIN_AT28 -to GXB_DOWN
set_location_assignment PIN_L20 -to DIS_RX_CLK
set_location_assignment PIN_M20 -to DIS_TX_CLK
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|tx_clkout[0]" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
set_global_assignment -name MISC_FILE "F:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2_example_design.dpf"
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|DO_WORD_ALIGN" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|GOT_V" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|GOT_V_Buffer" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RESET" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_CHAR_IS_COMMA[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_CHAR_IS_COMMA[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_CHAR_IS_K[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_CHAR_IS_K[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|got_v_c" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|left_aligned_r" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_r" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RESET" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=28" -section_id auto_signaltap_0
set_global_assignment -name MISC_FILE "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2_example_design.dpf"
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_pe_control_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_pe_control_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|word_aligned_control_bits_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|word_aligned_control_bits_r[1]" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=39" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=10007" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=19945" -section_id auto_signaltap_0
set_global_assignment -name VHDL_FILE SRL16.vhd
set_global_assignment -name VHDL_FILE MUXCY.vhd
set_global_assignment -name VHDL_FILE MUX16to1.vhd
set_global_assignment -name VHDL_FILE LPMSHIFTREG16.vhd
set_global_assignment -name VHDL_FILE FDR.vhd
set_global_assignment -name VHDL_FILE FD.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd
set_global_assignment -name VHDL_FILE aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd
set_global_assignment -name QIP_FILE MGT156_to_156.qip
set_global_assignment -name QIP_FILE PLL_LA.qip
set_global_assignment -name QIP_FILE MGT.qip
set_global_assignment -name SIGNALTAP_FILE ../../Aurora1lane3125MinAltera_125Mcore_cData/stp1.stp
set_global_assignment -name QIP_FILE LA.qip
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top