{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 23 01:43:18 2010 " "Info: Processing started: Thu Dec 23 01:43:18 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/program/fpga/final_test/altera/replacexilinxcomponent/fd_alan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /program/fpga/final_test/altera/replacexilinxcomponent/fd_alan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FD_Alan-FD_Alan " "Info: Found design unit 1: FD_Alan-FD_Alan" {  } { { "../../ReplaceXilinxComponent/FD_Alan.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/FD_Alan.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 FD_Alan " "Info: Found entity 1: FD_Alan" {  } { { "../../ReplaceXilinxComponent/FD_Alan.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/FD_Alan.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/program/fpga/final_test/altera/replacexilinxcomponent/fdr_alan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /program/fpga/final_test/altera/replacexilinxcomponent/fdr_alan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FDR_Alan-FDR_Alan " "Info: Found design unit 1: FDR_Alan-FDR_Alan" {  } { { "../../ReplaceXilinxComponent/FDR_Alan.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/FDR_Alan.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 FDR_Alan " "Info: Found entity 1: FDR_Alan" {  } { { "../../ReplaceXilinxComponent/FDR_Alan.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/FDR_Alan.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/program/fpga/final_test/altera/replacexilinxcomponent/lpmshiftreg16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /program/fpga/final_test/altera/replacexilinxcomponent/lpmshiftreg16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpmshiftreg16-SYN " "Info: Found design unit 1: lpmshiftreg16-SYN" {  } { { "../../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 LPMSHIFTREG16 " "Info: Found entity 1: LPMSHIFTREG16" {  } { { "../../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/program/fpga/final_test/altera/replacexilinxcomponent/mux16to1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /program/fpga/final_test/altera/replacexilinxcomponent/mux16to1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux16to1-SYN " "Info: Found design unit 1: mux16to1-SYN" {  } { { "../../ReplaceXilinxComponent/MUX16to1.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/MUX16to1.vhd" 67 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 MUX16to1 " "Info: Found entity 1: MUX16to1" {  } { { "../../ReplaceXilinxComponent/MUX16to1.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/MUX16to1.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/program/fpga/final_test/altera/replacexilinxcomponent/srl16_alan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /program/fpga/final_test/altera/replacexilinxcomponent/srl16_alan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SRL16_Alan-arch " "Info: Found design unit 1: SRL16_Alan-arch" {  } { { "../../ReplaceXilinxComponent/SRL16_Alan.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/SRL16_Alan.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 SRL16_Alan " "Info: Found entity 1: SRL16_Alan" {  } { { "../../ReplaceXilinxComponent/SRL16_Alan.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/SRL16_Alan.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_FRAME_CHECK-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_FRAME_CHECK-RTL" {  } { { "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" 97 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_FRAME_CHECK " "Info: Found entity 1: aurora_8b10b_v5_2_FRAME_CHECK" {  } { { "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" 75 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_FRAME_GEN-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_FRAME_GEN-RTL" {  } { { "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" 97 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_FRAME_GEN " "Info: Found entity 1: aurora_8b10b_v5_2_FRAME_GEN" {  } { { "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" 77 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd(93) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd(93)" {  } { { "aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" 93 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_CLOCK_MODULE-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_CLOCK_MODULE-MAPPED" {  } { { "aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" 91 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_CLOCK_MODULE " "Info: Found entity 1: aurora_8b10b_v5_2_CLOCK_MODULE" {  } { { "aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" 68 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd(87) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd(87)" {  } { { "aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" 87 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_STANDARD_CC_MODULE-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_STANDARD_CC_MODULE-RTL" {  } { { "aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" 85 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_STANDARD_CC_MODULE " "Info: Found entity 1: aurora_8b10b_v5_2_STANDARD_CC_MODULE" {  } { { "aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd(142) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd(142)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 142 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2-MAPPED" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 140 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2 " "Info: Found entity 1: aurora_8b10b_v5_2" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(109) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(109)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 109 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "ASYNC_REG aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(194) " "Warning (10335): Unrecognized synthesis attribute \"ASYNC_REG\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(194)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 194 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_example_design-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_example_design-MAPPED" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 107 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_example_design " "Info: Found entity 1: aurora_8b10b_v5_2_example_design" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(84) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(84)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 84 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "ASYNC_REG aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(100) " "Warning (10335): Unrecognized synthesis attribute \"ASYNC_REG\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(100)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 100 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_RESET_LOGIC-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_RESET_LOGIC-MAPPED" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 82 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_RESET_LOGIC " "Info: Found entity 1: aurora_8b10b_v5_2_RESET_LOGIC" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 64 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_AURORA_LANE-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_AURORA_LANE-MAPPED" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 131 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_AURORA_LANE " "Info: Found entity 1: aurora_8b10b_v5_2_AURORA_LANE" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 67 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AURORA_PKG " "Info: Found design unit 1: AURORA_PKG" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" 60 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 AURORA_PKG-body " "Info: Found design unit 2: AURORA_PKG-body" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_CHANNEL_ERR_DETECT-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_CHANNEL_ERR_DETECT-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" 91 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_CHANNEL_ERR_DETECT " "Info: Found entity 1: aurora_8b10b_v5_2_CHANNEL_ERR_DETECT" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" 65 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_CHANNEL_INIT_SM-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_CHANNEL_INIT_SM-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 127 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_CHANNEL_INIT_SM " "Info: Found entity 1: aurora_8b10b_v5_2_CHANNEL_INIT_SM" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 91 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_CHBOND_COUNT_DEC-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_CHBOND_COUNT_DEC-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" 76 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_CHBOND_COUNT_DEC " "Info: Found entity 1: aurora_8b10b_v5_2_CHBOND_COUNT_DEC" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" 64 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_ERR_DETECT-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_ERR_DETECT-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" 95 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_ERR_DETECT " "Info: Found entity 1: aurora_8b10b_v5_2_ERR_DETECT" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" 69 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_GLOBAL_LOGIC-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_GLOBAL_LOGIC-MAPPED" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 100 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_GLOBAL_LOGIC " "Info: Found entity 1: aurora_8b10b_v5_2_GLOBAL_LOGIC" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 63 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_IDLE_AND_VER_GEN-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_IDLE_AND_VER_GEN-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" 99 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_IDLE_AND_VER_GEN " "Info: Found entity 1: aurora_8b10b_v5_2_IDLE_AND_VER_GEN" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" 74 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_LANE_INIT_SM-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_LANE_INIT_SM-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" 120 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_LANE_INIT_SM " "Info: Found entity 1: aurora_8b10b_v5_2_LANE_INIT_SM" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" 71 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_RX_LL-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_RX_LL-MAPPED" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" 101 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_RX_LL " "Info: Found entity 1: aurora_8b10b_v5_2_RX_LL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" 65 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" 101 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH " "Info: Found entity 1: aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" 67 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_SYM_DEC-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_SYM_DEC-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" 105 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_SYM_DEC " "Info: Found entity 1: aurora_8b10b_v5_2_SYM_DEC" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" 66 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_SYM_GEN-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_SYM_GEN-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" 117 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_SYM_GEN " "Info: Found entity 1: aurora_8b10b_v5_2_SYM_GEN" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" 77 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_TX_LL-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL-MAPPED" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" 102 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_TX_LL " "Info: Found entity 1: aurora_8b10b_v5_2_TX_LL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" 63 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_TX_LL_CONTROL-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL_CONTROL-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" 109 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_TX_LL_CONTROL " "Info: Found entity 1: aurora_8b10b_v5_2_TX_LL_CONTROL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_TX_LL_DATAPATH-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL_DATAPATH-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" 94 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_TX_LL_DATAPATH " "Info: Found entity 1: aurora_8b10b_v5_2_TX_LL_DATAPATH" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" 62 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mgt156_to_156.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mgt156_to_156.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mgt156_to_156-SYN " "Info: Found design unit 1: mgt156_to_156-SYN" {  } { { "MGT156_to_156.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT156_to_156.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 MGT156_to_156 " "Info: Found entity 1: MGT156_to_156" {  } { { "MGT156_to_156.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT156_to_156.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_la.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pll_la.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll_la-SYN " "Info: Found design unit 1: pll_la-SYN" {  } { { "PLL_LA.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/PLL_LA.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 PLL_LA " "Info: Found entity 1: PLL_LA" {  } { { "PLL_LA.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/PLL_LA.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mgt.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file mgt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MGT_alt4gxb-RTL " "Info: Found design unit 1: MGT_alt4gxb-RTL" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 82 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 mgt-RTL " "Info: Found design unit 2: mgt-RTL" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 2118 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 MGT_alt4gxb " "Info: Found entity 1: MGT_alt4gxb" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 46 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 MGT " "Info: Found entity 2: MGT" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 2081 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "la.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file la.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 la-SYN " "Info: Found design unit 1: la-SYN" {  } { { "LA.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/LA.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 LA " "Info: Found entity 1: LA" {  } { { "LA.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/LA.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "aurora_8b10b_v5_2_example_design " "Info: Elaborating entity \"aurora_8b10b_v5_2_example_design\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "user_clk_i aurora_8b10b_v5_2_example_design.vhd(173) " "Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2_example_design.vhd(173): used implicit default value for signal \"user_clk_i\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 173 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "sync_clk_i aurora_8b10b_v5_2_example_design.vhd(174) " "Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2_example_design.vhd(174): used implicit default value for signal \"sync_clk_i\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 174 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tx_out_clk_i aurora_8b10b_v5_2_example_design.vhd(179) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_example_design.vhd(179): object \"tx_out_clk_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 179 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "la_clk aurora_8b10b_v5_2_example_design.vhd(442) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_example_design.vhd(442): object \"la_clk\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 442 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "ERR_COUNT_Buffer aurora_8b10b_v5_2_example_design.vhd(182) " "Warning (10873): Using initial value X (don't care) for net \"ERR_COUNT_Buffer\" at aurora_8b10b_v5_2_example_design.vhd(182)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 182 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "DIS_USER_CLK aurora_8b10b_v5_2_example_design.vhd(78) " "Warning (10873): Using initial value X (don't care) for net \"DIS_USER_CLK\" at aurora_8b10b_v5_2_example_design.vhd(78)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 78 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "HARD_ERR_Buffer aurora_8b10b_v5_2_example_design.vhd(117) " "Warning (10873): Using initial value X (don't care) for net \"HARD_ERR_Buffer\" at aurora_8b10b_v5_2_example_design.vhd(117)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 117 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "SOFT_ERR_Buffer aurora_8b10b_v5_2_example_design.vhd(118) " "Warning (10873): Using initial value X (don't care) for net \"SOFT_ERR_Buffer\" at aurora_8b10b_v5_2_example_design.vhd(118)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 118 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "FRAME_ERR_Buffer aurora_8b10b_v5_2_example_design.vhd(119) " "Warning (10873): Using initial value X (don't care) for net \"FRAME_ERR_Buffer\" at aurora_8b10b_v5_2_example_design.vhd(119)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 119 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LANE_UP_Buffer aurora_8b10b_v5_2_example_design.vhd(120) " "Warning (10873): Using initial value X (don't care) for net \"LANE_UP_Buffer\" at aurora_8b10b_v5_2_example_design.vhd(120)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 120 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "CHANNEL_UP_Buffer aurora_8b10b_v5_2_example_design.vhd(121) " "Warning (10873): Using initial value X (don't care) for net \"CHANNEL_UP_Buffer\" at aurora_8b10b_v5_2_example_design.vhd(121)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 121 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL_LA PLL_LA:LA_PLL " "Info: Elaborating entity \"PLL_LA\" for hierarchy \"PLL_LA:LA_PLL\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "LA_PLL" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 488 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL_LA:LA_PLL\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL_LA:LA_PLL\|altpll:altpll_component\"" {  } { { "PLL_LA.vhd" "altpll_component" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/PLL_LA.vhd" 135 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "PLL_LA:LA_PLL\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"PLL_LA:LA_PLL\|altpll:altpll_component\"" {  } { { "PLL_LA.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/PLL_LA.vhd" 135 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "PLL_LA:LA_PLL\|altpll:altpll_component " "Info: Instantiated megafunction \"PLL_LA:LA_PLL\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Info: Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 5 " "Info: Parameter \"clk0_divide_by\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 16 " "Info: Parameter \"clk0_multiply_by\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 6400 " "Info: Parameter \"inclk0_input_frequency\" = \"6400\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix IV " "Info: Parameter \"intended_device_family\" = \"Stratix IV\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=PLL_LA " "Info: Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=PLL_LA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Info: Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Info: Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Info: Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Info: Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Info: Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Info: Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Info: Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Info: Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Info: Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbout PORT_UNUSED " "Info: Parameter \"port_fbout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Info: Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Info: Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Info: Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Info: Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Info: Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Info: Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Info: Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Info: Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Info: Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Info: Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Info: Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Info: Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Info: Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Info: Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Info: Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Info: Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Info: Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Info: Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Info: Parameter \"port_clk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Info: Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Info: Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Info: Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Info: Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk6 PORT_UNUSED " "Info: Parameter \"port_clk6\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk7 PORT_UNUSED " "Info: Parameter \"port_clk7\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk8 PORT_UNUSED " "Info: Parameter \"port_clk8\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk9 PORT_UNUSED " "Info: Parameter \"port_clk9\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Info: Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Info: Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Info: Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Info: Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Info: Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Info: Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "using_fbmimicbidir_port OFF " "Info: Parameter \"using_fbmimicbidir_port\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 10 " "Info: Parameter \"width_clock\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "PLL_LA.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/PLL_LA.vhd" 135 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_la_altpll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/pll_la_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL_LA_altpll " "Info: Found entity 1: PLL_LA_altpll" {  } { { "db/pll_la_altpll.v" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/pll_la_altpll.v" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL_LA_altpll PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated " "Info: Elaborating entity \"PLL_LA_altpll\" for hierarchy \"PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/91/quartus/libraries/megafunctions/altpll.tdf" 884 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_FRAME_CHECK aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_FRAME_CHECK\" for hierarchy \"aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "frame_check_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 557 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_FRAME_GEN aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_FRAME_GEN\" for hierarchy \"aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "frame_gen_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 577 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2 aurora_8b10b_v5_2:aurora_module_i " "Info: Elaborating entity \"aurora_8b10b_v5_2\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "aurora_module_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 600 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "TXN aurora_8b10b_v5_2.vhd(102) " "Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2.vhd(102): used implicit default value for signal \"TXN\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 102 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ch_bond_load_not_used_i aurora_8b10b_v5_2.vhd(459) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(459): object \"ch_bond_load_not_used_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 459 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "chbondi_not_used_i aurora_8b10b_v5_2.vhd(462) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(462): object \"chbondi_not_used_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 462 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "en_chan_sync_i aurora_8b10b_v5_2.vhd(464) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(464): object \"en_chan_sync_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 464 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "raw_tx_out_clk_i aurora_8b10b_v5_2.vhd(491) " "Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2.vhd(491): used implicit default value for signal \"raw_tx_out_clk_i\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 491 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rx_data_width_i aurora_8b10b_v5_2.vhd(502) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(502): object \"rx_data_width_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 502 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rx_int_data_width_i aurora_8b10b_v5_2.vhd(506) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(506): object \"rx_int_data_width_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 506 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tied_to_ground_i aurora_8b10b_v5_2.vhd(524) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(524): object \"tied_to_ground_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 524 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tied_to_vcc_i aurora_8b10b_v5_2.vhd(526) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(526): object \"tied_to_vcc_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 526 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tx_data_width_i aurora_8b10b_v5_2.vhd(532) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(532): object \"tx_data_width_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 532 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tx_int_data_width_i aurora_8b10b_v5_2.vhd(533) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(533): object \"tx_int_data_width_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 533 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_AURORA_LANE aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_AURORA_LANE\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "aurora_lane_0_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 577 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_LANE_INIT_SM aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_LANE_INIT_SM\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "lane_init_sm_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 390 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FDR_Alan aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|FDR_Alan:lane_up_flop_i " "Info: Elaborating entity \"FDR_Alan\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|FDR_Alan:lane_up_flop_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" "lane_up_flop_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" 300 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_CHBOND_COUNT_DEC aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_CHBOND_COUNT_DEC\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "chbond_count_dec_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 442 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_SYM_GEN aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_SYM_GEN\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "sym_gen_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 455 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_SYM_DEC aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_SYM_DEC\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "sym_dec_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 496 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_ERR_DETECT aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_ERR_DETECT\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "err_detect_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 536 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MGT_alt4gxb aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0 " "Info: Elaborating entity \"MGT_alt4gxb\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "MGT_0" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 641 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "wire_receive_pcs0_signaldetect MGT.vhd(159) " "Warning (10036): Verilog HDL or VHDL warning at MGT.vhd(159): object \"wire_receive_pcs0_signaldetect\" assigned a value but never read" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 159 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "wire_transmit_pcs0_forceelecidleout MGT.vhd(177) " "Warning (10036): Verilog HDL or VHDL warning at MGT.vhd(177): object \"wire_transmit_pcs0_forceelecidleout\" assigned a value but never read" {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 177 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "refclkdividerdprioin MGT.vhd(239) " "Warning (10541): VHDL Signal Declaration warning at MGT.vhd(239): used implicit default value for signal \"refclkdividerdprioin\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "MGT.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/MGT.vhd" 239 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_GLOBAL_LOGIC aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_GLOBAL_LOGIC\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "global_logic_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 724 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_CHANNEL_INIT_SM aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_CHANNEL_INIT_SM\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "channel_init_sm_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 229 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tied_to_vcc aurora_8b10b_v5_2_channel_init_sm.vhd(174) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_channel_init_sm.vhd(174): object \"tied_to_vcc\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 174 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tied_to_gnd aurora_8b10b_v5_2_channel_init_sm.vhd(175) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_channel_init_sm.vhd(175): object \"tied_to_gnd\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 175 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FD_Alan aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i\|FD_Alan:reset_lanes_flop_i " "Info: Elaborating entity \"FD_Alan\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i\|FD_Alan:reset_lanes_flop_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "reset_lanes_flop_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 305 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_IDLE_AND_VER_GEN aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_IDLE_AND_VER_GEN\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "idle_and_ver_gen_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 266 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SRL16_Alan aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i " "Info: Elaborating entity \"SRL16_Alan\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" "ver_counter_0_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" 354 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPMSHIFTREG16 aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16 " "Info: Elaborating entity \"LPMSHIFTREG16\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\"" {  } { { "../../ReplaceXilinxComponent/SRL16_Alan.vhd" "lpm_shiftreg16" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/SRL16_Alan.vhd" 57 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_shiftreg aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborating entity \"lpm_shiftreg\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "../../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "lpm_shiftreg_component" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborated megafunction instantiation \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "../../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component " "Info: Instantiated megafunction \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction LEFT " "Info: Parameter \"lpm_direction\" = \"LEFT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_SHIFTREG " "Info: Parameter \"lpm_type\" = \"LPM_SHIFTREG\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Info: Parameter \"lpm_width\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "../../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 74 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MUX16to1 aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1 " "Info: Elaborating entity \"MUX16to1\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\"" {  } { { "../../ReplaceXilinxComponent/SRL16_Alan.vhd" "MUX_16to1" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/SRL16_Alan.vhd" 65 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_MUX aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component " "Info: Elaborating entity \"LPM_MUX\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\"" {  } { { "../../ReplaceXilinxComponent/MUX16to1.vhd" "lpm_mux_component" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/MUX16to1.vhd" 127 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component " "Info: Elaborated megafunction instantiation \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\"" {  } { { "../../ReplaceXilinxComponent/MUX16to1.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/MUX16to1.vhd" 127 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component " "Info: Instantiated megafunction \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 16 " "Info: Parameter \"LPM_SIZE\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 4 " "Info: Parameter \"LPM_WIDTHS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 0 " "Info: Parameter \"LPM_PIPELINE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MUX " "Info: Parameter \"LPM_TYPE\" = \"LPM_MUX\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Info: Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "../../ReplaceXilinxComponent/MUX16to1.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/ReplaceXilinxComponent/MUX16to1.vhd" 127 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_76e.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_76e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_76e " "Info: Found entity 1: mux_76e" {  } { { "db/mux_76e.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/mux_76e.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_76e aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\|mux_76e:auto_generated " "Info: Elaborating entity \"mux_76e\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\|mux_76e:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "c:/altera/91/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_CHANNEL_ERR_DETECT aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_CHANNEL_ERR_DETECT\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "channel_err_detect_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 293 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_TX_LL aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_TX_LL\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "tx_ll_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 762 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_TX_LL_DATAPATH aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_TX_LL_DATAPATH\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" "tx_ll_datapath_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" 213 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_TX_LL_CONTROL aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_TX_LL_CONTROL\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" "tx_ll_control_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" 246 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "channel_full_c aurora_8b10b_v5_2_tx_ll_control.vhd(153) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_tx_ll_control.vhd(153): object \"channel_full_c\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" 153 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_RX_LL aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_RX_LL:rx_ll_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_RX_LL\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_RX_LL:rx_ll_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "rx_ll_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 802 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_RX_LL:rx_ll_i\|aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_RX_LL:rx_ll_i\|aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" "rx_ll_pdu_datapath_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" 167 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_STANDARD_CC_MODULE aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_STANDARD_CC_MODULE\" for hierarchy \"aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "standard_cc_module_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 663 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_RESET_LOGIC aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_RESET_LOGIC\" for hierarchy \"aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "reset_logic_i" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 680 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sos3.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sos3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sos3 " "Info: Found entity 1: altsyncram_sos3" {  } { { "db/altsyncram_sos3.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/altsyncram_sos3.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_opc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_opc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_opc " "Info: Found entity 1: mux_opc" {  } { { "db/mux_opc.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/mux_opc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_asf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_asf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_asf " "Info: Found entity 1: decode_asf" {  } { { "db/decode_asf.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/decode_asf.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_kdi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_kdi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_kdi " "Info: Found entity 1: cntr_kdi" {  } { { "db/cntr_kdi.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/cntr_kdi.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_qdc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_qdc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_qdc " "Info: Found entity 1: cmpr_qdc" {  } { { "db/cmpr_qdc.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/cmpr_qdc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_d6j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_d6j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_d6j " "Info: Found entity 1: cntr_d6j" {  } { { "db/cntr_d6j.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/cntr_d6j.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_bdi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_bdi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_bdi " "Info: Found entity 1: cntr_bdi" {  } { { "db/cntr_bdi.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/cntr_bdi.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_odc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_odc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_odc " "Info: Found entity 1: cmpr_odc" {  } { { "db/cmpr_odc.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/cmpr_odc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_vvi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_vvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_vvi " "Info: Found entity 1: cntr_vvi" {  } { { "db/cntr_vvi.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/cntr_vvi.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_kdc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_kdc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_kdc " "Info: Found entity 1: cmpr_kdc" {  } { { "db/cmpr_kdc.tdf" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/db/cmpr_kdc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 0 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "aurora_8b10b_v5_2:aurora_module_i\|comb~synth " "Warning: Converted tri-state buffer \"aurora_8b10b_v5_2:aurora_module_i\|comb~synth\" feeding internal logic into a wire" {  } {  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "aurora_8b10b_v5_2:aurora_module_i\|comb~synth " "Warning: Converted tri-state buffer \"aurora_8b10b_v5_2:aurora_module_i\|comb~synth\" feeding internal logic into a wire" {  } {  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "aurora_8b10b_v5_2:aurora_module_i\|comb~synth " "Warning: Converted tri-state buffer \"aurora_8b10b_v5_2:aurora_module_i\|comb~synth\" feeding internal logic into a wire" {  } {  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "aurora_8b10b_v5_2:aurora_module_i\|comb~synth " "Warning: Converted tri-state buffer \"aurora_8b10b_v5_2:aurora_module_i\|comb~synth\" feeding internal logic into a wire" {  } {  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1}  } {  } 0 0 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DIS_USER_CLK GND " "Warning (13410): Pin \"DIS_USER_CLK\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 78 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HARD_ERR VCC " "Warning (13410): Pin \"HARD_ERR\" is stuck at VCC" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 83 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "SOFT_ERR VCC " "Warning (13410): Pin \"SOFT_ERR\" is stuck at VCC" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 84 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "FRAME_ERR VCC " "Warning (13410): Pin \"FRAME_ERR\" is stuck at VCC" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 85 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ERR_COUNT\[7\] GND " "Warning (13410): Pin \"ERR_COUNT\[7\]\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ERR_COUNT\[6\] GND " "Warning (13410): Pin \"ERR_COUNT\[6\]\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ERR_COUNT\[5\] GND " "Warning (13410): Pin \"ERR_COUNT\[5\]\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ERR_COUNT\[4\] GND " "Warning (13410): Pin \"ERR_COUNT\[4\]\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ERR_COUNT\[3\] GND " "Warning (13410): Pin \"ERR_COUNT\[3\]\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ERR_COUNT\[2\] GND " "Warning (13410): Pin \"ERR_COUNT\[2\]\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ERR_COUNT\[1\] GND " "Warning (13410): Pin \"ERR_COUNT\[1\]\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "ERR_COUNT\[0\] GND " "Warning (13410): Pin \"ERR_COUNT\[0\]\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LANE_UP VCC " "Warning (13410): Pin \"LANE_UP\" is stuck at VCC" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 87 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "CHANNEL_UP VCC " "Warning (13410): Pin \"CHANNEL_UP\" is stuck at VCC" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 88 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "TXN GND " "Warning (13410): Pin \"TXN\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 101 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_1_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[15\] " "Info: Register \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16_Alan:ver_counter_1_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Critical Warning" "WAMERGE_SLD_INSTANCE_WITH_INVALID_CONNECTIONS" "auto_signaltap_0 149 151 0 0 2 " "Critical Warning: Partially connected in-system debug instance \"auto_signaltap_0\" to 149 of its 151 required data inputs, trigger inputs, acquisition clocks, and dynamic pins.  There were 0 illegal, 0 inaccessible, and 2 missing sources or connections." {  } {  } 1 0 "Partially connected in-system debug instance \"%1!s!\" to %2!d! of its %3!d! required data inputs, trigger inputs, acquisition clocks, and dynamic pins.  There were %4!d! illegal, %5!d! inaccessible, and %6!d! missing sources or connections." 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "RESET " "Warning (15610): No output dependent on input pin \"RESET\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 82 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GT_RESET_IN " "Warning (15610): No output dependent on input pin \"GT_RESET_IN\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 90 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "RXN " "Warning (15610): No output dependent on input pin \"RXN\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "D:/program/FPGA/Final_test/ALTERA/Virtex6Aurora/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 99 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1510 " "Info: Implemented 1510 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "1394 " "Info: Implemented 1394 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "75 " "Info: Implemented 75 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 PLLs" {  } {  } 0 0 "Implemented %1!d! PLLs" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 61 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 61 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Info: Peak virtual memory: 303 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 23 01:43:46 2010 " "Info: Processing ended: Thu Dec 23 01:43:46 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Info: Total CPU time (on all processors): 00:00:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
