-------------------------------------------------------------------------------
-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- 
-- 
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : 
--  /   /         Filename : aurora_8b10b_v5_2_GTX_WRAPPER.vhd
-- /___/   /\     Timestamp : 02/16/2005 10:19:02
-- \   \  /  \ 
--  \___\/\___\ 
--------------------------------------------------------------------------------
--Command: 
--Design Name: aurora_8b10b_v5_2_GTX_WRAPPER
--
-- Module aurora_8b10b_v5_2_GTX_WRAPPER
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity aurora_8b10b_v5_2_GTX_WRAPPER is
generic
(
    SIM_GTXRESET_SPEEDUP :integer :=   0      --Set to 1 to speed up sim reset
);   

port
(

---------------------- Loopback and Powerdown Ports ----------------------
LOOPBACK_IN                               : in    std_logic_vector (2 downto 0);
--------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA_OUT : out   std_logic_vector (1 downto 0); 
RXCHARISK_OUT     : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT     : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT  : out   std_logic_vector (1 downto 0);

----------------- Receive Ports - Channel Bonding Ports -----------------
ENCHANSYNC_IN     : in    std_logic;
CHBONDDONE_OUT    : out   std_logic;

----------------- Receive Ports - Clock Correction Ports -----------------
RXBUFERR_OUT      : out   std_logic;

------------- Receive Ports - Comma Detection and Alignment --------------
RXREALIGN_OUT     : out   std_logic;
ENMCOMMAALIGN_IN  : in    std_logic;
ENPCOMMAALIGN_IN  : in    std_logic;

----------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT        : out   std_logic_vector (15 downto 0);
RXRECCLK1_OUT     : out   std_logic;
RXRECCLK2_OUT     : out   std_logic;
RXRESET_IN        : in    std_logic;
RXUSRCLK_IN                               : in    std_logic;
RXUSRCLK2_IN                              : in    std_logic;
----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RX1N_IN           : in    std_logic;
RX1P_IN           : in    std_logic;

--------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY_IN     : in    std_logic;

------------------- Shared Ports - Tile and PLL Ports --------------------
REFCLK                                    : in    std_logic;
GTXRESET_IN                               : in    std_logic;
PLLLKDET_OUT      : out   std_logic;

POWERDOWN_IN                              : in    std_logic;                  

-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARISK_IN      : in    std_logic_vector (1 downto 0);

---------------- Transmit Ports - TX Data Path interface -----------------
TXDATA_IN         : in    std_logic_vector (15 downto 0);
TXOUTCLK1_OUT     : out   std_logic;
TXOUTCLK2_OUT     : out   std_logic;
TXRESET_IN        : in    std_logic;
 
TXUSRCLK_IN                               : in    std_logic;       
TXUSRCLK2_IN                              : in    std_logic;
TXBUFERR_OUT      : out   std_logic;

------------- Transmit Ports - TX Driver and OOB signalling --------------
TX1N_OUT          : out   std_logic;
TX1P_OUT          : out   std_logic
);

end aurora_8b10b_v5_2_GTX_WRAPPER;


architecture BEHAVIORAL of aurora_8b10b_v5_2_GTX_WRAPPER is
  attribute core_generation_info               : string;
  attribute core_generation_info of BEHAVIORAL : architecture is "aurora_8b10b_v5_2,aurora_8b10b_v5_2,{backchannel_mode=Sidebands, c_aurora_lanes=1, c_column_used=left, c_gt_clock_1=GTXQ4, c_gt_clock_2=None, c_gt_loc_1=X, c_gt_loc_10=X, c_gt_loc_11=X, c_gt_loc_12=X, c_gt_loc_13=X, c_gt_loc_14=X, c_gt_loc_15=X, c_gt_loc_16=X, c_gt_loc_17=X, c_gt_loc_18=X, c_gt_loc_19=1, c_gt_loc_2=X, c_gt_loc_20=X, c_gt_loc_21=X, c_gt_loc_22=X, c_gt_loc_23=X, c_gt_loc_24=X, c_gt_loc_25=X, c_gt_loc_26=X, c_gt_loc_27=X, c_gt_loc_28=X, c_gt_loc_29=X, c_gt_loc_3=X, c_gt_loc_30=X, c_gt_loc_31=X, c_gt_loc_32=X, c_gt_loc_33=X, c_gt_loc_34=X, c_gt_loc_35=X, c_gt_loc_36=X, c_gt_loc_37=X, c_gt_loc_38=X, c_gt_loc_39=X, c_gt_loc_4=X, c_gt_loc_40=X, c_gt_loc_41=X, c_gt_loc_42=X, c_gt_loc_43=X, c_gt_loc_44=X, c_gt_loc_45=X, c_gt_loc_46=X, c_gt_loc_47=X, c_gt_loc_48=X, c_gt_loc_5=X, c_gt_loc_6=X, c_gt_loc_7=X, c_gt_loc_8=X, c_gt_loc_9=X, c_lane_width=2, c_line_rate=3.125, c_nfc=false, c_nfc_mode=IMM, c_refclk_frequency=125.0, c_simplex=false, c_simplex_mode=TX, c_stream=false, c_ufc=false, flow_mode=None, interface_mode=Framing, dataflow_config=Duplex}";
--***************************** Compopnent Declaration ****************************
component aurora_8b10b_v5_2_GTXE1 is
generic
(
    -- Simulation attributes
    GTX_SIM_TXREFCLK_SOURCE                 : bit_vector := "000";
    GTX_SIM_RXREFCLK_SOURCE                 : bit_vector := "000";
    GTX_SIM_GTXRESET_SPEEDUP                : integer    := 0;
    
    -- Share RX PLL parameter
    GTX_TX_CLK_SOURCE                       : string     := "TXPLL"
);
port 
(
    ------------------------ Loopback and Powerdown Ports ----------------------
    LOOPBACK_IN                             : in   std_logic_vector(2 downto 0);
    RXPOWERDOWN_IN   	                    : in   std_logic_vector(1 downto 0);
    TXPOWERDOWN_IN   	                    : in   std_logic_vector(1 downto 0);
    ----------------------- Receive Ports - 8b10b Decoder ----------------------
    RXCHARISCOMMA_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXCHARISK_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXDISPERR_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXNOTINTABLE_OUT 		     	    : out std_logic_vector(1 downto 0);
    ------------------- Receive Ports - Clock Correction Ports--
    RXCLKCORCNT_OUT                         : out  std_logic_vector(2 downto 0);
    --------------- Receive Ports - Comma Detection and Alignment --------------
    RXBYTEREALIGN_OUT                       : out  std_logic;
    RXENMCOMMAALIGN_IN                      : in   std_logic;
    RXENPCOMMAALIGN_IN                      : in   std_logic;
    ------------------- Receive Ports - RX Data Path interface -----------------
    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
    RXRECCLK_OUT                            : out  std_logic;
    RXRESET_IN                              : in   std_logic;
    RXUSRCLK_IN                             : in   std_logic;
    RXUSRCLK2_IN                            : in   std_logic;
    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
    RXCDRRESET_IN                           : in   std_logic;
    RXN_IN                                  : in   std_logic;
    RXP_IN                                  : in   std_logic;
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    RXBUFSTATUS_OUT                         : out  std_logic_vector(2 downto 0);
    RXCHANISALIGNED_OUT                     : out  std_logic;
    ------------------------ Receive Ports - RX PLL Ports ----------------------
    GREFCLKRX_IN                            : in   std_logic;
    GTXRXRESET_IN                           : in   std_logic;
    MGTREFCLKRX_IN                          : in   std_logic_vector(1 downto 0);
    NORTHREFCLKRX_IN                        : in   std_logic_vector(1 downto 0);
    PERFCLKRX_IN                            : in   std_logic;
    PLLRXRESET_IN                           : in   std_logic;
    RXPLLLKDET_OUT                          : out  std_logic;
    RXRESETDONE_OUT                         : out  std_logic;
    SOUTHREFCLKRX_IN                        : in   std_logic_vector(1 downto 0);
    ----------------- Receive Ports - RX Polarity Control Ports ----------------
    RXPOLARITY_IN                          : in   std_logic;
    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
    TXCHARISK_IN			    : in std_logic_vector(1 downto 0);
    ------------------ Transmit Ports - TX Data Path interface -----------------
    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
    TXOUTCLK_OUT                            : out  std_logic;
    TXRESET_IN                              : in   std_logic;
    TXUSRCLK_IN                             : in   std_logic;
    TXUSRCLK2_IN                            : in   std_logic;
    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
    TXN_OUT                                 : out  std_logic;
    TXP_OUT                                 : out  std_logic;
    --------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
    TXBUFSTATUS_OUT                         : out  std_logic_vector(1 downto 0);
    ----------------------- Transmit Ports - TX PLL Ports ----------------------
    GREFCLKTX_IN                            : in   std_logic;
    GTXTXRESET_IN                           : in   std_logic;
    MGTREFCLKTX_IN                          : in   std_logic_vector(1 downto 0);
    NORTHREFCLKTX_IN                        : in   std_logic_vector(1 downto 0);
    PERFCLKTX_IN                            : in   std_logic;
    PLLTXRESET_IN                           : in   std_logic;
    SOUTHREFCLKTX_IN                        : in   std_logic_vector(1 downto 0);
    TXPLLLKDET_OUT                          : out  std_logic;
    TXRESETDONE_OUT                         : out  std_logic

);
end component;

   signal tied_to_ground_i                               : std_logic;
   signal tied_to_ground_vec_i                           : std_logic_vector (63 downto 0);
   signal tied_to_vcc_i                                  : std_logic;
   signal chbondi                 : std_logic_vector (3 downto 0);
   signal chbondo                 : std_logic_vector (3 downto 0);
   signal open_rxbufstatus        : std_logic_vector (1 downto 0);
   signal open_txbufstatus        : std_logic;
   signal chbondi_unused_i                                    : std_logic_vector (3 downto 0);

   --signal to output lock signal
   signal tx_plllkdet_o          : std_logic;
   signal rx_plllkdet_o          : std_logic;


begin

  tied_to_ground_i                    <= '0';
  tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
  tied_to_vcc_i                       <= '1';

--Assign lock signals
  PLLLKDET_OUT  <=   rx_plllkdet_o;

  chbondi_unused_i  <= "0000";

   --Connect channel bonding bus
 
   chbondi <= chbondi_unused_i;
------------------------- GTX Instantiations  --------------------------   
   GTXE1_INST : aurora_8b10b_v5_2_GTXE1  
    generic map
    (
        -- Simulation attributes
        GTX_SIM_TXREFCLK_SOURCE             => "000",
        GTX_SIM_RXREFCLK_SOURCE             => "000",
        GTX_SIM_GTXRESET_SPEEDUP            => SIM_GTXRESET_SPEEDUP,
        
        -- Share RX PLL parameter
        GTX_TX_CLK_SOURCE                   => "RXPLL"

    )
    port map
    (
        ------------------------ Loopback and Powerdown Ports ----------------------
        LOOPBACK_IN                     =>      LOOPBACK_IN,
        RXPOWERDOWN_IN(0)               =>      POWERDOWN_IN,
        RXPOWERDOWN_IN(1)               =>      POWERDOWN_IN,
        TXPOWERDOWN_IN(0)               =>      POWERDOWN_IN,
        TXPOWERDOWN_IN(1)               =>      POWERDOWN_IN,
        ----------------------- Receive Ports - 8b10b Decoder ----------------------
        RXCHARISCOMMA_OUT               =>      RXCHARISCOMMA_OUT,
        RXCHARISK_OUT                   =>      RXCHARISK_OUT,
        RXDISPERR_OUT                   =>      RXDISPERR_OUT,
        RXNOTINTABLE_OUT                =>      RXNOTINTABLE_OUT,
        ------------------- Receive Ports - Channel Bonding Ports ------------------
        ------------------- Receive Ports - Clock Correction Ports -----------------
        RXCLKCORCNT_OUT                 =>      OPEN,
        --------------- Receive Ports - Comma Detection and Alignment --------------
        RXBYTEREALIGN_OUT               =>      RXREALIGN_OUT,
        RXENMCOMMAALIGN_IN              =>      ENMCOMMAALIGN_IN,
        RXENPCOMMAALIGN_IN              =>      ENPCOMMAALIGN_IN,
        ------------------- Receive Ports - RX Data Path interface -----------------
        RXDATA_OUT                      =>      RXDATA_OUT,
        RXRECCLK_OUT                    =>      RXRECCLK1_OUT,
 
        RXRESET_IN                      =>      RXRESET_IN,
        RXUSRCLK_IN                     =>      RXUSRCLK_IN,
        RXUSRCLK2_IN                    =>      RXUSRCLK2_IN,
        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
        RXCDRRESET_IN                   =>      tied_to_ground_i,
        RXN_IN                          =>      RX1N_IN,
        RXP_IN                          =>      RX1P_IN,
        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        RXBUFSTATUS_OUT(2)              =>      RXBUFERR_OUT ,
        RXBUFSTATUS_OUT(1 downto 0)     =>      open_rxbufstatus(1 downto 0),
        RXCHANISALIGNED_OUT             =>      CHBONDDONE_OUT,
        ------------------------ Receive Ports - RX PLL Ports ----------------------
        GREFCLKRX_IN                    =>      tied_to_ground_i,
        GTXRXRESET_IN                   =>      GTXRESET_IN,
        MGTREFCLKRX_IN(1)               =>      tied_to_ground_i,
        MGTREFCLKRX_IN(0)               =>      REFCLK,  
        NORTHREFCLKRX_IN                =>      tied_to_ground_vec_i(1 downto 0),
        PERFCLKRX_IN                    =>      tied_to_ground_i,
        PLLRXRESET_IN                   =>      tied_to_ground_i,
        RXPLLLKDET_OUT                  =>      rx_plllkdet_o,
        RXRESETDONE_OUT                 =>      OPEN,
        SOUTHREFCLKRX_IN                =>      tied_to_ground_vec_i(1 downto 0),
        ----------------- Receive Ports - RX Polarity Control Ports ----------------
        RXPOLARITY_IN                   =>      RXPOLARITY_IN,
        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
        TXCHARISK_IN                    =>      TXCHARISK_IN,
        ------------------ Transmit Ports - TX Data Path interface -----------------
        TXDATA_IN                       =>      TXDATA_IN,
        TXOUTCLK_OUT                    =>      TXOUTCLK1_OUT,
        TXRESET_IN                      =>      TXRESET_IN,
        TXUSRCLK_IN                     =>      TXUSRCLK_IN,
        TXUSRCLK2_IN                    =>      TXUSRCLK2_IN,
        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
        TXN_OUT                         =>      TX1N_OUT,
        TXP_OUT                         =>      TX1P_OUT,
        --------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
        TXBUFSTATUS_OUT(1)              =>      TXBUFERR_OUT ,
        TXBUFSTATUS_OUT(0)              =>      open_txbufstatus,
        ----------------------- Transmit Ports - TX PLL Ports ----------------------
        GREFCLKTX_IN                    =>      tied_to_ground_i,
        GTXTXRESET_IN                   =>      GTXRESET_IN,
        MGTREFCLKTX_IN(1)               =>      tied_to_ground_i,
        MGTREFCLKTX_IN(0)               =>      REFCLK,  
        NORTHREFCLKTX_IN                =>      tied_to_ground_vec_i(1 downto 0),
        PERFCLKTX_IN                    =>      tied_to_ground_i,
        PLLTXRESET_IN                   =>      tied_to_ground_i,
        TXPLLLKDET_OUT                  =>      tx_plllkdet_o,
        TXRESETDONE_OUT                 =>      OPEN,
        SOUTHREFCLKTX_IN                =>      tied_to_ground_vec_i(1 downto 0)

    );

end BEHAVIORAL;   
