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-- 

--
--  CHANNEL_ERR_DETECT
--
--
--  Description: the CHANNEL_ERR_DETECT module monitors the error signals
--               from the Aurora Lanes in the channel.  If one or more errors
--               are detected, the error is reported as a channel error.  If
--               a hard error is detected, it sends a message to the channel
--               initialization state machine to reset the channel.
--
--               This module supports 1 2-byte lane designs
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity aurora_8b10b_v5_2_CHANNEL_ERR_DETECT is

    port (

    -- Aurora Lane Interface

            SOFT_ERR         : in std_logic;
            HARD_ERR         : in std_logic;
            LANE_UP            : in std_logic;

    -- System Interface

            USER_CLK           : in std_logic;
            POWER_DOWN         : in std_logic;

            CHANNEL_SOFT_ERR : out std_logic;
            CHANNEL_HARD_ERR : out std_logic;

    -- Channel Init SM Interface

            RESET_CHANNEL      : out std_logic

         );

end aurora_8b10b_v5_2_CHANNEL_ERR_DETECT;

architecture RTL of aurora_8b10b_v5_2_CHANNEL_ERR_DETECT is

-- Parameter Declarations --

    constant DLY : time := 1 ns;

-- External Register Declarations --

    signal CHANNEL_SOFT_ERR_Buffer : std_logic := '1';
    signal CHANNEL_HARD_ERR_Buffer : std_logic := '1';
    signal RESET_CHANNEL_Buffer      : std_logic := '1';

-- Internal Register Declarations --

    signal soft_err_r : std_logic;
    signal hard_err_r : std_logic;
    signal lane_up_r  : std_logic;

-- Wire Declarations --

    signal channel_soft_err_c : std_logic;
    signal channel_hard_err_c : std_logic;
    signal reset_channel_c      : std_logic;

begin

    CHANNEL_SOFT_ERR <= CHANNEL_SOFT_ERR_Buffer;
    CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer;
    RESET_CHANNEL      <= RESET_CHANNEL_Buffer;

-- Main Body of Code --

    -- Register all of the incoming error signals.  This is neccessary for timing.

    process (USER_CLK)

    begin

        if (USER_CLK 'event and USER_CLK = '1') then

            soft_err_r <= SOFT_ERR after DLY;
            hard_err_r <= HARD_ERR after DLY;

        end if;

    end process;


    -- Assert Channel soft error if any of the soft error signals are asserted.

    channel_soft_err_c <= soft_err_r;

    process (USER_CLK)

    begin

        if (USER_CLK 'event and USER_CLK = '1') then

            CHANNEL_SOFT_ERR_Buffer <= channel_soft_err_c after DLY;

        end if;

    end process;


    -- Assert Channel hard error if any of the hard error signals are asserted.

    channel_hard_err_c <= hard_err_r;

    process (USER_CLK)

    begin

        if (USER_CLK 'event and USER_CLK = '1') then

            CHANNEL_HARD_ERR_Buffer <= channel_hard_err_c after DLY;

        end if;

    end process;

    -- FF stage added for timing closure
    process (USER_CLK)

    begin

        if (USER_CLK 'event and USER_CLK = '1') then

            lane_up_r <= LANE_UP after DLY;

        end if;

    end process;

    -- "reset_channel_c" is asserted when any of the LANE_UP signals are low.

    reset_channel_c <= not lane_up_r;

    process (USER_CLK)

    begin

        if (USER_CLK 'event and USER_CLK = '1') then

            RESET_CHANNEL_Buffer <= reset_channel_c or POWER_DOWN after DLY;

        end if;

    end process;

end RTL;
