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---------------------------------------------------------------------------------------------
--  AURORA_EXAMPLE
--
--  Aurora Generator
--
--
--
--  Description: Sample Instantiation of a 1 2-byte lane module.
--               Only tests initialization in hardware.
--
--         

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.all;
use WORK.AURORA_PKG.all;

-- synthesis translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synthesis translate_on

entity aurora_8b10b_v5_2_example_design is
   generic(
           USE_CHIPSCOPE          : integer :=   0;
           SIM_GTXRESET_SPEEDUP   : integer :=   1      --Set to 1 to speed up sim reset
         );
    port (

    -- User I/O
			DIS_USER_CLK 		: out std_logic;
			DIS_TX_CLK : out std_logic;
			DIS_RX_CLK : out std_logic;
			GXB_DOWN : in std_logic;
            RESET             : in std_logic;
            HARD_ERR          : out std_logic;
            SOFT_ERR          : out std_logic;
            FRAME_ERR         : out std_logic;
            ERR_COUNT         : out std_logic_vector(0 to 7);
            LANE_UP           : out std_logic;
            CHANNEL_UP        : out std_logic;
            INIT_CLK         : in std_logic;
            GT_RESET_IN       : in  std_logic;

    -- Clocks

			GTXQ4    : in  std_logic;

   -- V5 I/O

            RXP               : in std_logic;
            RXN               : in std_logic;
            TXP               : out std_logic;
            TXN               : out std_logic

         );

end aurora_8b10b_v5_2_example_design;

architecture MAPPED of aurora_8b10b_v5_2_example_design is
  attribute core_generation_info           : string;
  attribute core_generation_info of MAPPED : architecture is "aurora_8b10b_v5_2,aurora_8b10b_v5_2,{backchannel_mode=Sidebands, c_aurora_lanes=1, c_column_used=left, c_gt_clock_1=GTXQ4, c_gt_clock_2=None, c_gt_loc_1=X, c_gt_loc_10=X, c_gt_loc_11=X, c_gt_loc_12=X, c_gt_loc_13=X, c_gt_loc_14=X, c_gt_loc_15=X, c_gt_loc_16=X, c_gt_loc_17=X, c_gt_loc_18=X, c_gt_loc_19=1, c_gt_loc_2=X, c_gt_loc_20=X, c_gt_loc_21=X, c_gt_loc_22=X, c_gt_loc_23=X, c_gt_loc_24=X, c_gt_loc_25=X, c_gt_loc_26=X, c_gt_loc_27=X, c_gt_loc_28=X, c_gt_loc_29=X, c_gt_loc_3=X, c_gt_loc_30=X, c_gt_loc_31=X, c_gt_loc_32=X, c_gt_loc_33=X, c_gt_loc_34=X, c_gt_loc_35=X, c_gt_loc_36=X, c_gt_loc_37=X, c_gt_loc_38=X, c_gt_loc_39=X, c_gt_loc_4=X, c_gt_loc_40=X, c_gt_loc_41=X, c_gt_loc_42=X, c_gt_loc_43=X, c_gt_loc_44=X, c_gt_loc_45=X, c_gt_loc_46=X, c_gt_loc_47=X, c_gt_loc_48=X, c_gt_loc_5=X, c_gt_loc_6=X, c_gt_loc_7=X, c_gt_loc_8=X, c_gt_loc_9=X, c_lane_width=2, c_line_rate=3.125, c_nfc=false, c_nfc_mode=IMM, c_refclk_frequency=125.0, c_simplex=false, c_simplex_mode=TX, c_stream=false, c_ufc=false, flow_mode=None, interface_mode=Framing, dataflow_config=Duplex}";

-- Parameter Declarations --

    constant DLY : time := 1 ns;

-- External Register Declarations --

    signal HARD_ERR_Buffer    : std_logic;
    signal SOFT_ERR_Buffer    : std_logic;
    signal FRAME_ERR_Buffer   : std_logic;
    signal LANE_UP_Buffer     : std_logic;
    signal CHANNEL_UP_Buffer  : std_logic;
    signal TXP_Buffer         : std_logic;
    signal TXN_Buffer         : std_logic;

-- Internal Register Declarations --

    signal gt_reset_i         : std_logic; 
    signal system_reset_i     : std_logic;
 
-- Wire Declarations --

    -- LocalLink TX Interface

    signal tx_d_i             : std_logic_vector(0 to 15);
    signal tx_rem_i           : std_logic;
    signal tx_src_rdy_n_i     : std_logic;
    signal tx_sof_n_i         : std_logic;
    signal tx_eof_n_i         : std_logic;

    signal tx_dst_rdy_n_i     : std_logic;

    -- LocalLink RX Interface

    signal rx_d_i             : std_logic_vector(0 to 15);
    signal rx_rem_i           : std_logic;
    signal rx_src_rdy_n_i     : std_logic;
    signal rx_sof_n_i         : std_logic;
    signal rx_eof_n_i         : std_logic;


    -- V5 Reference Clock Interface
    signal GTXQ4_left_i      : std_logic;

    -- Error Detection Interface

    signal hard_err_i       : std_logic;
    signal soft_err_i       : std_logic;
    signal frame_err_i      : std_logic;

    -- Status

    signal channel_up_i       : std_logic;
    signal lane_up_i          : std_logic;

    -- Clock Compensation Control Interface

    signal warn_cc_i          : std_logic;
    signal do_cc_i            : std_logic;

    -- System Interface

    signal pll_not_locked_i   : std_logic;
    signal user_clk_i         : std_logic;
    signal sync_clk_i         : std_logic;
    signal reset_i            : std_logic;
    signal power_down_i       : std_logic;
    signal loopback_i         : std_logic_vector(2 downto 0);
    signal tx_lock_i          : std_logic;
    signal tx_out_clk_i       : std_logic;
    --Frame check signals
    signal err_count_i      : std_logic_vector(0 to 7);
    signal ERR_COUNT_Buffer : std_logic_vector(0 to 7);

-- VIO Signals
   signal icon_to_vio_i       : std_logic_vector (35 downto 0);
   signal sync_in_i           : std_logic_vector (0 to 63);
   signal sync_out_i          : std_logic_vector (0 to 15);


   signal lane_up_i_i  	      : std_logic;
   signal tx_lock_i_i  	      : std_logic;
   signal lane_up_reduce_i    : std_logic;
   attribute ASYNC_REG        : string;
   attribute ASYNC_REG of tx_lock_i  : signal is "TRUE";

-- Component Declarations --

    component IBUFDS_GTXE1

    generic(

      CLKCM_CFG	    : boolean       := TRUE;
      CLKRCV_TRST   : boolean       := TRUE;
      REFCLKOUT_DLY : bit_vector    := b"0000000000"
      );

    port(
      O       : out std_ulogic;
      ODIV2   : out std_ulogic;

      CEB     : in  std_ulogic;
      I       : in  std_ulogic;
      IB      : in  std_ulogic
       );

    end component; 
    component IBUFDS
        port (

                O : out std_ulogic;
                I : in std_ulogic;
                IB : in std_ulogic);

    end component;

    component IBUFG

        port (

                O : out std_ulogic;
                I : in  std_ulogic

             );
    
    end component;


    component aurora_8b10b_v5_2_CLOCK_MODULE
        port (
                GT_CLK                  : in std_logic;
                GT_CLK_LOCKED           : in std_logic;
                USER_CLK                : out std_logic;
                SYNC_CLK                : out std_logic;
                PLL_NOT_LOCKED          : out std_logic
             );
    end component;

    component aurora_8b10b_v5_2_RESET_LOGIC
        port (
                RESET                  : in std_logic;
                USER_CLK               : in std_logic;
                INIT_CLK             : in std_logic;
                GT_RESET_IN            : in std_logic;
                TX_LOCK_IN             : in std_logic;
                PLL_NOT_LOCKED         : in std_logic;

                SYSTEM_RESET           : out std_logic;
                GT_RESET_OUT           : out std_logic
             );
    end component;

    component aurora_8b10b_v5_2
        generic(
                 SIM_GTXRESET_SPEEDUP :integer := 1
               );
        port   (
            
            rxclk :out std_logic;
			txclk :out std_logic;
			GXB_DOWN : in std_logic;
        -- LocalLink TX Interface

                TX_D             : in std_logic_vector(0 to 15);
                TX_REM           : in std_logic;
                TX_SRC_RDY_N     : in std_logic;
                TX_SOF_N         : in std_logic;
                TX_EOF_N         : in std_logic;
                TX_DST_RDY_N     : out std_logic;

        -- LocalLink RX Interface

                RX_D             : out std_logic_vector(0 to 15);
                RX_REM           : out std_logic;
                RX_SRC_RDY_N     : out std_logic;
                RX_SOF_N         : out std_logic;
                RX_EOF_N         : out std_logic;
        -- V5 Serial I/O

                RXP              : in std_logic;
                RXN              : in std_logic;

                TXP              : out std_logic;
                TXN              : out std_logic;

        -- V5 Reference Clock Interface

                GTXQ4    : in std_logic;
        -- Error Detection Interface

                HARD_ERR       : out std_logic;
                SOFT_ERR       : out std_logic;
                
                FRAME_ERR      : out std_logic;

        -- Status

                CHANNEL_UP       : out std_logic;
                LANE_UP          : out std_logic;

        -- Clock Compensation Control Interface

                WARN_CC          : in std_logic;
                DO_CC            : in std_logic;

        -- System Interface
				INIT_CLK		 : in  std_logic;
                USER_CLK         : in std_logic;
                SYNC_CLK         : in std_logic;
                GT_RESET         : in std_logic;
                RESET            : in std_logic;
                POWER_DOWN       : in std_logic;
                LOOPBACK         : in std_logic_vector(2 downto 0);
                TX_OUT_CLK       : out std_logic;
                TX_LOCK          : out std_logic
            );

    end component;


    component aurora_8b10b_v5_2_STANDARD_CC_MODULE

        port (

        -- Clock Compensation Control Interface

                WARN_CC        : out std_logic;
                DO_CC          : out std_logic;

        -- System Interface

                PLL_NOT_LOCKED : in std_logic;
                USER_CLK       : in std_logic;
                RESET          : in std_logic

             );

    end component;
    
 
    component aurora_8b10b_v5_2_FRAME_GEN
    port
    (
        -- User Interface
        TX_D            : out  std_logic_vector(0 to 15); 
        TX_REM          : out  std_logic;     
        TX_SOF_N        : out  std_logic;
        TX_EOF_N        : out  std_logic;
        TX_SRC_RDY_N    : out  std_logic;
        TX_DST_RDY_N    : in   std_logic;  
  

        -- System Interface
        USER_CLK        : in  std_logic;   
        RESET           : in  std_logic;
        CHANNEL_UP      : in  std_logic
    ); 
    end component;
 
 
    component aurora_8b10b_v5_2_FRAME_CHECK
    port
    (
        -- User Interface
        RX_D            : in  std_logic_vector(0 to 15); 
        RX_REM          : in  std_logic;     
        RX_SOF_N        : in  std_logic;
        RX_EOF_N        : in  std_logic;
        RX_SRC_RDY_N    : in  std_logic; 


        -- System Interface
        USER_CLK        : in  std_logic;   
        RESET           : in  std_logic;
        CHANNEL_UP      : in  std_logic;
        ERR_COUNT       : out std_logic_vector(0 to 7)
  
    );
    end component;

  -------------------------------------------------------------------
  --  ICON core component declaration
  -------------------------------------------------------------------
  component v6_icon
  
    port
    (
      control0    :   out std_logic_vector(35 downto 0)
    );
  end component;

  -------------------------------------------------------------------
  --  VIO core component declaration
  -------------------------------------------------------------------
  component v6_vio
  
    port
    (
      control     : in    std_logic_vector(35 downto 0);
      clk         : in    std_logic;
      sync_in     : in    std_logic_vector(63 downto 0);
      sync_out    : out   std_logic_vector(15 downto 0)
    );
  end component;
  
  component MGT156_to_156 
	PORT
	(
		areset		: IN STD_LOGIC  := '0';
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
	end component;
  
  component PLL_LA
	PORT
	(
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC 
	);
	end component;
	
	component LA
	PORT
	(
		acq_clk		: IN STD_LOGIC ;
		acq_data_in		: IN STD_LOGIC_VECTOR (77 DOWNTO 0);
		acq_trigger_in		: IN STD_LOGIC_VECTOR (2 DOWNTO 0)
	);
	end component;
	
	signal la_clk : std_logic;
	signal rx_clk : std_logic;
	signal tx_clk : std_logic;
	signal tx_user_clk_i         : std_logic;
	signal rx_user_clk_i         : std_logic;
                                                                           
begin

DIS_TX_CLK <= tx_user_clk_i;
DIS_RX_CLK <= rx_user_clk_i;

-- MGT_LA : LA
--	PORT map
--	(
--		acq_clk		=>GTXQ4_left_i,
--		acq_data_in(15 downto 0) => tx_d_i,
--		acq_trigger_in(0) => user_clk_i,
--		acq_trigger_in(1) => tx_clk,
--		acq_trigger_in(2) => rx_clk
--	);

process(user_clk_i)
	variable status : std_logic;
begin
	if user_clk_i='1' and user_clk_i'event then
		if status = '1' then
			status := '0';
			DIS_USER_CLK <= '0';
		else
			status := '1';
			DIS_USER_CLK <= '1';
		end if;
	end if;
end process;

    lane_up_reduce_i    <=  lane_up_i;

    HARD_ERR  <= not HARD_ERR_Buffer;
    SOFT_ERR  <= not SOFT_ERR_Buffer;
    FRAME_ERR <= not FRAME_ERR_Buffer;
    ERR_COUNT   <= ERR_COUNT_Buffer;
    LANE_UP     <= not LANE_UP_Buffer;
    CHANNEL_UP  <= not CHANNEL_UP_Buffer;
    TXP         <= TXP_Buffer;
    TXN         <= TXN_Buffer;

	LA_PLL : PLL_LA
	PORT map
	(
		inclk0	=>INIT_CLK,
		c0		=>la_clk 
	);

--	MGTPLL : MGT156_to_156 
--	PORT map
--	(
--		areset	=> not tx_lock_i,
--		inclk0	=> tx_user_clk_i,
--		c0		=> user_clk_i,
--		locked	=> pll_not_locked_i 
--	);
pll_not_locked_i <= not tx_lock_i;
	
	
    -- ___________________________Clock Buffers________________________
--      IBUFDS_i :  IBUFDS_GTXE1
--      port map (
--           I     => GTXQ4_P,
--           IB    => GTXQ4_N,
--           CEB   => '0',
--           O     => GTXQ4_left_i,
--           ODIV2 => OPEN);

    -- Instantiate a clock module for clock division

--    clock_module_i : aurora_8b10b_v5_2_CLOCK_MODULE
--        port map (
--
--                    GT_CLK              => tx_out_clk_i,
--                    GT_CLK_LOCKED       => tx_lock_i,
--                    USER_CLK            => user_clk_i,
--                    SYNC_CLK            => sync_clk_i,
--                    PLL_NOT_LOCKED      => pll_not_locked_i
--                 );

    -- Register User I/O --

    -- Register User Outputs from core.

    process (user_clk_i)

    begin

        if (user_clk_i 'event and user_clk_i = '1') then

            HARD_ERR_Buffer  <= hard_err_i;
            SOFT_ERR_Buffer  <= soft_err_i;
            FRAME_ERR_Buffer <= frame_err_i;
            ERR_COUNT_Buffer <= err_count_i;
            LANE_UP_Buffer     <= lane_up_i;
            CHANNEL_UP_Buffer  <= channel_up_i;

        end if;

    end process;

    -- System Interface

    power_down_i     <= '0';
    loopback_i       <= "000";


    -- _______________________________ Module Instantiations ________________________--

    --Connect a frame checker to the user interface
    frame_check_i : aurora_8b10b_v5_2_FRAME_CHECK
    port map
    (
        -- User Interface
        RX_D            =>  rx_d_i, 
        RX_REM          =>  rx_rem_i,
        RX_SOF_N        =>  rx_sof_n_i,
        RX_EOF_N        =>  rx_eof_n_i,
        RX_SRC_RDY_N    =>  rx_src_rdy_n_i,  

        -- System Interface
        USER_CLK        =>  user_clk_i,   
        RESET           =>  reset_i,
        CHANNEL_UP      =>  channel_up_i,
        ERR_COUNT       =>  err_count_i
  
    );


    --Connect a frame generator to the user interface
    frame_gen_i : aurora_8b10b_v5_2_FRAME_GEN
    port map
    (
        -- User Interface
        TX_D            =>  tx_d_i,
            TX_REM          =>  tx_rem_i,
        TX_SOF_N        =>  tx_sof_n_i,
        TX_EOF_N        =>  tx_eof_n_i,
            TX_SRC_RDY_N    =>  tx_src_rdy_n_i,
        TX_DST_RDY_N    =>  tx_dst_rdy_n_i,    


        -- System Interface
        USER_CLK        =>  user_clk_i,
        RESET           =>  reset_i,
        CHANNEL_UP      =>  channel_up_i
    ); 




    -- Module Instantiations --

    aurora_module_i : aurora_8b10b_v5_2
        generic map(
                    SIM_GTXRESET_SPEEDUP => SIM_GTXRESET_SPEEDUP
                   )
        port map   (
                 rxclk => rx_user_clk_i,
				 txclk => user_clk_i,
				GXB_DOWN => not GXB_DOWN,
        -- LocalLink TX Interface

                    TX_D             => tx_d_i,
                    TX_REM           => tx_rem_i,
                    TX_SRC_RDY_N     => tx_src_rdy_n_i,
                    TX_SOF_N         => tx_sof_n_i,
                    TX_EOF_N         => tx_eof_n_i,
                    TX_DST_RDY_N     => tx_dst_rdy_n_i,

        -- LocalLink RX Interface

                    RX_D             => rx_d_i,
                    RX_REM           => rx_rem_i,
                    RX_SRC_RDY_N     => rx_src_rdy_n_i,
                    RX_SOF_N         => rx_sof_n_i,
                    RX_EOF_N         => rx_eof_n_i,

        -- V5 Serial I/O

                    RXP              => RXP,
                    RXN              => RXN,
                    TXP              => TXP_Buffer,
                    TXN              => TXN_Buffer,

        -- V5 Reference Clock Interface
                   GTXQ4    => GTXQ4,

        -- Error Detection Interface

                    HARD_ERR       => hard_err_i,
                    SOFT_ERR       => soft_err_i,
                    FRAME_ERR      => frame_err_i,

        -- Status

                    CHANNEL_UP       => channel_up_i,
                    LANE_UP          => lane_up_i,

        -- Clock Compensation Control Interface

                    WARN_CC          => warn_cc_i,
                    DO_CC            => do_cc_i,

        -- System Interface
					INIT_CLK		 => INIT_CLK,
                    USER_CLK         => user_clk_i,
                    SYNC_CLK         => sync_clk_i,
                    RESET            => reset_i,
                    POWER_DOWN       => power_down_i,
                    LOOPBACK         => loopback_i,
                    GT_RESET         => gt_reset_i,
                    TX_OUT_CLK       => tx_out_clk_i,
                    TX_LOCK          => tx_lock_i
                 );

    standard_cc_module_i : aurora_8b10b_v5_2_STANDARD_CC_MODULE

        port map (

        -- Clock Compensation Control Interface

                    WARN_CC        => warn_cc_i,
                    DO_CC          => do_cc_i,

        -- System Interface

                    PLL_NOT_LOCKED => pll_not_locked_i,
                    USER_CLK       => user_clk_i,
                    RESET          => lane_up_reduce_i

                 );

    reset_logic_i : aurora_8b10b_v5_2_RESET_LOGIC
        port map (
                    RESET            =>	not RESET,
                    USER_CLK         => user_clk_i,
                    INIT_CLK       => INIT_CLK,
                    GT_RESET_IN      => not GT_RESET_IN,
                    TX_LOCK_IN       => tx_lock_i,
                    PLL_NOT_LOCKED   => pll_not_locked_i,

                    SYSTEM_RESET     => reset_i,
                    GT_RESET_OUT     => gt_reset_i
                 );


end MAPPED;
