Analysis & Synthesis report for aurora_8b10b_v5_2_example_design
Fri Sep 16 11:25:40 2011
Quartus II 64-Bit Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. Registers Removed During Synthesis
 11. Removed Registers Triggering Further Register Optimizations
 12. General Register Statistics
 13. Inverted Register Statistics
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_6p14:auto_generated
 16. Parameter Settings for User Entity Instance: Top-level Entity: |aurora_8b10b_v5_2_example_design
 17. Parameter Settings for User Entity Instance: PLL_LA:LA_PLL|altpll:altpll_component
 18. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i
 19. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|FDR:lane_up_flop_i
 20. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0
 21. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|FD:reset_lanes_flop_i
 22. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_last_flop_i
 23. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_taps_i
 24. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component
 25. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component
 26. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component
 27. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component
 28. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_0_i
 29. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_1_i
 30. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_a_flop_0_i
 31. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_0_i
 32. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_1_i
 33. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_0_i
 34. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_1_i
 35. Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i|FDR:gen_cc_flop_0_i
 36. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 37. Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub
 38. altpll Parameter Settings by Entity Instance
 39. lpm_shiftreg Parameter Settings by Entity Instance
 40. Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i"
 41. Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i"
 42. Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i"
 43. Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0"
 44. Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i"
 45. Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i"
 46. Port Connectivity Checks: "PLL_LA:LA_PLL"
 47. SignalTap II Logic Analyzer Settings
 48. Elapsed Time Per Partition
 49. Connections to In-System Debugging Instance "auto_signaltap_0"
 50. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+-----------------------------------+------------------------------------------------+
; Analysis & Synthesis Status       ; Successful - Fri Sep 16 11:25:39 2011          ;
; Quartus II 64-Bit Version         ; 10.1 Build 197 01/19/2011 SP 1 SJ Full Version ;
; Revision Name                     ; aurora_8b10b_v5_2_example_design               ;
; Top-level Entity Name             ; aurora_8b10b_v5_2_example_design               ;
; Family                            ; Stratix IV                                     ;
; Logic utilization                 ; N/A                                            ;
;     Combinational ALUTs           ; 569                                            ;
;     Memory ALUTs                  ; 0                                              ;
;     Dedicated logic registers     ; 1,280                                          ;
; Total registers                   ; 1280                                           ;
; Total pins                        ; 25                                             ;
; Total virtual pins                ; 0                                              ;
; Total block memory bits           ; 79,872                                         ;
; DSP block 18-bit elements         ; 0                                              ;
; Total GXB Receiver Channel PCS    ; 1                                              ;
; Total GXB Receiver Channel PMA    ; 1                                              ;
; Total GXB Transmitter Channel PCS ; 1                                              ;
; Total GXB Transmitter Channel PMA ; 1                                              ;
; Total PLLs                        ; 0                                              ;
; Total DLLs                        ; 0                                              ;
+-----------------------------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                                                    ;
+----------------------------------------------------------------------------+----------------------------------+----------------------------------+
; Option                                                                     ; Setting                          ; Default Value                    ;
+----------------------------------------------------------------------------+----------------------------------+----------------------------------+
; Device                                                                     ; EP4SGX230KF40C2                  ;                                  ;
; Top-level entity name                                                      ; aurora_8b10b_v5_2_example_design ; aurora_8b10b_v5_2_example_design ;
; Family name                                                                ; Stratix IV                       ; Cyclone IV GX                    ;
; Use smart compilation                                                      ; Off                              ; Off                              ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                               ; On                               ;
; Enable compact report table                                                ; Off                              ; Off                              ;
; Restructure Multiplexers                                                   ; Auto                             ; Auto                             ;
; Create Debugging Nodes for IP Cores                                        ; Off                              ; Off                              ;
; Preserve fewer node names                                                  ; On                               ; On                               ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                              ; Off                              ;
; Verilog Version                                                            ; Verilog_2001                     ; Verilog_2001                     ;
; VHDL Version                                                               ; VHDL_1993                        ; VHDL_1993                        ;
; State Machine Processing                                                   ; Auto                             ; Auto                             ;
; Safe State Machine                                                         ; Off                              ; Off                              ;
; Extract Verilog State Machines                                             ; On                               ; On                               ;
; Extract VHDL State Machines                                                ; On                               ; On                               ;
; Ignore Verilog initial constructs                                          ; Off                              ; Off                              ;
; Iteration limit for constant Verilog loops                                 ; 5000                             ; 5000                             ;
; Iteration limit for non-constant Verilog loops                             ; 250                              ; 250                              ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                               ; On                               ;
; Parallel Synthesis                                                         ; On                               ; On                               ;
; DSP Block Balancing                                                        ; Auto                             ; Auto                             ;
; NOT Gate Push-Back                                                         ; On                               ; On                               ;
; Power-Up Don't Care                                                        ; On                               ; On                               ;
; Remove Redundant Logic Cells                                               ; Off                              ; Off                              ;
; Remove Duplicate Registers                                                 ; On                               ; On                               ;
; Ignore CARRY Buffers                                                       ; Off                              ; Off                              ;
; Ignore CASCADE Buffers                                                     ; Off                              ; Off                              ;
; Ignore GLOBAL Buffers                                                      ; Off                              ; Off                              ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                              ; Off                              ;
; Ignore LCELL Buffers                                                       ; Off                              ; Off                              ;
; Ignore SOFT Buffers                                                        ; On                               ; On                               ;
; Limit AHDL Integers to 32 Bits                                             ; Off                              ; Off                              ;
; Optimization Technique                                                     ; Balanced                         ; Balanced                         ;
; Carry Chain Length                                                         ; 70                               ; 70                               ;
; Auto Carry Chains                                                          ; On                               ; On                               ;
; Auto Open-Drain Pins                                                       ; On                               ; On                               ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                              ; Off                              ;
; Auto ROM Replacement                                                       ; On                               ; On                               ;
; Auto RAM Replacement                                                       ; On                               ; On                               ;
; Auto DSP Block Replacement                                                 ; On                               ; On                               ;
; Auto Shift Register Replacement                                            ; Auto                             ; Auto                             ;
; Auto Clock Enable Replacement                                              ; On                               ; On                               ;
; Strict RAM Replacement                                                     ; Off                              ; Off                              ;
; Allow Synchronous Control Signals                                          ; On                               ; On                               ;
; Force Use of Synchronous Clear Signals                                     ; Off                              ; Off                              ;
; Auto RAM Block Balancing                                                   ; On                               ; On                               ;
; Auto RAM to Logic Cell Conversion                                          ; Off                              ; Off                              ;
; Auto Resource Sharing                                                      ; Off                              ; Off                              ;
; Allow Any RAM Size For Recognition                                         ; Off                              ; Off                              ;
; Allow Any ROM Size For Recognition                                         ; Off                              ; Off                              ;
; Allow Any Shift Register Size For Recognition                              ; Off                              ; Off                              ;
; Use LogicLock Constraints during Resource Balancing                        ; On                               ; On                               ;
; Ignore translate_off and synthesis_off directives                          ; Off                              ; Off                              ;
; Timing-Driven Synthesis                                                    ; On                               ; On                               ;
; Report Parameter Settings                                                  ; On                               ; On                               ;
; Report Source Assignments                                                  ; On                               ; On                               ;
; Report Connectivity Checks                                                 ; On                               ; On                               ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                              ; Off                              ;
; Synchronization Register Chain Length                                      ; 2                                ; 2                                ;
; PowerPlay Power Optimization                                               ; Normal compilation               ; Normal compilation               ;
; HDL message level                                                          ; Level2                           ; Level2                           ;
; Suppress Register Optimization Related Messages                            ; Off                              ; Off                              ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000                             ; 5000                             ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                              ; 100                              ;
; Clock MUX Protection                                                       ; On                               ; On                               ;
; Auto Gated Clock Conversion                                                ; Off                              ; Off                              ;
; Block Design Naming                                                        ; Auto                             ; Auto                             ;
; SDC constraint protection                                                  ; Off                              ; Off                              ;
; Synthesis Effort                                                           ; Auto                             ; Auto                             ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                               ; On                               ;
; Analysis & Synthesis Message Level                                         ; Medium                           ; Medium                           ;
; Disable Register Merging Across Hierarchies                                ; Auto                             ; Auto                             ;
; Resource Aware Inference For Block RAM                                     ; On                               ; On                               ;
; Synthesis Seed                                                             ; 1                                ; 1                                ;
+----------------------------------------------------------------------------+----------------------------------+----------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ; < 0.1%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path                                                     ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                                                                   ;
+--------------------------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------+
; SRL16.vhd                                                                            ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/SRL16.vhd                                                                            ;
; MUX16to1.vhd                                                                         ; yes             ; User Wizard-Generated File   ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/MUX16to1.vhd                                                                         ;
; LPMSHIFTREG16.vhd                                                                    ; yes             ; User Wizard-Generated File   ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/LPMSHIFTREG16.vhd                                                                    ;
; FDR.vhd                                                                              ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/FDR.vhd                                                                              ;
; FD.vhd                                                                               ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/FD.vhd                                                                               ;
; aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd ;
; aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd   ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd   ;
; aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd ;
; aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd                               ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd                               ;
; aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd                ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd                ;
; aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd                   ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd                   ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd                              ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd                              ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd                               ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd                               ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd                       ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd                       ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd                          ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd                          ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd                         ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd                         ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd                               ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd                               ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd                             ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd                             ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd                         ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd                         ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd                             ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd                             ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd                                    ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd                                    ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd                       ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd                       ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd                                  ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd                                  ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd                                  ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd                                  ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd                                    ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd                                    ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd                            ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd                            ;
; aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd                           ; yes             ; User VHDL File               ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd                           ;
; PLL_LA.vhd                                                                           ; yes             ; User Wizard-Generated File   ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/PLL_LA.vhd                                                                           ;
; MGT.vhd                                                                              ; yes             ; User Wizard-Generated File   ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/MGT.vhd                                                                              ;
; altpll.tdf                                                                           ; yes             ; Megafunction                 ; c:/altera/10.1/quartus/libraries/megafunctions/altpll.tdf                                                                      ;
; db/pll_la_altpll.v                                                                   ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/pll_la_altpll.v                                                                   ;
; lpm_shiftreg.tdf                                                                     ; yes             ; Megafunction                 ; c:/altera/10.1/quartus/libraries/megafunctions/lpm_shiftreg.tdf                                                                ;
; lpm_mux.tdf                                                                          ; yes             ; Megafunction                 ; c:/altera/10.1/quartus/libraries/megafunctions/lpm_mux.tdf                                                                     ;
; db/mux_76e.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/mux_76e.tdf                                                                       ;
; sld_signaltap.vhd                                                                    ; yes             ; Encrypted Megafunction       ; c:/altera/10.1/quartus/libraries/megafunctions/sld_signaltap.vhd                                                               ;
; sld_ela_control.vhd                                                                  ; yes             ; Encrypted Megafunction       ; c:/altera/10.1/quartus/libraries/megafunctions/sld_ela_control.vhd                                                             ;
; sld_mbpmg.vhd                                                                        ; yes             ; Encrypted Megafunction       ; c:/altera/10.1/quartus/libraries/megafunctions/sld_mbpmg.vhd                                                                   ;
; sld_ela_trigger_flow_mgr.vhd                                                         ; yes             ; Encrypted Megafunction       ; c:/altera/10.1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd                                                    ;
; sld_buffer_manager.vhd                                                               ; yes             ; Encrypted Megafunction       ; c:/altera/10.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd                                                          ;
; altsyncram.tdf                                                                       ; yes             ; Megafunction                 ; c:/altera/10.1/quartus/libraries/megafunctions/altsyncram.tdf                                                                  ;
; db/altsyncram_6p14.tdf                                                               ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/altsyncram_6p14.tdf                                                               ;
; altdpram.tdf                                                                         ; yes             ; Megafunction                 ; c:/altera/10.1/quartus/libraries/megafunctions/altdpram.tdf                                                                    ;
; db/mux_opc.tdf                                                                       ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/mux_opc.tdf                                                                       ;
; lpm_decode.tdf                                                                       ; yes             ; Megafunction                 ; c:/altera/10.1/quartus/libraries/megafunctions/lpm_decode.tdf                                                                  ;
; db/decode_asf.tdf                                                                    ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/decode_asf.tdf                                                                    ;
; lpm_counter.tdf                                                                      ; yes             ; Megafunction                 ; c:/altera/10.1/quartus/libraries/megafunctions/lpm_counter.tdf                                                                 ;
; db/cntr_sdi.tdf                                                                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cntr_sdi.tdf                                                                      ;
; db/cmpr_pdc.tdf                                                                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cmpr_pdc.tdf                                                                      ;
; db/cntr_d6j.tdf                                                                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cntr_d6j.tdf                                                                      ;
; db/cntr_bdi.tdf                                                                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cntr_bdi.tdf                                                                      ;
; db/cmpr_odc.tdf                                                                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cmpr_odc.tdf                                                                      ;
; db/cntr_vvi.tdf                                                                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cntr_vvi.tdf                                                                      ;
; db/cmpr_kdc.tdf                                                                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cmpr_kdc.tdf                                                                      ;
; sld_rom_sr.vhd                                                                       ; yes             ; Encrypted Megafunction       ; c:/altera/10.1/quartus/libraries/megafunctions/sld_rom_sr.vhd                                                                  ;
; sld_hub.vhd                                                                          ; yes             ; Encrypted Megafunction       ; c:/altera/10.1/quartus/libraries/megafunctions/sld_hub.vhd                                                                     ;
; ../../ReplaceXilinxComponent/FD_Alan.vhd                                             ; yes             ; User VHDL File               ; ../../ReplaceXilinxComponent/FD_Alan.vhd                                                                                       ;
; ../../ReplaceXilinxComponent/FDR_Alan.vhd                                            ; yes             ; User VHDL File               ; ../../ReplaceXilinxComponent/FDR_Alan.vhd                                                                                      ;
; ../../ReplaceXilinxComponent/LPMSHIFTREG16.vhd                                       ; yes             ; User Wizard-Generated File   ; ../../ReplaceXilinxComponent/LPMSHIFTREG16.vhd                                                                                 ;
; ../../ReplaceXilinxComponent/MUX16to1.vhd                                            ; yes             ; User Wizard-Generated File   ; ../../ReplaceXilinxComponent/MUX16to1.vhd                                                                                      ;
; ../../ReplaceXilinxComponent/SRL16_Alan.vhd                                          ; yes             ; User VHDL File               ; ../../ReplaceXilinxComponent/SRL16_Alan.vhd                                                                                    ;
; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/altsyncram_3p14.tdf                     ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/altsyncram_3p14.tdf                                                               ;
; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cntr_kdi.tdf                            ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cntr_kdi.tdf                                                                      ;
; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cmpr_qdc.tdf                            ; yes             ; Auto-Generated Megafunction  ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/db/cmpr_qdc.tdf                                                                      ;
; ../ReplaceXilinxComponent/SRL16.vhd                                                  ; yes             ; User VHDL File               ; ../ReplaceXilinxComponent/SRL16.vhd                                                                                            ;
; ../ReplaceXilinxComponent/MUX16to1.vhd                                               ; yes             ; User Wizard-Generated File   ; ../ReplaceXilinxComponent/MUX16to1.vhd                                                                                         ;
; ../ReplaceXilinxComponent/LPMSHIFTREG16.vhd                                          ; yes             ; User Wizard-Generated File   ; ../ReplaceXilinxComponent/LPMSHIFTREG16.vhd                                                                                    ;
; ../ReplaceXilinxComponent/FDR.vhd                                                    ; yes             ; User VHDL File               ; ../ReplaceXilinxComponent/FDR.vhd                                                                                              ;
; ../ReplaceXilinxComponent/FD.vhd                                                     ; yes             ; User VHDL File               ; ../ReplaceXilinxComponent/FD.vhd                                                                                               ;
+--------------------------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                      ;
+-----------------------------------------------+----------------------------------------------------------------------------------+
; Resource                                      ; Usage                                                                            ;
+-----------------------------------------------+----------------------------------------------------------------------------------+
; Estimated ALUTs Used                          ; 569                                                                              ;
;     -- Combinational ALUTs                    ; 569                                                                              ;
;     -- Memory ALUTs                           ; 0                                                                                ;
;     -- LUT_REGs                               ; 0                                                                                ;
; Dedicated logic registers                     ; 1280                                                                             ;
;                                               ;                                                                                  ;
; Estimated ALUTs Unavailable                   ; 8                                                                                ;
;     -- Due to unpartnered combinational logic ; 8                                                                                ;
;     -- Due to Memory ALUTs                    ; 0                                                                                ;
;                                               ;                                                                                  ;
; Total combinational functions                 ; 569                                                                              ;
; Combinational ALUT usage by number of inputs  ;                                                                                  ;
;     -- 7 input functions                      ; 8                                                                                ;
;     -- 6 input functions                      ; 38                                                                               ;
;     -- 5 input functions                      ; 74                                                                               ;
;     -- 4 input functions                      ; 131                                                                              ;
;     -- <=3 input functions                    ; 318                                                                              ;
;                                               ;                                                                                  ;
; Combinational ALUTs by mode                   ;                                                                                  ;
;     -- normal mode                            ; 439                                                                              ;
;     -- extended LUT mode                      ; 8                                                                                ;
;     -- arithmetic mode                        ; 122                                                                              ;
;     -- shared arithmetic mode                 ; 0                                                                                ;
;                                               ;                                                                                  ;
; Estimated ALUT/register pairs used            ; 1386                                                                             ;
;                                               ;                                                                                  ;
; Total registers                               ; 1280                                                                             ;
;     -- Dedicated logic registers              ; 1280                                                                             ;
;     -- I/O registers                          ; 0                                                                                ;
;     -- LUT_REGs                               ; 0                                                                                ;
;                                               ;                                                                                  ;
; Estimated ALMs:  partially or completely used ; 693                                                                              ;
;                                               ;                                                                                  ;
; I/O pins                                      ; 25                                                                               ;
; Total MLAB memory bits                        ; 0                                                                                ;
; Total block memory bits                       ; 79872                                                                            ;
; Total PLLs                                    ; 2                                                                                ;
;     -- GXB PLLs                               ; 2                                                                                ;
;                                               ;                                                                                  ;
; Maximum fan-out node                          ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_transmit_pma0_datain[0] ;
; Maximum fan-out                               ; 1059                                                                             ;
; Total fan-out                                 ; 6798                                                                             ;
; Average fan-out                               ; 3.47                                                                             ;
+-----------------------------------------------+----------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                           ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 12x12 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                                                                            ; Library Name ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |aurora_8b10b_v5_2_example_design                                                                    ; 569 (4)           ; 1280 (15)    ; 79872             ; 0            ; 0       ; 0         ; 0         ; 0         ; 25   ; 0            ; |aurora_8b10b_v5_2_example_design                                                                                                                                                                                                                                                                                              ;              ;
;    |aurora_8b10b_v5_2:aurora_module_i|                                                               ; 193 (0)           ; 463 (0)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i                                                                                                                                                                                                                                                            ;              ;
;       |MGT_alt4gxb:MGT_0|                                                                            ; 0 (0)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0                                                                                                                                                                                                                                          ;              ;
;       |aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|                                                ; 132 (0)           ; 225 (0)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i                                                                                                                                                                                                              ;              ;
;          |aurora_8b10b_v5_2_ERR_DETECT:err_detect_i|                                                 ; 14 (14)           ; 11 (11)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i                                                                                                                                                                    ;              ;
;          |aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|                                             ; 36 (35)           ; 75 (74)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i                                                                                                                                                                ;              ;
;             |FDR:lane_up_flop_i|                                                                     ; 1 (1)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|FDR:lane_up_flop_i                                                                                                                                             ;              ;
;          |aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|                                                       ; 44 (44)           ; 89 (89)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i                                                                                                                                                                          ;              ;
;          |aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|                                                       ; 38 (38)           ; 50 (50)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i                                                                                                                                                                          ;              ;
;       |aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|                                                ; 37 (0)            ; 131 (0)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i                                                                                                                                                                                                              ;              ;
;          |aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i|                                 ; 2 (2)             ; 5 (5)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i                                                                                                                                                    ;              ;
;          |aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|                                       ; 21 (21)           ; 76 (75)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i                                                                                                                                                          ;              ;
;             |FD:reset_lanes_flop_i|                                                                  ; 0 (0)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|FD:reset_lanes_flop_i                                                                                                                                    ;              ;
;          |aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|                                     ; 14 (11)           ; 50 (10)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i                                                                                                                                                        ;              ;
;             |FD:gen_a_flop_0_i|                                                                      ; 0 (0)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_a_flop_0_i                                                                                                                                      ;              ;
;             |FD:gen_k_flop_0_i|                                                                      ; 0 (0)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_0_i                                                                                                                                      ;              ;
;             |FD:gen_k_flop_1_i|                                                                      ; 0 (0)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_1_i                                                                                                                                      ;              ;
;             |FD:gen_r_flop_0_i|                                                                      ; 0 (0)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_0_i                                                                                                                                      ;              ;
;             |FD:gen_r_flop_1_i|                                                                      ; 1 (1)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_1_i                                                                                                                                      ;              ;
;             |FD:gen_v_flop_0_i|                                                                      ; 0 (0)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_0_i                                                                                                                                      ;              ;
;             |FD:gen_v_flop_1_i|                                                                      ; 0 (0)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_1_i                                                                                                                                      ;              ;
;             |FDR:lfsr_last_flop_i|                                                                   ; 1 (1)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_last_flop_i                                                                                                                                   ;              ;
;             |FDR:lfsr_taps_i|                                                                        ; 1 (1)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_taps_i                                                                                                                                        ;              ;
;             |SRL16:ver_counter_0_i|                                                                  ; 0 (0)             ; 16 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i                                                                                                                                  ;              ;
;                |LPMSHIFTREG16:lpm_shiftreg16|                                                        ; 0 (0)             ; 16 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16                                                                                                     ;              ;
;                   |lpm_shiftreg:lpm_shiftreg_component|                                              ; 0 (0)             ; 16 (16)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component                                                                 ;              ;
;             |SRL16:ver_counter_1_i|                                                                  ; 0 (0)             ; 15 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i                                                                                                                                  ;              ;
;                |LPMSHIFTREG16:lpm_shiftreg16|                                                        ; 0 (0)             ; 15 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16                                                                                                     ;              ;
;                   |lpm_shiftreg:lpm_shiftreg_component|                                              ; 0 (0)             ; 15 (15)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component                                                                 ;              ;
;       |aurora_8b10b_v5_2_RX_LL:rx_ll_i|                                                              ; 9 (0)             ; 41 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_RX_LL:rx_ll_i                                                                                                                                                                                                                            ;              ;
;          |aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i|                                 ; 9 (9)             ; 41 (41)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_RX_LL:rx_ll_i|aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i                                                                                                                                                                  ;              ;
;       |aurora_8b10b_v5_2_TX_LL:tx_ll_i|                                                              ; 15 (0)            ; 66 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i                                                                                                                                                                                                                            ;              ;
;          |aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i|                                           ; 12 (10)           ; 14 (13)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i                                                                                                                                                                            ;              ;
;             |FDR:gen_cc_flop_0_i|                                                                    ; 2 (2)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i|FDR:gen_cc_flop_0_i                                                                                                                                                        ;              ;
;          |aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i|                                         ; 3 (3)             ; 52 (52)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i                                                                                                                                                                          ;              ;
;    |aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|                                                     ; 54 (54)           ; 58 (58)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i                                                                                                                                                                                                                                                  ;              ;
;    |aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i|                                                         ; 67 (67)           ; 60 (60)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i                                                                                                                                                                                                                                                      ;              ;
;    |aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i|                                                     ; 5 (5)             ; 11 (11)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i                                                                                                                                                                                                                                                  ;              ;
;    |aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i|                                       ; 9 (9)             ; 71 (71)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i                                                                                                                                                                                                                                    ;              ;
;    |sld_hub:auto_hub|                                                                                ; 67 (34)           ; 73 (45)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_hub:auto_hub                                                                                                                                                                                                                                                                             ;              ;
;       |sld_rom_sr:hub_info_reg|                                                                      ; 16 (16)           ; 9 (9)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_hub:auto_hub|sld_rom_sr:hub_info_reg                                                                                                                                                                                                                                                     ;              ;
;       |sld_shadow_jsm:shadow_jsm|                                                                    ; 17 (17)           ; 19 (19)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_hub:auto_hub|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                                                                                   ;              ;
;    |sld_signaltap:auto_signaltap_0|                                                                  ; 170 (1)           ; 529 (0)      ; 79872             ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                               ;              ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                        ; 169 (16)          ; 529 (230)    ; 79872             ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                         ;              ;
;          |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|                            ; 2 (0)             ; 70 (70)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem                                                                                                                                                          ;              ;
;             |lpm_decode:wdecoder|                                                                    ; 2 (0)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                      ;              ;
;                |decode_asf:auto_generated|                                                           ; 2 (2)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_asf:auto_generated                                                                                                            ;              ;
;          |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                           ; 0 (0)             ; 0 (0)        ; 79872             ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                         ;              ;
;             |altsyncram_6p14:auto_generated|                                                         ; 0 (0)             ; 0 (0)        ; 79872             ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_6p14:auto_generated                                                                                                                                          ;              ;
;          |lpm_shiftreg:segment_offset_config_deserialize|                                            ; 0 (0)             ; 11 (11)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize                                                                                                                                                                          ;              ;
;          |lpm_shiftreg:status_register|                                                              ; 17 (17)           ; 17 (17)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:status_register                                                                                                                                                                                            ;              ;
;          |sld_buffer_manager:sld_buffer_manager_inst|                                                ; 79 (79)           ; 64 (64)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst                                                                                                                                                                              ;              ;
;          |sld_ela_control:ela_control|                                                               ; 3 (1)             ; 21 (1)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control                                                                                                                                                                                             ;              ;
;             |lpm_shiftreg:trigger_config_deserialize|                                                ; 0 (0)             ; 4 (4)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                     ;              ;
;             |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 1 (0)             ; 5 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                      ;              ;
;                |lpm_shiftreg:trigger_condition_deserialize|                                          ; 0 (0)             ; 3 (3)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                           ;              ;
;                |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                      ; 1 (0)             ; 2 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                       ;              ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                            ; 1 (1)             ; 2 (2)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ;              ;
;             |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|                          ; 1 (1)             ; 11 (1)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity                                                                                                                               ;              ;
;                |lpm_shiftreg:trigger_config_deserialize|                                             ; 0 (0)             ; 10 (10)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize                                                                                       ;              ;
;          |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|          ; 41 (10)           ; 108 (0)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                        ;              ;
;             |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                              ; 8 (0)             ; 6 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                              ;              ;
;                |cntr_sdi:auto_generated|                                                             ; 8 (8)             ; 6 (6)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_sdi:auto_generated                                                      ;              ;
;             |lpm_counter:read_pointer_counter|                                                       ; 11 (0)            ; 11 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                       ;              ;
;                |cntr_d6j:auto_generated|                                                             ; 11 (11)           ; 11 (11)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d6j:auto_generated                                                                               ;              ;
;             |lpm_counter:status_advance_pointer_counter|                                             ; 7 (0)             ; 5 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter                                                                                             ;              ;
;                |cntr_bdi:auto_generated|                                                             ; 7 (7)             ; 5 (5)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_bdi:auto_generated                                                                     ;              ;
;             |lpm_counter:status_read_pointer_counter|                                                ; 3 (0)             ; 1 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter                                                                                                ;              ;
;                |cntr_vvi:auto_generated|                                                             ; 3 (3)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_vvi:auto_generated                                                                        ;              ;
;             |lpm_shiftreg:info_data_shift_out|                                                       ; 0 (0)             ; 23 (23)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                       ;              ;
;             |lpm_shiftreg:ram_data_shift_out|                                                        ; 1 (1)             ; 39 (39)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                        ;              ;
;             |lpm_shiftreg:status_data_shift_out|                                                     ; 1 (1)             ; 23 (23)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out                                                                                                     ;              ;
;          |sld_rom_sr:crc_rom_sr|                                                                     ; 11 (11)           ; 8 (8)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |aurora_8b10b_v5_2_example_design|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                   ;              ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                         ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Name                                                                                                                                                           ; Type      ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+--------------+--------------+--------------+--------------+-------+------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_6p14:auto_generated|ALTSYNCRAM ; M9K block ; Simple Dual Port ; 2048         ; 39           ; 2048         ; 39           ; 79872 ; None ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------------+--------------+--------------+--------------+--------------+-------+------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                                                                                                    ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                                                                                                            ; IP Include File                                             ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------+
; Altera ; ALTPLL       ; 10.1    ; N/A          ; N/A          ; |aurora_8b10b_v5_2_example_design|PLL_LA:LA_PLL                                                                                                                                                                            ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/PLL_LA.vhd        ;
; Altera ; ALTGX        ; 10.1    ; N/A          ; N/A          ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0                                                                                                                                      ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/MGT.vhd           ;
; Altera ; LPM_SHIFTREG ; N/A     ; N/A          ; N/A          ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16 ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/LPMSHIFTREG16.vhd ;
; Altera ; LPM_MUX      ; N/A     ; N/A          ; N/A          ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1           ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/MUX16to1.vhd      ;
; Altera ; LPM_MUX      ; N/A     ; N/A          ; N/A          ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1           ; C:/Users/Alan/Desktop/V6aurora_3125M_156M/MUX16to1.vhd      ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                           ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                                         ; Reason for Removal                                                                                                                                   ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i|storage_pad_r                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                               ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i|gen_pad_r                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                               ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component|dffs[15] ; Lost fanout                                                                                                                                          ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i|GEN_PAD_Buffer                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                               ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|gen_pad_r                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                               ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|odd_word_r                                                                                              ; Merged with status                                                                                                                                   ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i|lane_up_r                                                                                   ; Merged with aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i|reset_r                                                                        ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_spa_d_r[3]                                                                                              ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_pad_d_r[1]        ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_spa_d_r[3]                                                                                                     ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_pad_d_r[1]        ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_sp_d_r[3]                                                                                                      ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_sp_d_r[3]  ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_sp_d_r[1]                                                                                               ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_scp_d_r[1]        ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_spa_d_r[1]                                                                                              ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_scp_d_r[1]        ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_spa_d_r[1]                                                                                                     ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_scp_d_r[1]        ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[1]                                                                                                ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_scp_d_r[1]        ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_ecp_d_r[2]                                                                                                     ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_scp_d_r[2]        ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_spa_d_r[0]                                                                                              ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_sp_d_r[0]  ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[0]                                                                                                ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_sp_d_r[0]  ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_sp_d_r[2]                                                                                                      ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_sp_d_r[2]  ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_spa_d_r[2]                                                                                                     ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_spa_d_r[2] ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[3]                                                                                                       ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[3]   ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[2]                                                                                                       ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[2]   ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|counter2_r[0]                                                                                           ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|gen_spa_data_r[1]    ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|ENABLE_ERR_DETECT_Buffer                                                                                ; Merged with aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|gen_sp_data_r[1]     ;
; aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|data_lfsr_r[8]                                                                                                                                                                            ; Merged with aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|pdu_cmp_data_r[7]                                                                            ;
; aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|data_lfsr_r[1]                                                                                                                                                                            ; Merged with aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|pdu_cmp_data_r[0]                                                                            ;
; Total Number of Removed Registers = 25                                                                                                                                                                                                ;                                                                                                                                                      ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                    ;
+------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                      ; Reason for Removal        ; Registers Removed due to This Register                                                                                        ;
+------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------+
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i|storage_pad_r  ; Stuck at GND              ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i|gen_pad_r ;
;                                                                                                                                    ; due to stuck port data_in ;                                                                                                                               ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i|GEN_PAD_Buffer ; Stuck at GND              ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|gen_pad_r ;
;                                                                                                                                    ; due to stuck port data_in ;                                                                                                                               ;
+------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1280  ;
; Number of registers using Synchronous Clear  ; 243   ;
; Number of registers using Synchronous Load   ; 155   ;
; Number of registers using Asynchronous Clear ; 226   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 500   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                 ; Fan out ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; status                                                                                                                                                            ; 7       ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i|CHANNEL_HARD_ERR_Buffer ; 1       ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i|CHANNEL_SOFT_ERR_Buffer ; 1       ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i|RESET_CHANNEL_Buffer    ; 2       ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|counter1_r[7]                       ; 1       ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|downcounter_r[3]            ; 6       ;
; aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i|reset_debounce_r[3]                                                                                                   ; 1       ;
; aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i|reset_debounce_r[2]                                                                                                   ; 2       ;
; aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i|reset_debounce_r[0]                                                                                                   ; 2       ;
; aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i|reset_debounce_r[1]                                                                                                   ; 2       ;
; sld_hub:auto_hub|tdo                                                                                                                                              ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11]                           ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[9]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[10]                           ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3]                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4]                            ; 1       ;
; Total number of inverted registers = 23                                                                                                                           ;         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 9 bits    ; 18 ALUTs      ; 0 ALUTs              ; 18 ALUTs               ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|err_count_tmp[8]                                                                                           ;
; 3:1                ; 10 bits   ; 20 ALUTs      ; 10 ALUTs             ; 10 ALUTs               ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|data_lfsr_r[7]                                                                                             ;
; 3:1                ; 6 bits    ; 12 ALUTs      ; 6 ALUTs              ; 6 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|data_lfsr_r[15]                                                                                            ;
; 3:1                ; 2 bits    ; 4 ALUTs       ; 4 ALUTs              ; 0 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|downcounter_r[2] ;
; 3:1                ; 8 bits    ; 16 ALUTs      ; 8 ALUTs              ; 8 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i|bytes_sent_r[1]                                                                                                ;
; 3:1                ; 15 bits   ; 30 ALUTs      ; 0 ALUTs              ; 30 ALUTs               ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i|count_16d_srl_r[9]                                                                           ;
; 3:1                ; 23 bits   ; 46 ALUTs      ; 0 ALUTs              ; 46 ALUTs               ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i|count_24d_srl_r[16]                                                                          ;
; 3:1                ; 8 bits    ; 16 ALUTs      ; 0 ALUTs              ; 16 ALUTs               ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|RX_D_R[0]                                                                                                  ;
; 3:1                ; 8 bits    ; 16 ALUTs      ; 0 ALUTs              ; 16 ALUTs               ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i|data_eof_1_r                         ;
; 3:1                ; 4 bits    ; 8 ALUTs       ; 4 ALUTs              ; 4 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i|TX_SRC_RDY_N                                                                                                   ;
; 3:1                ; 4 bits    ; 8 ALUTs       ; 4 ALUTs              ; 4 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i|eof_r                                                                                                          ;
; 4:1                ; 5 bits    ; 10 ALUTs      ; 5 ALUTs              ; 5 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|pdu_cmp_data_r[0]                                                                                          ;
; 4:1                ; 3 bits    ; 6 ALUTs       ; 3 ALUTs              ; 3 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|pdu_cmp_data_r[2]                                                                                          ;
; 4:1                ; 16 bits   ; 32 ALUTs      ; 0 ALUTs              ; 32 ALUTs               ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i|tx_data_buf_2[7]                                                                                               ;
; 4:1                ; 8 bits    ; 16 ALUTs      ; 0 ALUTs              ; 16 ALUTs               ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|RX_D_R[13]                                                                                                 ;
; 5:1                ; 5 bits    ; 15 ALUTs      ; 10 ALUTs             ; 5 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|pdu_cmp_data_r[8]                                                                                          ;
; 5:1                ; 3 bits    ; 9 ALUTs       ; 6 ALUTs              ; 3 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i|pdu_cmp_data_r[12]                                                                                         ;
; 8:1                ; 2 bits    ; 10 ALUTs      ; 8 ALUTs              ; 2 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i|good_count_r[0]              ;
; 10:1               ; 4 bits    ; 24 ALUTs      ; 24 ALUTs             ; 0 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|TX_DATA_Buffer[6]                  ;
; 10:1               ; 4 bits    ; 24 ALUTs      ; 24 ALUTs             ; 0 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|TX_DATA_Buffer[0]                  ;
; 12:1               ; 4 bits    ; 32 ALUTs      ; 28 ALUTs             ; 4 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|TX_DATA_Buffer[13]                 ;
; 12:1               ; 4 bits    ; 32 ALUTs      ; 28 ALUTs             ; 4 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i|TX_DATA_Buffer[12]                 ;
; 27:1               ; 2 bits    ; 36 ALUTs      ; 34 ALUTs             ; 2 ALUTs                ; Yes        ; |aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i|count_r[1]                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_6p14:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                           ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                            ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |aurora_8b10b_v5_2_example_design ;
+----------------------+-------+-------------------------------------------------------------------+
; Parameter Name       ; Value ; Type                                                              ;
+----------------------+-------+-------------------------------------------------------------------+
; USE_CHIPSCOPE        ; 0     ; Signed Integer                                                    ;
; SIM_GTXRESET_SPEEDUP ; 1     ; Signed Integer                                                    ;
+----------------------+-------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: PLL_LA:LA_PLL|altpll:altpll_component ;
+-------------------------------+--------------------------+-------------------------+
; Parameter Name                ; Value                    ; Type                    ;
+-------------------------------+--------------------------+-------------------------+
; OPERATION_MODE                ; NORMAL                   ; Untyped                 ;
; PLL_TYPE                      ; AUTO                     ; Untyped                 ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=PLL_LA ; Untyped                 ;
; QUALIFY_CONF_DONE             ; OFF                      ; Untyped                 ;
; COMPENSATE_CLOCK              ; CLK0                     ; Untyped                 ;
; SCAN_CHAIN                    ; LONG                     ; Untyped                 ;
; PRIMARY_CLOCK                 ; INCLK0                   ; Untyped                 ;
; INCLK0_INPUT_FREQUENCY        ; 6400                     ; Signed Integer          ;
; INCLK1_INPUT_FREQUENCY        ; 0                        ; Untyped                 ;
; GATE_LOCK_SIGNAL              ; NO                       ; Untyped                 ;
; GATE_LOCK_COUNTER             ; 0                        ; Untyped                 ;
; LOCK_HIGH                     ; 1                        ; Untyped                 ;
; LOCK_LOW                      ; 1                        ; Untyped                 ;
; VALID_LOCK_MULTIPLIER         ; 1                        ; Untyped                 ;
; INVALID_LOCK_MULTIPLIER       ; 5                        ; Untyped                 ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                      ; Untyped                 ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                      ; Untyped                 ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                      ; Untyped                 ;
; SKIP_VCO                      ; OFF                      ; Untyped                 ;
; SWITCH_OVER_COUNTER           ; 0                        ; Untyped                 ;
; SWITCH_OVER_TYPE              ; AUTO                     ; Untyped                 ;
; FEEDBACK_SOURCE               ; EXTCLK0                  ; Untyped                 ;
; BANDWIDTH                     ; 0                        ; Untyped                 ;
; BANDWIDTH_TYPE                ; AUTO                     ; Untyped                 ;
; SPREAD_FREQUENCY              ; 0                        ; Untyped                 ;
; DOWN_SPREAD                   ; 0                        ; Untyped                 ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                      ; Untyped                 ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                      ; Untyped                 ;
; CLK9_MULTIPLY_BY              ; 0                        ; Untyped                 ;
; CLK8_MULTIPLY_BY              ; 0                        ; Untyped                 ;
; CLK7_MULTIPLY_BY              ; 0                        ; Untyped                 ;
; CLK6_MULTIPLY_BY              ; 0                        ; Untyped                 ;
; CLK5_MULTIPLY_BY              ; 1                        ; Untyped                 ;
; CLK4_MULTIPLY_BY              ; 1                        ; Untyped                 ;
; CLK3_MULTIPLY_BY              ; 1                        ; Untyped                 ;
; CLK2_MULTIPLY_BY              ; 1                        ; Untyped                 ;
; CLK1_MULTIPLY_BY              ; 1                        ; Untyped                 ;
; CLK0_MULTIPLY_BY              ; 2                        ; Signed Integer          ;
; CLK9_DIVIDE_BY                ; 0                        ; Untyped                 ;
; CLK8_DIVIDE_BY                ; 0                        ; Untyped                 ;
; CLK7_DIVIDE_BY                ; 0                        ; Untyped                 ;
; CLK6_DIVIDE_BY                ; 0                        ; Untyped                 ;
; CLK5_DIVIDE_BY                ; 1                        ; Untyped                 ;
; CLK4_DIVIDE_BY                ; 1                        ; Untyped                 ;
; CLK3_DIVIDE_BY                ; 1                        ; Untyped                 ;
; CLK2_DIVIDE_BY                ; 1                        ; Untyped                 ;
; CLK1_DIVIDE_BY                ; 1                        ; Untyped                 ;
; CLK0_DIVIDE_BY                ; 1                        ; Signed Integer          ;
; CLK9_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK8_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK7_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK6_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK5_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK4_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK3_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK2_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK1_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK0_PHASE_SHIFT              ; 0                        ; Untyped                 ;
; CLK5_TIME_DELAY               ; 0                        ; Untyped                 ;
; CLK4_TIME_DELAY               ; 0                        ; Untyped                 ;
; CLK3_TIME_DELAY               ; 0                        ; Untyped                 ;
; CLK2_TIME_DELAY               ; 0                        ; Untyped                 ;
; CLK1_TIME_DELAY               ; 0                        ; Untyped                 ;
; CLK0_TIME_DELAY               ; 0                        ; Untyped                 ;
; CLK9_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK8_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK7_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK6_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK5_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK4_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK3_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK2_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK1_DUTY_CYCLE               ; 50                       ; Untyped                 ;
; CLK0_DUTY_CYCLE               ; 50                       ; Signed Integer          ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                      ; Untyped                 ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                      ; Untyped                 ;
; LOCK_WINDOW_UI                ;  0.05                    ; Untyped                 ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                   ; Untyped                 ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                   ; Untyped                 ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                   ; Untyped                 ;
; DPA_MULTIPLY_BY               ; 0                        ; Untyped                 ;
; DPA_DIVIDE_BY                 ; 1                        ; Untyped                 ;
; DPA_DIVIDER                   ; 0                        ; Untyped                 ;
; EXTCLK3_MULTIPLY_BY           ; 1                        ; Untyped                 ;
; EXTCLK2_MULTIPLY_BY           ; 1                        ; Untyped                 ;
; EXTCLK1_MULTIPLY_BY           ; 1                        ; Untyped                 ;
; EXTCLK0_MULTIPLY_BY           ; 1                        ; Untyped                 ;
; EXTCLK3_DIVIDE_BY             ; 1                        ; Untyped                 ;
; EXTCLK2_DIVIDE_BY             ; 1                        ; Untyped                 ;
; EXTCLK1_DIVIDE_BY             ; 1                        ; Untyped                 ;
; EXTCLK0_DIVIDE_BY             ; 1                        ; Untyped                 ;
; EXTCLK3_PHASE_SHIFT           ; 0                        ; Untyped                 ;
; EXTCLK2_PHASE_SHIFT           ; 0                        ; Untyped                 ;
; EXTCLK1_PHASE_SHIFT           ; 0                        ; Untyped                 ;
; EXTCLK0_PHASE_SHIFT           ; 0                        ; Untyped                 ;
; EXTCLK3_TIME_DELAY            ; 0                        ; Untyped                 ;
; EXTCLK2_TIME_DELAY            ; 0                        ; Untyped                 ;
; EXTCLK1_TIME_DELAY            ; 0                        ; Untyped                 ;
; EXTCLK0_TIME_DELAY            ; 0                        ; Untyped                 ;
; EXTCLK3_DUTY_CYCLE            ; 50                       ; Untyped                 ;
; EXTCLK2_DUTY_CYCLE            ; 50                       ; Untyped                 ;
; EXTCLK1_DUTY_CYCLE            ; 50                       ; Untyped                 ;
; EXTCLK0_DUTY_CYCLE            ; 50                       ; Untyped                 ;
; VCO_MULTIPLY_BY               ; 0                        ; Untyped                 ;
; VCO_DIVIDE_BY                 ; 0                        ; Untyped                 ;
; SCLKOUT0_PHASE_SHIFT          ; 0                        ; Untyped                 ;
; SCLKOUT1_PHASE_SHIFT          ; 0                        ; Untyped                 ;
; VCO_MIN                       ; 0                        ; Untyped                 ;
; VCO_MAX                       ; 0                        ; Untyped                 ;
; VCO_CENTER                    ; 0                        ; Untyped                 ;
; PFD_MIN                       ; 0                        ; Untyped                 ;
; PFD_MAX                       ; 0                        ; Untyped                 ;
; M_INITIAL                     ; 0                        ; Untyped                 ;
; M                             ; 0                        ; Untyped                 ;
; N                             ; 1                        ; Untyped                 ;
; M2                            ; 1                        ; Untyped                 ;
; N2                            ; 1                        ; Untyped                 ;
; SS                            ; 1                        ; Untyped                 ;
; C0_HIGH                       ; 0                        ; Untyped                 ;
; C1_HIGH                       ; 0                        ; Untyped                 ;
; C2_HIGH                       ; 0                        ; Untyped                 ;
; C3_HIGH                       ; 0                        ; Untyped                 ;
; C4_HIGH                       ; 0                        ; Untyped                 ;
; C5_HIGH                       ; 0                        ; Untyped                 ;
; C6_HIGH                       ; 0                        ; Untyped                 ;
; C7_HIGH                       ; 0                        ; Untyped                 ;
; C8_HIGH                       ; 0                        ; Untyped                 ;
; C9_HIGH                       ; 0                        ; Untyped                 ;
; C0_LOW                        ; 0                        ; Untyped                 ;
; C1_LOW                        ; 0                        ; Untyped                 ;
; C2_LOW                        ; 0                        ; Untyped                 ;
; C3_LOW                        ; 0                        ; Untyped                 ;
; C4_LOW                        ; 0                        ; Untyped                 ;
; C5_LOW                        ; 0                        ; Untyped                 ;
; C6_LOW                        ; 0                        ; Untyped                 ;
; C7_LOW                        ; 0                        ; Untyped                 ;
; C8_LOW                        ; 0                        ; Untyped                 ;
; C9_LOW                        ; 0                        ; Untyped                 ;
; C0_INITIAL                    ; 0                        ; Untyped                 ;
; C1_INITIAL                    ; 0                        ; Untyped                 ;
; C2_INITIAL                    ; 0                        ; Untyped                 ;
; C3_INITIAL                    ; 0                        ; Untyped                 ;
; C4_INITIAL                    ; 0                        ; Untyped                 ;
; C5_INITIAL                    ; 0                        ; Untyped                 ;
; C6_INITIAL                    ; 0                        ; Untyped                 ;
; C7_INITIAL                    ; 0                        ; Untyped                 ;
; C8_INITIAL                    ; 0                        ; Untyped                 ;
; C9_INITIAL                    ; 0                        ; Untyped                 ;
; C0_MODE                       ; BYPASS                   ; Untyped                 ;
; C1_MODE                       ; BYPASS                   ; Untyped                 ;
; C2_MODE                       ; BYPASS                   ; Untyped                 ;
; C3_MODE                       ; BYPASS                   ; Untyped                 ;
; C4_MODE                       ; BYPASS                   ; Untyped                 ;
; C5_MODE                       ; BYPASS                   ; Untyped                 ;
; C6_MODE                       ; BYPASS                   ; Untyped                 ;
; C7_MODE                       ; BYPASS                   ; Untyped                 ;
; C8_MODE                       ; BYPASS                   ; Untyped                 ;
; C9_MODE                       ; BYPASS                   ; Untyped                 ;
; C0_PH                         ; 0                        ; Untyped                 ;
; C1_PH                         ; 0                        ; Untyped                 ;
; C2_PH                         ; 0                        ; Untyped                 ;
; C3_PH                         ; 0                        ; Untyped                 ;
; C4_PH                         ; 0                        ; Untyped                 ;
; C5_PH                         ; 0                        ; Untyped                 ;
; C6_PH                         ; 0                        ; Untyped                 ;
; C7_PH                         ; 0                        ; Untyped                 ;
; C8_PH                         ; 0                        ; Untyped                 ;
; C9_PH                         ; 0                        ; Untyped                 ;
; L0_HIGH                       ; 1                        ; Untyped                 ;
; L1_HIGH                       ; 1                        ; Untyped                 ;
; G0_HIGH                       ; 1                        ; Untyped                 ;
; G1_HIGH                       ; 1                        ; Untyped                 ;
; G2_HIGH                       ; 1                        ; Untyped                 ;
; G3_HIGH                       ; 1                        ; Untyped                 ;
; E0_HIGH                       ; 1                        ; Untyped                 ;
; E1_HIGH                       ; 1                        ; Untyped                 ;
; E2_HIGH                       ; 1                        ; Untyped                 ;
; E3_HIGH                       ; 1                        ; Untyped                 ;
; L0_LOW                        ; 1                        ; Untyped                 ;
; L1_LOW                        ; 1                        ; Untyped                 ;
; G0_LOW                        ; 1                        ; Untyped                 ;
; G1_LOW                        ; 1                        ; Untyped                 ;
; G2_LOW                        ; 1                        ; Untyped                 ;
; G3_LOW                        ; 1                        ; Untyped                 ;
; E0_LOW                        ; 1                        ; Untyped                 ;
; E1_LOW                        ; 1                        ; Untyped                 ;
; E2_LOW                        ; 1                        ; Untyped                 ;
; E3_LOW                        ; 1                        ; Untyped                 ;
; L0_INITIAL                    ; 1                        ; Untyped                 ;
; L1_INITIAL                    ; 1                        ; Untyped                 ;
; G0_INITIAL                    ; 1                        ; Untyped                 ;
; G1_INITIAL                    ; 1                        ; Untyped                 ;
; G2_INITIAL                    ; 1                        ; Untyped                 ;
; G3_INITIAL                    ; 1                        ; Untyped                 ;
; E0_INITIAL                    ; 1                        ; Untyped                 ;
; E1_INITIAL                    ; 1                        ; Untyped                 ;
; E2_INITIAL                    ; 1                        ; Untyped                 ;
; E3_INITIAL                    ; 1                        ; Untyped                 ;
; L0_MODE                       ; BYPASS                   ; Untyped                 ;
; L1_MODE                       ; BYPASS                   ; Untyped                 ;
; G0_MODE                       ; BYPASS                   ; Untyped                 ;
; G1_MODE                       ; BYPASS                   ; Untyped                 ;
; G2_MODE                       ; BYPASS                   ; Untyped                 ;
; G3_MODE                       ; BYPASS                   ; Untyped                 ;
; E0_MODE                       ; BYPASS                   ; Untyped                 ;
; E1_MODE                       ; BYPASS                   ; Untyped                 ;
; E2_MODE                       ; BYPASS                   ; Untyped                 ;
; E3_MODE                       ; BYPASS                   ; Untyped                 ;
; L0_PH                         ; 0                        ; Untyped                 ;
; L1_PH                         ; 0                        ; Untyped                 ;
; G0_PH                         ; 0                        ; Untyped                 ;
; G1_PH                         ; 0                        ; Untyped                 ;
; G2_PH                         ; 0                        ; Untyped                 ;
; G3_PH                         ; 0                        ; Untyped                 ;
; E0_PH                         ; 0                        ; Untyped                 ;
; E1_PH                         ; 0                        ; Untyped                 ;
; E2_PH                         ; 0                        ; Untyped                 ;
; E3_PH                         ; 0                        ; Untyped                 ;
; M_PH                          ; 0                        ; Untyped                 ;
; C1_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; C2_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; C3_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; C4_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; C5_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; C6_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; C7_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; C8_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; C9_USE_CASC_IN                ; OFF                      ; Untyped                 ;
; CLK0_COUNTER                  ; G0                       ; Untyped                 ;
; CLK1_COUNTER                  ; G0                       ; Untyped                 ;
; CLK2_COUNTER                  ; G0                       ; Untyped                 ;
; CLK3_COUNTER                  ; G0                       ; Untyped                 ;
; CLK4_COUNTER                  ; G0                       ; Untyped                 ;
; CLK5_COUNTER                  ; G0                       ; Untyped                 ;
; CLK6_COUNTER                  ; E0                       ; Untyped                 ;
; CLK7_COUNTER                  ; E1                       ; Untyped                 ;
; CLK8_COUNTER                  ; E2                       ; Untyped                 ;
; CLK9_COUNTER                  ; E3                       ; Untyped                 ;
; L0_TIME_DELAY                 ; 0                        ; Untyped                 ;
; L1_TIME_DELAY                 ; 0                        ; Untyped                 ;
; G0_TIME_DELAY                 ; 0                        ; Untyped                 ;
; G1_TIME_DELAY                 ; 0                        ; Untyped                 ;
; G2_TIME_DELAY                 ; 0                        ; Untyped                 ;
; G3_TIME_DELAY                 ; 0                        ; Untyped                 ;
; E0_TIME_DELAY                 ; 0                        ; Untyped                 ;
; E1_TIME_DELAY                 ; 0                        ; Untyped                 ;
; E2_TIME_DELAY                 ; 0                        ; Untyped                 ;
; E3_TIME_DELAY                 ; 0                        ; Untyped                 ;
; M_TIME_DELAY                  ; 0                        ; Untyped                 ;
; N_TIME_DELAY                  ; 0                        ; Untyped                 ;
; EXTCLK3_COUNTER               ; E3                       ; Untyped                 ;
; EXTCLK2_COUNTER               ; E2                       ; Untyped                 ;
; EXTCLK1_COUNTER               ; E1                       ; Untyped                 ;
; EXTCLK0_COUNTER               ; E0                       ; Untyped                 ;
; ENABLE0_COUNTER               ; L0                       ; Untyped                 ;
; ENABLE1_COUNTER               ; L0                       ; Untyped                 ;
; CHARGE_PUMP_CURRENT           ; 2                        ; Untyped                 ;
; LOOP_FILTER_R                 ;  1.000000                ; Untyped                 ;
; LOOP_FILTER_C                 ; 5                        ; Untyped                 ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                     ; Untyped                 ;
; LOOP_FILTER_R_BITS            ; 9999                     ; Untyped                 ;
; LOOP_FILTER_C_BITS            ; 9999                     ; Untyped                 ;
; VCO_POST_SCALE                ; 0                        ; Untyped                 ;
; CLK2_OUTPUT_FREQUENCY         ; 0                        ; Untyped                 ;
; CLK1_OUTPUT_FREQUENCY         ; 0                        ; Untyped                 ;
; CLK0_OUTPUT_FREQUENCY         ; 0                        ; Untyped                 ;
; INTENDED_DEVICE_FAMILY        ; Stratix IV               ; Untyped                 ;
; PORT_CLKENA0                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLKENA1                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLKENA2                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLKENA3                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLKENA4                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLKENA5                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_EXTCLK0                  ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_EXTCLK1                  ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_EXTCLK2                  ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_EXTCLK3                  ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_CLKBAD0                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLKBAD1                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK0                     ; PORT_USED                ; Untyped                 ;
; PORT_CLK1                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK2                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK3                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK4                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK5                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK6                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK7                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK8                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLK9                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCANDATA                 ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCANDATAOUT              ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCANDONE                 ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLKLOSS                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_INCLK1                   ; PORT_UNUSED              ; Untyped                 ;
; PORT_INCLK0                   ; PORT_USED                ; Untyped                 ;
; PORT_FBIN                     ; PORT_UNUSED              ; Untyped                 ;
; PORT_PLLENA                   ; PORT_UNUSED              ; Untyped                 ;
; PORT_CLKSWITCH                ; PORT_UNUSED              ; Untyped                 ;
; PORT_ARESET                   ; PORT_UNUSED              ; Untyped                 ;
; PORT_PFDENA                   ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCANCLK                  ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCANACLR                 ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCANREAD                 ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCANWRITE                ; PORT_UNUSED              ; Untyped                 ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_LOCKED                   ; PORT_UNUSED              ; Untyped                 ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED              ; Untyped                 ;
; PORT_FBOUT                    ; PORT_UNUSED              ; Untyped                 ;
; PORT_PHASEDONE                ; PORT_UNUSED              ; Untyped                 ;
; PORT_PHASESTEP                ; PORT_UNUSED              ; Untyped                 ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED              ; Untyped                 ;
; PORT_SCANCLKENA               ; PORT_UNUSED              ; Untyped                 ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED              ; Untyped                 ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY        ; Untyped                 ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY        ; Untyped                 ;
; M_TEST_SOURCE                 ; 5                        ; Untyped                 ;
; C0_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C1_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C2_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C3_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C4_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C5_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C6_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C7_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C8_TEST_SOURCE                ; 5                        ; Untyped                 ;
; C9_TEST_SOURCE                ; 5                        ; Untyped                 ;
; CBXI_PARAMETER                ; PLL_LA_altpll            ; Untyped                 ;
; VCO_FREQUENCY_CONTROL         ; AUTO                     ; Untyped                 ;
; VCO_PHASE_SHIFT_STEP          ; 0                        ; Untyped                 ;
; WIDTH_CLOCK                   ; 10                       ; Signed Integer          ;
; WIDTH_PHASECOUNTERSELECT      ; 4                        ; Untyped                 ;
; USING_FBMIMICBIDIR_PORT       ; OFF                      ; Untyped                 ;
; DEVICE_FAMILY                 ; Stratix IV               ; Untyped                 ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                   ; Untyped                 ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                      ; Untyped                 ;
; AUTO_CARRY_CHAINS             ; ON                       ; AUTO_CARRY              ;
; IGNORE_CARRY_BUFFERS          ; OFF                      ; IGNORE_CARRY            ;
; AUTO_CASCADE_CHAINS           ; ON                       ; AUTO_CASCADE            ;
; IGNORE_CASCADE_BUFFERS        ; OFF                      ; IGNORE_CASCADE          ;
+-------------------------------+--------------------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i ;
+----------------------+-------+-------------------------------------------------+
; Parameter Name       ; Value ; Type                                            ;
+----------------------+-------+-------------------------------------------------+
; sim_gtxreset_speedup ; 1     ; Signed Integer                                  ;
+----------------------+-------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|FDR:lane_up_flop_i ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                 ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                           ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0 ;
+-------------------------+-------+----------------------------------------------------------------+
; Parameter Name          ; Value ; Type                                                           ;
+-------------------------+-------+----------------------------------------------------------------+
; starting_channel_number ; 0     ; Signed Integer                                                 ;
+-------------------------+-------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|FD:reset_lanes_flop_i ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                    ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_last_flop_i ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                           ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                     ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_taps_i ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                      ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component ;
+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value      ; Type                                                                                                                                                                                                                                ;
+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 16         ; Signed Integer                                                                                                                                                                                                                      ;
; LPM_DIRECTION          ; LEFT       ; Untyped                                                                                                                                                                                                                             ;
; LPM_AVALUE             ; UNUSED     ; Untyped                                                                                                                                                                                                                             ;
; LPM_SVALUE             ; UNUSED     ; Untyped                                                                                                                                                                                                                             ;
; DEVICE_FAMILY          ; Stratix IV ; Untyped                                                                                                                                                                                                                             ;
; AUTO_CARRY_CHAINS      ; ON         ; AUTO_CARRY                                                                                                                                                                                                                          ;
; IGNORE_CARRY_BUFFERS   ; OFF        ; IGNORE_CARRY                                                                                                                                                                                                                        ;
; AUTO_CASCADE_CHAINS    ; ON         ; AUTO_CASCADE                                                                                                                                                                                                                        ;
; IGNORE_CASCADE_BUFFERS ; OFF        ; IGNORE_CASCADE                                                                                                                                                                                                                      ;
+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value      ; Type                                                                                                                                                                                                            ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON         ; AUTO_CARRY                                                                                                                                                                                                      ;
; IGNORE_CARRY_BUFFERS   ; OFF        ; IGNORE_CARRY                                                                                                                                                                                                    ;
; AUTO_CASCADE_CHAINS    ; ON         ; AUTO_CASCADE                                                                                                                                                                                                    ;
; IGNORE_CASCADE_BUFFERS ; OFF        ; IGNORE_CASCADE                                                                                                                                                                                                  ;
; LPM_WIDTH              ; 1          ; Signed Integer                                                                                                                                                                                                  ;
; LPM_SIZE               ; 16         ; Signed Integer                                                                                                                                                                                                  ;
; LPM_WIDTHS             ; 4          ; Signed Integer                                                                                                                                                                                                  ;
; LPM_PIPELINE           ; 0          ; Signed Integer                                                                                                                                                                                                  ;
; CBXI_PARAMETER         ; mux_76e    ; Untyped                                                                                                                                                                                                         ;
; DEVICE_FAMILY          ; Stratix IV ; Untyped                                                                                                                                                                                                         ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component ;
+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value      ; Type                                                                                                                                                                                                                                ;
+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 16         ; Signed Integer                                                                                                                                                                                                                      ;
; LPM_DIRECTION          ; LEFT       ; Untyped                                                                                                                                                                                                                             ;
; LPM_AVALUE             ; UNUSED     ; Untyped                                                                                                                                                                                                                             ;
; LPM_SVALUE             ; UNUSED     ; Untyped                                                                                                                                                                                                                             ;
; DEVICE_FAMILY          ; Stratix IV ; Untyped                                                                                                                                                                                                                             ;
; AUTO_CARRY_CHAINS      ; ON         ; AUTO_CARRY                                                                                                                                                                                                                          ;
; IGNORE_CARRY_BUFFERS   ; OFF        ; IGNORE_CARRY                                                                                                                                                                                                                        ;
; AUTO_CASCADE_CHAINS    ; ON         ; AUTO_CASCADE                                                                                                                                                                                                                        ;
; IGNORE_CASCADE_BUFFERS ; OFF        ; IGNORE_CASCADE                                                                                                                                                                                                                      ;
+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value      ; Type                                                                                                                                                                                                            ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON         ; AUTO_CARRY                                                                                                                                                                                                      ;
; IGNORE_CARRY_BUFFERS   ; OFF        ; IGNORE_CARRY                                                                                                                                                                                                    ;
; AUTO_CASCADE_CHAINS    ; ON         ; AUTO_CASCADE                                                                                                                                                                                                    ;
; IGNORE_CASCADE_BUFFERS ; OFF        ; IGNORE_CASCADE                                                                                                                                                                                                  ;
; LPM_WIDTH              ; 1          ; Signed Integer                                                                                                                                                                                                  ;
; LPM_SIZE               ; 16         ; Signed Integer                                                                                                                                                                                                  ;
; LPM_WIDTHS             ; 4          ; Signed Integer                                                                                                                                                                                                  ;
; LPM_PIPELINE           ; 0          ; Signed Integer                                                                                                                                                                                                  ;
; CBXI_PARAMETER         ; mux_76e    ; Untyped                                                                                                                                                                                                         ;
; DEVICE_FAMILY          ; Stratix IV ; Untyped                                                                                                                                                                                                         ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_0_i ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                  ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_1_i ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                  ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_a_flop_0_i ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                  ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_0_i ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                  ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_1_i ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                  ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_0_i ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                  ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_1_i ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                                  ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i|FDR:gen_cc_flop_0_i ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                      ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; INIT           ; '0'   ; Enumerated                                                                                                                                                ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0                 ;
+-------------------------------------------------+------------------------------+----------------+
; Parameter Name                                  ; Value                        ; Type           ;
+-------------------------------------------------+------------------------------+----------------+
; lpm_type                                        ; sld_signaltap                ; String         ;
; sld_node_info                                   ; 805334528                    ; Untyped        ;
; SLD_IP_VERSION                                  ; 6                            ; Signed Integer ;
; SLD_IP_MINOR_VERSION                            ; 0                            ; Signed Integer ;
; SLD_COMMON_IP_VERSION                           ; 0                            ; Signed Integer ;
; sld_data_bits                                   ; 39                           ; Untyped        ;
; sld_trigger_bits                                ; 1                            ; Untyped        ;
; SLD_NODE_CRC_BITS                               ; 32                           ; Signed Integer ;
; sld_node_crc_hiword                             ; 19945                        ; Untyped        ;
; sld_node_crc_loword                             ; 10007                        ; Untyped        ;
; SLD_INCREMENTAL_ROUTING                         ; 0                            ; Signed Integer ;
; sld_sample_depth                                ; 2048                         ; Untyped        ;
; sld_segment_size                                ; 2048                         ; Untyped        ;
; sld_ram_block_type                              ; M9K                          ; Untyped        ;
; sld_state_bits                                  ; 11                           ; Untyped        ;
; sld_buffer_full_stop                            ; 1                            ; Untyped        ;
; SLD_MEM_ADDRESS_BITS                            ; 7                            ; Signed Integer ;
; SLD_DATA_BIT_CNTR_BITS                          ; 4                            ; Signed Integer ;
; sld_trigger_level                               ; 1                            ; Untyped        ;
; sld_trigger_in_enabled                          ; 0                            ; Untyped        ;
; sld_advanced_trigger_entity                     ; basic,1,                     ; Untyped        ;
; sld_trigger_level_pipeline                      ; 1                            ; Untyped        ;
; sld_enable_advanced_trigger                     ; 0                            ; Untyped        ;
; SLD_ADVANCED_TRIGGER_1                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_2                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_3                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_4                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_5                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_6                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_7                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_8                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_9                          ; NONE                         ; String         ;
; SLD_ADVANCED_TRIGGER_10                         ; NONE                         ; String         ;
; sld_inversion_mask_length                       ; 28                           ; Untyped        ;
; sld_inversion_mask                              ; 0000000000000000000000000000 ; Untyped        ;
; sld_power_up_trigger                            ; 0                            ; Untyped        ;
; SLD_STATE_FLOW_MGR_ENTITY                       ; state_flow_mgr_entity.vhd    ; String         ;
; sld_state_flow_use_generated                    ; 0                            ; Untyped        ;
; sld_current_resource_width                      ; 1                            ; Untyped        ;
; sld_attribute_mem_mode                          ; OFF                          ; Untyped        ;
; SLD_STORAGE_QUALIFIER_BITS                      ; 1                            ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_GAP_RECORD                ; 0                            ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_MODE                      ; OFF                          ; String         ;
; SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION ; 0                            ; Signed Integer ;
; sld_storage_qualifier_inversion_mask_length     ; 0                            ; Untyped        ;
; SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY ; basic                        ; String         ;
; SLD_STORAGE_QUALIFIER_PIPELINE                  ; 0                            ; Signed Integer ;
+-------------------------------------------------+------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:auto_hub             ;
+--------------------------+----------------------------------+-----------------+
; Parameter Name           ; Value                            ; Type            ;
+--------------------------+----------------------------------+-----------------+
; sld_hub_ip_version       ; 1                                ; Untyped         ;
; sld_hub_ip_minor_version ; 4                                ; Untyped         ;
; sld_common_ip_version    ; 0                                ; Untyped         ;
; device_family            ; Stratix IV                       ; Untyped         ;
; n_nodes                  ; 1                                ; Untyped         ;
; n_sel_bits               ; 1                                ; Untyped         ;
; n_node_ir_bits           ; 8                                ; Untyped         ;
; node_info                ; 00110000000000000110111000000000 ; Unsigned Binary ;
; compilation_mode         ; 1                                ; Untyped         ;
; BROADCAST_FEATURE        ; 1                                ; Signed Integer  ;
; FORCE_IR_CAPTURE_FEATURE ; 1                                ; Signed Integer  ;
+--------------------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                          ;
+-------------------------------+---------------------------------------+
; Name                          ; Value                                 ;
+-------------------------------+---------------------------------------+
; Number of entity instances    ; 1                                     ;
; Entity Instance               ; PLL_LA:LA_PLL|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                ;
;     -- PLL_TYPE               ; AUTO                                  ;
;     -- PRIMARY_CLOCK          ; INCLK0                                ;
;     -- INCLK0_INPUT_FREQUENCY ; 6400                                  ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                     ;
;     -- VCO_MULTIPLY_BY        ; 0                                     ;
;     -- VCO_DIVIDE_BY          ; 0                                     ;
+-------------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_shiftreg Parameter Settings by Entity Instance                                                                                                                                                                                                        ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                                                                                                                                        ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                                                                                                                                                            ;
; Entity Instance            ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component ;
;     -- LPM_WIDTH           ; 16                                                                                                                                                                                                                           ;
;     -- LPM_DIRECTION       ; LEFT                                                                                                                                                                                                                         ;
; Entity Instance            ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component ;
;     -- LPM_WIDTH           ; 16                                                                                                                                                                                                                           ;
;     -- LPM_DIRECTION       ; LEFT                                                                                                                                                                                                                         ;
+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i" ;
+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                       ;
+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; a0   ; Input ; Info     ; Stuck at GND                                                                                                                                                  ;
; a1   ; Input ; Info     ; Stuck at VCC                                                                                                                                                  ;
; a2   ; Input ; Info     ; Stuck at VCC                                                                                                                                                  ;
; a3   ; Input ; Info     ; Stuck at VCC                                                                                                                                                  ;
+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i" ;
+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                       ;
+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; a0   ; Input ; Info     ; Stuck at VCC                                                                                                                                                  ;
; a1   ; Input ; Info     ; Stuck at VCC                                                                                                                                                  ;
; a2   ; Input ; Info     ; Stuck at VCC                                                                                                                                                  ;
; a3   ; Input ; Info     ; Stuck at VCC                                                                                                                                                  ;
+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i"                 ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                             ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
; ch_bond_done      ; Input  ; Info     ; Stuck at GND                                                                        ;
; en_chan_sync      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; channel_bond_load ; Input  ; Info     ; Stuck at GND                                                                        ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0"                                            ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port             ; Type   ; Severity ; Details                                                                             ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; reconfig_clk     ; Input  ; Info     ; Stuck at GND                                                                        ;
; reconfig_fromgxb ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i"                 ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                             ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+
; rx_status         ; Input  ; Info     ; Stuck at GND                                                                        ;
; channel_bond_load ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "aurora_8b10b_v5_2:aurora_module_i"                                                        ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; Port       ; Type   ; Severity ; Details                                                                             ;
+------------+--------+----------+-------------------------------------------------------------------------------------+
; power_down ; Input  ; Info     ; Stuck at GND                                                                        ;
; loopback   ; Input  ; Info     ; Stuck at GND                                                                        ;
; tx_out_clk ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "PLL_LA:LA_PLL"                                                                      ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type   ; Severity ; Details                                                                             ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; c0   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                                                                    ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Segments ; Storage Qualifier Type ; Trigger Flow Control ; Trigger Conditions ; Advanced Trigger Conditions ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; 0              ; auto_signaltap_0 ; 1                   ; 39               ; 2048         ; 1        ; continuous             ; sequential           ; 1                  ; 0                           ; no              ; no               ; no                       ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:54     ;
+----------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Connections to In-System Debugging Instance "auto_signaltap_0"                                                                                                                                                                                                                                                                                                                              ;
+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-----------+----------------+-------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Name                                                                                                                                               ; Type          ; Status    ; Partition Name ; Netlist Type Used ; Actual Connection                                                                                                                                           ; Details ;
+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-----------+----------------+-------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|tx_clkout[0]                                                                                   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|tx_coreclk_in[0]                                                                                        ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|DO_WORD_ALIGN                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|DO_WORD_ALIGN                 ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|GOT_V                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|GOT_V_Buffer                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|GOT_V_Buffer                   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|GOT_V_Buffer                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RESET                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|FD:reset_lanes_flop_i|Q ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RESET                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|FD:reset_lanes_flop_i|Q ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_CHAR_IS_COMMA[0]            ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_patterndetect[1]                                                                      ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_CHAR_IS_COMMA[1]            ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_patterndetect[0]                                                                      ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_CHAR_IS_K[0]                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_ctrldetect[1]                                                                         ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_CHAR_IS_K[1]                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_ctrldetect[0]                                                                         ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[0]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[8]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[10]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[2]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[11]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[3]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[12]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[4]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[13]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[5]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[14]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[6]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[15]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[7]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[1]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[9]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[2]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[10]                                                                           ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[3]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[11]                                                                           ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[4]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[12]                                                                           ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[5]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[13]                                                                           ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[6]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[14]                                                                           ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[7]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[15]                                                                           ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[8]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[0]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|RX_DATA[9]                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[1]                                                                            ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|got_v_c                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|got_v_c~1                               ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|left_aligned_r                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|left_aligned_r                          ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[0]             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_sp_d_r[0]                     ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[1]             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_scp_d_r[1]                           ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[2]             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[2]                      ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[3]             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[3]                      ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_r                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_r                           ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_pe_control_r[0]             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_pe_control_r[0]                      ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_pe_control_r[1]             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_pe_control_r[1]                      ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[0]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[0]                             ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[1]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[1]                             ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[2]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[2]                      ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|rx_v_d_r[3]                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|prev_beat_v_d_r[3]                      ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|word_aligned_control_bits_r[0] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|word_aligned_control_bits_r[0]          ; N/A     ;
; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|word_aligned_control_bits_r[1] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i|word_aligned_control_bits_r[1]          ; N/A     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-----------+----------------+-------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Sep 16 11:23:55 2011
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 2 design units, including 1 entities, in source file srl16.vhd
    Info: Found design unit 1: SRL16-arch
    Info: Found entity 1: SRL16
Info: Found 2 design units, including 1 entities, in source file muxcy.vhd
    Info: Found design unit 1: MUXCY-MAPPED
    Info: Found entity 1: MUXCY
Info: Found 2 design units, including 1 entities, in source file mux16to1.vhd
    Info: Found design unit 1: mux16to1-SYN
    Info: Found entity 1: MUX16to1
Info: Found 2 design units, including 1 entities, in source file lpmshiftreg16.vhd
    Info: Found design unit 1: lpmshiftreg16-SYN
    Info: Found entity 1: LPMSHIFTREG16
Info: Found 2 design units, including 1 entities, in source file fdr.vhd
    Info: Found design unit 1: FDR-MAIN
    Info: Found entity 1: FDR
Info: Found 2 design units, including 1 entities, in source file fd.vhd
    Info: Found design unit 1: FD-MAIN
    Info: Found entity 1: FD
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_FRAME_CHECK-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_FRAME_CHECK
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_FRAME_GEN-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_FRAME_GEN
Warning (10335): Unrecognized synthesis attribute "core_generation_info" at aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd(93)
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_CLOCK_MODULE-MAPPED
    Info: Found entity 1: aurora_8b10b_v5_2_CLOCK_MODULE
Warning (10335): Unrecognized synthesis attribute "core_generation_info" at aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd(87)
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_STANDARD_CC_MODULE-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_STANDARD_CC_MODULE
Warning (10335): Unrecognized synthesis attribute "core_generation_info" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd(142)
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2-MAPPED
    Info: Found entity 1: aurora_8b10b_v5_2
Warning (10335): Unrecognized synthesis attribute "core_generation_info" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(109)
Warning (10335): Unrecognized synthesis attribute "ASYNC_REG" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(194)
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_example_design-MAPPED
    Info: Found entity 1: aurora_8b10b_v5_2_example_design
Warning (10335): Unrecognized synthesis attribute "core_generation_info" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(84)
Warning (10335): Unrecognized synthesis attribute "ASYNC_REG" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(100)
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_RESET_LOGIC-MAPPED
    Info: Found entity 1: aurora_8b10b_v5_2_RESET_LOGIC
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_AURORA_LANE-MAPPED
    Info: Found entity 1: aurora_8b10b_v5_2_AURORA_LANE
Info: Found 2 design units, including 0 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd
    Info: Found design unit 1: AURORA_PKG
    Info: Found design unit 2: AURORA_PKG-body
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_CHANNEL_ERR_DETECT-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_CHANNEL_ERR_DETECT
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_CHANNEL_INIT_SM-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_CHANNEL_INIT_SM
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_CHBOND_COUNT_DEC-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_CHBOND_COUNT_DEC
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_ERR_DETECT-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_ERR_DETECT
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_GLOBAL_LOGIC-MAPPED
    Info: Found entity 1: aurora_8b10b_v5_2_GLOBAL_LOGIC
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_IDLE_AND_VER_GEN-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_IDLE_AND_VER_GEN
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_LANE_INIT_SM-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_LANE_INIT_SM
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_RX_LL-MAPPED
    Info: Found entity 1: aurora_8b10b_v5_2_RX_LL
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_SYM_DEC-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_SYM_DEC
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_SYM_GEN-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_SYM_GEN
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL-MAPPED
    Info: Found entity 1: aurora_8b10b_v5_2_TX_LL
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL_CONTROL-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_TX_LL_CONTROL
Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd
    Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL_DATAPATH-RTL
    Info: Found entity 1: aurora_8b10b_v5_2_TX_LL_DATAPATH
Info: Found 2 design units, including 1 entities, in source file mgt156_to_156.vhd
    Info: Found design unit 1: mgt156_to_156-SYN
    Info: Found entity 1: MGT156_to_156
Info: Found 2 design units, including 1 entities, in source file pll_la.vhd
    Info: Found design unit 1: pll_la-SYN
    Info: Found entity 1: PLL_LA
Info: Found 4 design units, including 2 entities, in source file mgt.vhd
    Info: Found design unit 1: MGT_alt4gxb-RTL
    Info: Found design unit 2: mgt-RTL
    Info: Found entity 1: MGT_alt4gxb
    Info: Found entity 2: MGT
Info: Found 2 design units, including 1 entities, in source file la.vhd
    Info: Found design unit 1: la-SYN
    Info: Found entity 1: LA
Info: Elaborating entity "aurora_8b10b_v5_2_example_design" for the top level hierarchy
Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2_example_design.vhd(174): used implicit default value for signal "sync_clk_i" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_example_design.vhd(179): object "tx_out_clk_i" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_example_design.vhd(442): object "la_clk" assigned a value but never read
Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2_example_design.vhd(445): used implicit default value for signal "tx_user_clk_i" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Info: Elaborating entity "PLL_LA" for hierarchy "PLL_LA:LA_PLL"
Info: Elaborating entity "altpll" for hierarchy "PLL_LA:LA_PLL|altpll:altpll_component"
Info: Elaborated megafunction instantiation "PLL_LA:LA_PLL|altpll:altpll_component"
Info: Instantiated megafunction "PLL_LA:LA_PLL|altpll:altpll_component" with the following parameter:
    Info: Parameter "bandwidth_type" = "AUTO"
    Info: Parameter "clk0_divide_by" = "1"
    Info: Parameter "clk0_duty_cycle" = "50"
    Info: Parameter "clk0_multiply_by" = "2"
    Info: Parameter "clk0_phase_shift" = "0"
    Info: Parameter "compensate_clock" = "CLK0"
    Info: Parameter "inclk0_input_frequency" = "6400"
    Info: Parameter "intended_device_family" = "Stratix IV"
    Info: Parameter "lpm_hint" = "CBX_MODULE_PREFIX=PLL_LA"
    Info: Parameter "lpm_type" = "altpll"
    Info: Parameter "operation_mode" = "NORMAL"
    Info: Parameter "pll_type" = "AUTO"
    Info: Parameter "port_activeclock" = "PORT_UNUSED"
    Info: Parameter "port_areset" = "PORT_UNUSED"
    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
    Info: Parameter "port_clkloss" = "PORT_UNUSED"
    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
    Info: Parameter "port_configupdate" = "PORT_UNUSED"
    Info: Parameter "port_fbin" = "PORT_UNUSED"
    Info: Parameter "port_fbout" = "PORT_UNUSED"
    Info: Parameter "port_inclk0" = "PORT_USED"
    Info: Parameter "port_inclk1" = "PORT_UNUSED"
    Info: Parameter "port_locked" = "PORT_UNUSED"
    Info: Parameter "port_pfdena" = "PORT_UNUSED"
    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info: Parameter "port_phasedone" = "PORT_UNUSED"
    Info: Parameter "port_phasestep" = "PORT_UNUSED"
    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info: Parameter "port_pllena" = "PORT_UNUSED"
    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
    Info: Parameter "port_scanclk" = "PORT_UNUSED"
    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
    Info: Parameter "port_scandata" = "PORT_UNUSED"
    Info: Parameter "port_scandataout" = "PORT_UNUSED"
    Info: Parameter "port_scandone" = "PORT_UNUSED"
    Info: Parameter "port_scanread" = "PORT_UNUSED"
    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
    Info: Parameter "port_clk0" = "PORT_USED"
    Info: Parameter "port_clk1" = "PORT_UNUSED"
    Info: Parameter "port_clk2" = "PORT_UNUSED"
    Info: Parameter "port_clk3" = "PORT_UNUSED"
    Info: Parameter "port_clk4" = "PORT_UNUSED"
    Info: Parameter "port_clk5" = "PORT_UNUSED"
    Info: Parameter "port_clk6" = "PORT_UNUSED"
    Info: Parameter "port_clk7" = "PORT_UNUSED"
    Info: Parameter "port_clk8" = "PORT_UNUSED"
    Info: Parameter "port_clk9" = "PORT_UNUSED"
    Info: Parameter "port_clkena0" = "PORT_UNUSED"
    Info: Parameter "port_clkena1" = "PORT_UNUSED"
    Info: Parameter "port_clkena2" = "PORT_UNUSED"
    Info: Parameter "port_clkena3" = "PORT_UNUSED"
    Info: Parameter "port_clkena4" = "PORT_UNUSED"
    Info: Parameter "port_clkena5" = "PORT_UNUSED"
    Info: Parameter "using_fbmimicbidir_port" = "OFF"
    Info: Parameter "width_clock" = "10"
Info: Found 1 design units, including 1 entities, in source file db/pll_la_altpll.v
    Info: Found entity 1: PLL_LA_altpll
Info: Elaborating entity "PLL_LA_altpll" for hierarchy "PLL_LA:LA_PLL|altpll:altpll_component|PLL_LA_altpll:auto_generated"
Info: Elaborating entity "aurora_8b10b_v5_2_FRAME_CHECK" for hierarchy "aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i"
Info: Elaborating entity "aurora_8b10b_v5_2_FRAME_GEN" for hierarchy "aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i"
Info: Elaborating entity "aurora_8b10b_v5_2" for hierarchy "aurora_8b10b_v5_2:aurora_module_i"
Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2.vhd(102): used implicit default value for signal "TXN" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(459): object "ch_bond_load_not_used_i" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(462): object "chbondi_not_used_i" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(464): object "en_chan_sync_i" assigned a value but never read
Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2.vhd(491): used implicit default value for signal "raw_tx_out_clk_i" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(502): object "rx_data_width_i" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(506): object "rx_int_data_width_i" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(524): object "tied_to_ground_i" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(526): object "tied_to_vcc_i" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(532): object "tx_data_width_i" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(533): object "tx_int_data_width_i" assigned a value but never read
Info: Elaborating entity "aurora_8b10b_v5_2_AURORA_LANE" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i"
Info: Elaborating entity "aurora_8b10b_v5_2_LANE_INIT_SM" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i"
Info: Elaborating entity "FDR" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|FDR:lane_up_flop_i"
Info: Elaborating entity "aurora_8b10b_v5_2_CHBOND_COUNT_DEC" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i"
Info: Elaborating entity "aurora_8b10b_v5_2_SYM_GEN" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i"
Info: Elaborating entity "aurora_8b10b_v5_2_SYM_DEC" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i"
Info: Elaborating entity "aurora_8b10b_v5_2_ERR_DETECT" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i"
Info: Elaborating entity "MGT_alt4gxb" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0"
Warning (10036): Verilog HDL or VHDL warning at MGT.vhd(168): object "wire_receive_pma0_signaldetect" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at MGT.vhd(177): object "wire_transmit_pcs0_forceelecidleout" assigned a value but never read
Info: Elaborating entity "aurora_8b10b_v5_2_GLOBAL_LOGIC" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i"
Info: Elaborating entity "aurora_8b10b_v5_2_CHANNEL_INIT_SM" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i"
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_channel_init_sm.vhd(174): object "tied_to_vcc" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_channel_init_sm.vhd(175): object "tied_to_gnd" assigned a value but never read
Info: Elaborating entity "FD" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|FD:reset_lanes_flop_i"
Info: Elaborating entity "aurora_8b10b_v5_2_IDLE_AND_VER_GEN" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i"
Info: Elaborating entity "SRL16" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i"
Info: Elaborating entity "LPMSHIFTREG16" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16"
Info: Elaborating entity "lpm_shiftreg" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component"
Info: Elaborated megafunction instantiation "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component"
Info: Instantiated megafunction "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component" with the following parameter:
    Info: Parameter "lpm_direction" = "LEFT"
    Info: Parameter "lpm_type" = "LPM_SHIFTREG"
    Info: Parameter "lpm_width" = "16"
Info: Elaborating entity "MUX16to1" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1"
Info: Elaborating entity "LPM_MUX" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component"
Info: Elaborated megafunction instantiation "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component"
Info: Instantiated megafunction "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "1"
    Info: Parameter "LPM_SIZE" = "16"
    Info: Parameter "LPM_WIDTHS" = "4"
    Info: Parameter "LPM_PIPELINE" = "0"
    Info: Parameter "LPM_TYPE" = "LPM_MUX"
    Info: Parameter "LPM_HINT" = "UNUSED"
Info: Found 1 design units, including 1 entities, in source file db/mux_76e.tdf
    Info: Found entity 1: mux_76e
Info: Elaborating entity "mux_76e" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component|mux_76e:auto_generated"
Info: Elaborating entity "aurora_8b10b_v5_2_CHANNEL_ERR_DETECT" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i"
Info: Elaborating entity "aurora_8b10b_v5_2_TX_LL" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i"
Info: Elaborating entity "aurora_8b10b_v5_2_TX_LL_DATAPATH" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i"
Info: Elaborating entity "aurora_8b10b_v5_2_TX_LL_CONTROL" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i"
Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_tx_ll_control.vhd(153): object "channel_full_c" assigned a value but never read
Info: Elaborating entity "aurora_8b10b_v5_2_RX_LL" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_RX_LL:rx_ll_i"
Info: Elaborating entity "aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH" for hierarchy "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_RX_LL:rx_ll_i|aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i"
Info: Elaborating entity "aurora_8b10b_v5_2_STANDARD_CC_MODULE" for hierarchy "aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i"
Info: Elaborating entity "aurora_8b10b_v5_2_RESET_LOGIC" for hierarchy "aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6p14.tdf
    Info: Found entity 1: altsyncram_6p14
Info: Found 1 design units, including 1 entities, in source file db/mux_opc.tdf
    Info: Found entity 1: mux_opc
Info: Found 1 design units, including 1 entities, in source file db/decode_asf.tdf
    Info: Found entity 1: decode_asf
Info: Found 1 design units, including 1 entities, in source file db/cntr_sdi.tdf
    Info: Found entity 1: cntr_sdi
Info: Found 1 design units, including 1 entities, in source file db/cmpr_pdc.tdf
    Info: Found entity 1: cmpr_pdc
Info: Found 1 design units, including 1 entities, in source file db/cntr_d6j.tdf
    Info: Found entity 1: cntr_d6j
Info: Found 1 design units, including 1 entities, in source file db/cntr_bdi.tdf
    Info: Found entity 1: cntr_bdi
Info: Found 1 design units, including 1 entities, in source file db/cmpr_odc.tdf
    Info: Found entity 1: cmpr_odc
Info: Found 1 design units, including 1 entities, in source file db/cntr_vvi.tdf
    Info: Found entity 1: cntr_vvi
Info: Found 1 design units, including 1 entities, in source file db/cmpr_kdc.tdf
    Info: Found entity 1: cmpr_kdc
Info: Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0"
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following PLL node(s):
        Warning (14320): Synthesized away node "PLL_LA:LA_PLL|altpll:altpll_component|PLL_LA_altpll:auto_generated|wire_pll1_clk[0]"
Warning: Tri-state node(s) do not directly drive top-level pin(s)
    Warning: Converted tri-state buffer "aurora_8b10b_v5_2:aurora_module_i|comb~synth" feeding internal logic into a wire
    Warning: Converted tri-state buffer "aurora_8b10b_v5_2:aurora_module_i|comb~synth" feeding internal logic into a wire
    Warning: Converted tri-state buffer "aurora_8b10b_v5_2:aurora_module_i|comb~synth" feeding internal logic into a wire
    Warning: Converted tri-state buffer "aurora_8b10b_v5_2:aurora_module_i|comb~synth" feeding internal logic into a wire
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "DIS_TX_CLK" is stuck at GND
    Warning (13410): Pin "TXN" is stuck at GND
Info: Timing-Driven Synthesis is running on partition "Top"
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component|dffs[15]" lost all its fanouts during netlist optimizations.
Info: Succesfully connected in-system debug instance "auto_signaltap_0" to all 41 required data inputs, trigger inputs, acquisition clocks, and dynamic pins
Info: Generating hard_block partition "hard_block:auto_generated_inst"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|receive_pcs0"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|transmit_pma0"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|transmit_pcs0"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|cent_unit0"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|receive_pma0"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|ch_clk_div0"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|tx_pll0"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|cal_blk0"
    Info: Adding node "aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|rx_cdr_pll0"
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "RXN"
Info: Implemented 1566 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 19 output pins
    Info: Implemented 1487 logic cells
    Info: Implemented 39 RAM segments
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 40 warnings
    Info: Peak virtual memory: 523 megabytes
    Info: Processing ended: Fri Sep 16 11:25:40 2011
    Info: Elapsed time: 00:01:45
    Info: Total CPU time (on all processors): 00:01:14


