LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;

ENTITY SRL16 IS
	port
	(
		A0  : in  std_ulogic;
        A1  : in  std_ulogic;
        A2  : in  std_ulogic;
        A3  : in  std_ulogic;
		CLK : IN STD_LOGIC;
		D : IN STD_LOGIC;
		Q : OUT STD_LOGIC
	);
END SRL16;

ARCHITECTURE arch OF SRL16 IS

component LPMSHIFTREG16 IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END component;

component MUX16to1 IS
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data10		: IN STD_LOGIC ;
		data11		: IN STD_LOGIC ;
		data12		: IN STD_LOGIC ;
		data13		: IN STD_LOGIC ;
		data14		: IN STD_LOGIC ;
		data15		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		data3		: IN STD_LOGIC ;
		data4		: IN STD_LOGIC ;
		data5		: IN STD_LOGIC ;
		data6		: IN STD_LOGIC ;
		data7		: IN STD_LOGIC ;
		data8		: IN STD_LOGIC ;
		data9		: IN STD_LOGIC ;
		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		result		: OUT STD_LOGIC 
	);
END component;

signal shift_out : STD_LOGIC_VECTOR(15 downto 0);

BEGIN

lpm_shiftreg16 : LPMSHIFTREG16
	PORT map
	(
		clock		=> CLK,
		shiftin		=> D,
		q			=> shift_out
	);
	
MUX_16to1 : MUX16to1
	PORT map
	(
		data0		=> shift_out(0),
		data1		=> shift_out(1),
		data2		=> shift_out(2),
		data3		=> shift_out(3),
		data4		=> shift_out(4),
		data5		=> shift_out(5),
		data6		=> shift_out(6),
		data7		=> shift_out(7),
		data8		=> shift_out(8),
		data9		=> shift_out(9),
		data10		=> shift_out(10),
		data11		=> shift_out(11),
		data12		=> shift_out(12),
		data13		=> shift_out(13),
		data14		=> shift_out(14),
		data15		=> shift_out(15),		
		sel(0)		=> A0,
		sel(1)		=> A1,
		sel(2)		=> A2,
		sel(3)		=> A3,
		result		=> Q
	);

END;