Hierarchy | Input | Constant Input | Unused Input | Floating Input | Output | Constant Output | Unused Output | Floating Output | Bidir | Constant Bidir | Unused Bidir | Input only Bidir | Output only Bidir
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
reset_logic_i | 6 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
standard_cc_module_i | 3 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|rx_ll_i|rx_ll_pdu_datapath_i | 22 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|rx_ll_i | 22 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|tx_ll_i|tx_ll_control_i|gen_cc_flop_0_i | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|tx_ll_i|tx_ll_control_i | 8 | 0 | 2 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|tx_ll_i|tx_ll_datapath_i | 24 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|tx_ll_i | 24 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|channel_err_detect_i | 5 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|gen_r_flop_1_i | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|gen_r_flop_0_i | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|gen_k_flop_1_i | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|gen_k_flop_0_i | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|gen_a_flop_0_i | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|gen_v_flop_1_i | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|gen_v_flop_0_i | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|ver_counter_1_i|MUX_16to1|lpm_mux_component|auto_generated | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|ver_counter_1_i|MUX_16to1 | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|ver_counter_1_i|lpm_shiftreg16 | 2 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|ver_counter_1_i | 6 | 4 | 0 | 4 | 1 | 4 | 4 | 4 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|ver_counter_0_i|MUX_16to1|lpm_mux_component|auto_generated | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|ver_counter_0_i|MUX_16to1 | 20 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|ver_counter_0_i|lpm_shiftreg16 | 2 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|ver_counter_0_i | 6 | 4 | 0 | 4 | 1 | 4 | 4 | 4 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|lfsr_taps_i | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i|lfsr_last_flop_i | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|idle_and_ver_gen_i | 3 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|channel_init_sm_i|reset_lanes_flop_i | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i|channel_init_sm_i | 9 | 1 | 4 | 1 | 5 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
aurora_module_i|global_logic_i | 11 | 3 | 0 | 3 | 13 | 3 | 3 | 3 | 0 | 0 | 0 | 0 | 0
aurora_module_i|MGT_0 | 32 | 18 | 0 | 18 | 49 | 18 | 18 | 18 | 0 | 0 | 0 | 0 | 0
aurora_module_i|aurora_lane_0_i|err_detect_i | 9 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|aurora_lane_0_i|sym_dec_i | 23 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|aurora_lane_0_i|sym_gen_i | 35 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|aurora_lane_0_i|chbond_count_dec_i | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|aurora_lane_0_i|lane_init_sm_i|lane_up_flop_i | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|aurora_lane_0_i|lane_init_sm_i | 13 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
aurora_module_i|aurora_lane_0_i | 64 | 7 | 0 | 7 | 49 | 7 | 7 | 7 | 0 | 0 | 0 | 0 | 0
aurora_module_i | 35 | 5 | 3 | 5 | 32 | 5 | 5 | 5 | 0 | 0 | 0 | 0 | 0
frame_gen_i | 4 | 1 | 0 | 1 | 20 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
frame_check_i | 23 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
LA_PLL|altpll_component|auto_generated | 2 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
LA_PLL | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0