{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 18 13:07:40 2011 " "Info: Processing started: Fri Mar 18 13:07:40 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/replacexilinxcomponent/srl16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /replacexilinxcomponent/srl16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SRL16-arch " "Info: Found design unit 1: SRL16-arch" {  } { { "../ReplaceXilinxComponent/SRL16.vhd" "" { Text "T:/ReplaceXilinxComponent/SRL16.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 SRL16 " "Info: Found entity 1: SRL16" {  } { { "../ReplaceXilinxComponent/SRL16.vhd" "" { Text "T:/ReplaceXilinxComponent/SRL16.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/replacexilinxcomponent/muxcy.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /replacexilinxcomponent/muxcy.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MUXCY-MAPPED " "Info: Found design unit 1: MUXCY-MAPPED" {  } { { "../ReplaceXilinxComponent/MUXCY.vhd" "" { Text "T:/ReplaceXilinxComponent/MUXCY.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 MUXCY " "Info: Found entity 1: MUXCY" {  } { { "../ReplaceXilinxComponent/MUXCY.vhd" "" { Text "T:/ReplaceXilinxComponent/MUXCY.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/replacexilinxcomponent/mux16to1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /replacexilinxcomponent/mux16to1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux16to1-SYN " "Info: Found design unit 1: mux16to1-SYN" {  } { { "../ReplaceXilinxComponent/MUX16to1.vhd" "" { Text "T:/ReplaceXilinxComponent/MUX16to1.vhd" 67 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 MUX16to1 " "Info: Found entity 1: MUX16to1" {  } { { "../ReplaceXilinxComponent/MUX16to1.vhd" "" { Text "T:/ReplaceXilinxComponent/MUX16to1.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/replacexilinxcomponent/lpmshiftreg16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /replacexilinxcomponent/lpmshiftreg16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpmshiftreg16-SYN " "Info: Found design unit 1: lpmshiftreg16-SYN" {  } { { "../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "" { Text "T:/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 LPMSHIFTREG16 " "Info: Found entity 1: LPMSHIFTREG16" {  } { { "../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "" { Text "T:/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/replacexilinxcomponent/fdr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /replacexilinxcomponent/fdr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FDR-MAIN " "Info: Found design unit 1: FDR-MAIN" {  } { { "../ReplaceXilinxComponent/FDR.vhd" "" { Text "T:/ReplaceXilinxComponent/FDR.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 FDR " "Info: Found entity 1: FDR" {  } { { "../ReplaceXilinxComponent/FDR.vhd" "" { Text "T:/ReplaceXilinxComponent/FDR.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/replacexilinxcomponent/fd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /replacexilinxcomponent/fd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FD-MAIN " "Info: Found design unit 1: FD-MAIN" {  } { { "../ReplaceXilinxComponent/FD.vhd" "" { Text "T:/ReplaceXilinxComponent/FD.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 FD " "Info: Found entity 1: FD" {  } { { "../ReplaceXilinxComponent/FD.vhd" "" { Text "T:/ReplaceXilinxComponent/FD.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_FRAME_CHECK-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_FRAME_CHECK-RTL" {  } { { "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" 97 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_FRAME_CHECK " "Info: Found entity 1: aurora_8b10b_v5_2_FRAME_CHECK" {  } { { "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_check.vhd" 75 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_FRAME_GEN-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_FRAME_GEN-RTL" {  } { { "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" 97 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_FRAME_GEN " "Info: Found entity 1: aurora_8b10b_v5_2_FRAME_GEN" {  } { { "aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/traffic_gen_check/aurora_8b10b_v5_2_frame_gen.vhd" 77 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd(93) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd(93)" {  } { { "aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" 93 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_CLOCK_MODULE-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_CLOCK_MODULE-MAPPED" {  } { { "aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" 91 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_CLOCK_MODULE " "Info: Found entity 1: aurora_8b10b_v5_2_CLOCK_MODULE" {  } { { "aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/clock_module/aurora_8b10b_v5_2_clock_module.vhd" 68 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd(87) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd(87)" {  } { { "aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" 87 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_STANDARD_CC_MODULE-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_STANDARD_CC_MODULE-RTL" {  } { { "aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" 85 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_STANDARD_CC_MODULE " "Info: Found entity 1: aurora_8b10b_v5_2_STANDARD_CC_MODULE" {  } { { "aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/cc_manager/aurora_8b10b_v5_2_standard_cc_module.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd(142) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd(142)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 142 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2-MAPPED" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 140 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2 " "Info: Found entity 1: aurora_8b10b_v5_2" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(109) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(109)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 109 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "ASYNC_REG aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(194) " "Warning (10335): Unrecognized synthesis attribute \"ASYNC_REG\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd(194)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 194 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_example_design-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_example_design-MAPPED" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 107 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_example_design " "Info: Found entity 1: aurora_8b10b_v5_2_example_design" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "core_generation_info aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(84) " "Warning (10335): Unrecognized synthesis attribute \"core_generation_info\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(84)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 84 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "ASYNC_REG aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(100) " "Warning (10335): Unrecognized synthesis attribute \"ASYNC_REG\" at aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd(100)" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 100 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_RESET_LOGIC-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_RESET_LOGIC-MAPPED" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 82 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_RESET_LOGIC " "Info: Found entity 1: aurora_8b10b_v5_2_RESET_LOGIC" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 64 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_AURORA_LANE-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_AURORA_LANE-MAPPED" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 131 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_AURORA_LANE " "Info: Found entity 1: aurora_8b10b_v5_2_AURORA_LANE" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 67 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AURORA_PKG " "Info: Found design unit 1: AURORA_PKG" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" 60 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 AURORA_PKG-body " "Info: Found design unit 2: AURORA_PKG-body" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_pkg.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_CHANNEL_ERR_DETECT-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_CHANNEL_ERR_DETECT-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" 91 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_CHANNEL_ERR_DETECT " "Info: Found entity 1: aurora_8b10b_v5_2_CHANNEL_ERR_DETECT" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_err_detect.vhd" 65 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_CHANNEL_INIT_SM-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_CHANNEL_INIT_SM-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 127 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_CHANNEL_INIT_SM " "Info: Found entity 1: aurora_8b10b_v5_2_CHANNEL_INIT_SM" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 91 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_CHBOND_COUNT_DEC-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_CHBOND_COUNT_DEC-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" 76 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_CHBOND_COUNT_DEC " "Info: Found entity 1: aurora_8b10b_v5_2_CHBOND_COUNT_DEC" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_chbond_count_dec.vhd" 64 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_ERR_DETECT-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_ERR_DETECT-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" 95 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_ERR_DETECT " "Info: Found entity 1: aurora_8b10b_v5_2_ERR_DETECT" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_err_detect.vhd" 69 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_GLOBAL_LOGIC-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_GLOBAL_LOGIC-MAPPED" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 100 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_GLOBAL_LOGIC " "Info: Found entity 1: aurora_8b10b_v5_2_GLOBAL_LOGIC" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 63 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_IDLE_AND_VER_GEN-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_IDLE_AND_VER_GEN-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" 99 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_IDLE_AND_VER_GEN " "Info: Found entity 1: aurora_8b10b_v5_2_IDLE_AND_VER_GEN" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" 74 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_LANE_INIT_SM-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_LANE_INIT_SM-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" 120 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_LANE_INIT_SM " "Info: Found entity 1: aurora_8b10b_v5_2_LANE_INIT_SM" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" 71 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_RX_LL-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_RX_LL-MAPPED" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" 101 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_RX_LL " "Info: Found entity 1: aurora_8b10b_v5_2_RX_LL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" 65 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" 101 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH " "Info: Found entity 1: aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd" 67 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_SYM_DEC-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_SYM_DEC-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" 105 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_SYM_DEC " "Info: Found entity 1: aurora_8b10b_v5_2_SYM_DEC" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_dec.vhd" 66 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_SYM_GEN-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_SYM_GEN-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" 117 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_SYM_GEN " "Info: Found entity 1: aurora_8b10b_v5_2_SYM_GEN" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_sym_gen.vhd" 77 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_TX_LL-MAPPED " "Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL-MAPPED" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" 102 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_TX_LL " "Info: Found entity 1: aurora_8b10b_v5_2_TX_LL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" 63 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_TX_LL_CONTROL-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL_CONTROL-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" 109 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_TX_LL_CONTROL " "Info: Found entity 1: aurora_8b10b_v5_2_TX_LL_CONTROL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" 70 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 aurora_8b10b_v5_2_TX_LL_DATAPATH-RTL " "Info: Found design unit 1: aurora_8b10b_v5_2_TX_LL_DATAPATH-RTL" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" 94 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 aurora_8b10b_v5_2_TX_LL_DATAPATH " "Info: Found entity 1: aurora_8b10b_v5_2_TX_LL_DATAPATH" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_datapath.vhd" 62 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mgt156_to_156.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mgt156_to_156.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mgt156_to_156-SYN " "Info: Found design unit 1: mgt156_to_156-SYN" {  } { { "MGT156_to_156.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT156_to_156.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 MGT156_to_156 " "Info: Found entity 1: MGT156_to_156" {  } { { "MGT156_to_156.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT156_to_156.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_la.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pll_la.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll_la-SYN " "Info: Found design unit 1: pll_la-SYN" {  } { { "PLL_LA.vhd" "" { Text "T:/V6aurora_3125M_156M/PLL_LA.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 PLL_LA " "Info: Found entity 1: PLL_LA" {  } { { "PLL_LA.vhd" "" { Text "T:/V6aurora_3125M_156M/PLL_LA.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mgt.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file mgt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MGT_alt4gxb-RTL " "Info: Found design unit 1: MGT_alt4gxb-RTL" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 82 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 mgt-RTL " "Info: Found design unit 2: mgt-RTL" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 2112 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 MGT_alt4gxb " "Info: Found entity 1: MGT_alt4gxb" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 46 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 MGT " "Info: Found entity 2: MGT" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 2075 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "la.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file la.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 la-SYN " "Info: Found design unit 1: la-SYN" {  } { { "LA.vhd" "" { Text "T:/V6aurora_3125M_156M/LA.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 LA " "Info: Found entity 1: LA" {  } { { "LA.vhd" "" { Text "T:/V6aurora_3125M_156M/LA.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "aurora_8b10b_v5_2_example_design " "Info: Elaborating entity \"aurora_8b10b_v5_2_example_design\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "sync_clk_i aurora_8b10b_v5_2_example_design.vhd(174) " "Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2_example_design.vhd(174): used implicit default value for signal \"sync_clk_i\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 174 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tx_out_clk_i aurora_8b10b_v5_2_example_design.vhd(179) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_example_design.vhd(179): object \"tx_out_clk_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 179 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "la_clk aurora_8b10b_v5_2_example_design.vhd(442) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_example_design.vhd(442): object \"la_clk\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 442 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "tx_user_clk_i aurora_8b10b_v5_2_example_design.vhd(445) " "Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2_example_design.vhd(445): used implicit default value for signal \"tx_user_clk_i\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 445 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL_LA PLL_LA:LA_PLL " "Info: Elaborating entity \"PLL_LA\" for hierarchy \"PLL_LA:LA_PLL\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "LA_PLL" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 488 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL_LA:LA_PLL\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL_LA:LA_PLL\|altpll:altpll_component\"" {  } { { "PLL_LA.vhd" "altpll_component" { Text "T:/V6aurora_3125M_156M/PLL_LA.vhd" 135 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "PLL_LA:LA_PLL\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"PLL_LA:LA_PLL\|altpll:altpll_component\"" {  } { { "PLL_LA.vhd" "" { Text "T:/V6aurora_3125M_156M/PLL_LA.vhd" 135 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "PLL_LA:LA_PLL\|altpll:altpll_component " "Info: Instantiated megafunction \"PLL_LA:LA_PLL\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Info: Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Info: Parameter \"clk0_divide_by\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Info: Parameter \"clk0_multiply_by\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 6400 " "Info: Parameter \"inclk0_input_frequency\" = \"6400\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix IV " "Info: Parameter \"intended_device_family\" = \"Stratix IV\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=PLL_LA " "Info: Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=PLL_LA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Info: Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Info: Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Info: Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Info: Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Info: Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Info: Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Info: Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Info: Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Info: Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbout PORT_UNUSED " "Info: Parameter \"port_fbout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Info: Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Info: Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Info: Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Info: Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Info: Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Info: Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Info: Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Info: Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Info: Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Info: Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Info: Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Info: Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Info: Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Info: Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Info: Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Info: Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Info: Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Info: Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Info: Parameter \"port_clk1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Info: Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Info: Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Info: Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Info: Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk6 PORT_UNUSED " "Info: Parameter \"port_clk6\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk7 PORT_UNUSED " "Info: Parameter \"port_clk7\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk8 PORT_UNUSED " "Info: Parameter \"port_clk8\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk9 PORT_UNUSED " "Info: Parameter \"port_clk9\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Info: Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Info: Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Info: Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Info: Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Info: Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Info: Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "using_fbmimicbidir_port OFF " "Info: Parameter \"using_fbmimicbidir_port\" = \"OFF\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 10 " "Info: Parameter \"width_clock\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "PLL_LA.vhd" "" { Text "T:/V6aurora_3125M_156M/PLL_LA.vhd" 135 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_la_altpll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/pll_la_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL_LA_altpll " "Info: Found entity 1: PLL_LA_altpll" {  } { { "db/pll_la_altpll.v" "" { Text "T:/V6aurora_3125M_156M/db/pll_la_altpll.v" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL_LA_altpll PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated " "Info: Elaborating entity \"PLL_LA_altpll\" for hierarchy \"PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/10.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_FRAME_CHECK aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_FRAME_CHECK\" for hierarchy \"aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "frame_check_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 557 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_FRAME_GEN aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_FRAME_GEN\" for hierarchy \"aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "frame_gen_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 577 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2 aurora_8b10b_v5_2:aurora_module_i " "Info: Elaborating entity \"aurora_8b10b_v5_2\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "aurora_module_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 600 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "TXN aurora_8b10b_v5_2.vhd(102) " "Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2.vhd(102): used implicit default value for signal \"TXN\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 102 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ch_bond_load_not_used_i aurora_8b10b_v5_2.vhd(459) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(459): object \"ch_bond_load_not_used_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 459 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "chbondi_not_used_i aurora_8b10b_v5_2.vhd(462) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(462): object \"chbondi_not_used_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 462 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "en_chan_sync_i aurora_8b10b_v5_2.vhd(464) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(464): object \"en_chan_sync_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 464 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "raw_tx_out_clk_i aurora_8b10b_v5_2.vhd(491) " "Warning (10541): VHDL Signal Declaration warning at aurora_8b10b_v5_2.vhd(491): used implicit default value for signal \"raw_tx_out_clk_i\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 491 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rx_data_width_i aurora_8b10b_v5_2.vhd(502) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(502): object \"rx_data_width_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 502 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rx_int_data_width_i aurora_8b10b_v5_2.vhd(506) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(506): object \"rx_int_data_width_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 506 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tied_to_ground_i aurora_8b10b_v5_2.vhd(524) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(524): object \"tied_to_ground_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 524 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tied_to_vcc_i aurora_8b10b_v5_2.vhd(526) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(526): object \"tied_to_vcc_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 526 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tx_data_width_i aurora_8b10b_v5_2.vhd(532) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(532): object \"tx_data_width_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 532 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tx_int_data_width_i aurora_8b10b_v5_2.vhd(533) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2.vhd(533): object \"tx_int_data_width_i\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 533 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_AURORA_LANE aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_AURORA_LANE\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "aurora_lane_0_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 577 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_LANE_INIT_SM aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_LANE_INIT_SM\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "lane_init_sm_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 390 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FDR aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|FDR:lane_up_flop_i " "Info: Elaborating entity \"FDR\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|FDR:lane_up_flop_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" "lane_up_flop_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_lane_init_sm.vhd" 300 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_CHBOND_COUNT_DEC aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_CHBOND_COUNT_DEC\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "chbond_count_dec_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 442 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_SYM_GEN aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_SYM_GEN\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "sym_gen_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 455 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_SYM_DEC aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_SYM_DEC\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "sym_dec_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 496 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_ERR_DETECT aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_ERR_DETECT\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" "err_detect_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_aurora_lane.vhd" 536 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MGT_alt4gxb aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0 " "Info: Elaborating entity \"MGT_alt4gxb\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "MGT_0" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 641 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "wire_receive_pma0_signaldetect MGT.vhd(168) " "Warning (10036): Verilog HDL or VHDL warning at MGT.vhd(168): object \"wire_receive_pma0_signaldetect\" assigned a value but never read" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 168 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "wire_transmit_pcs0_forceelecidleout MGT.vhd(177) " "Warning (10036): Verilog HDL or VHDL warning at MGT.vhd(177): object \"wire_transmit_pcs0_forceelecidleout\" assigned a value but never read" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 177 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_GLOBAL_LOGIC aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_GLOBAL_LOGIC\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "global_logic_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 724 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_CHANNEL_INIT_SM aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_CHANNEL_INIT_SM\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "channel_init_sm_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 229 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tied_to_vcc aurora_8b10b_v5_2_channel_init_sm.vhd(174) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_channel_init_sm.vhd(174): object \"tied_to_vcc\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 174 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tied_to_gnd aurora_8b10b_v5_2_channel_init_sm.vhd(175) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_channel_init_sm.vhd(175): object \"tied_to_gnd\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 175 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FD aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i\|FD:reset_lanes_flop_i " "Info: Elaborating entity \"FD\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i\|FD:reset_lanes_flop_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" "reset_lanes_flop_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_channel_init_sm.vhd" 305 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_IDLE_AND_VER_GEN aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_IDLE_AND_VER_GEN\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "idle_and_ver_gen_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 266 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SRL16 aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i " "Info: Elaborating entity \"SRL16\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" "ver_counter_0_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_idle_and_ver_gen.vhd" 354 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPMSHIFTREG16 aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16 " "Info: Elaborating entity \"LPMSHIFTREG16\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\"" {  } { { "../ReplaceXilinxComponent/SRL16.vhd" "lpm_shiftreg16" { Text "T:/ReplaceXilinxComponent/SRL16.vhd" 57 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_shiftreg aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborating entity \"lpm_shiftreg\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "lpm_shiftreg_component" { Text "T:/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborated megafunction instantiation \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "" { Text "T:/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component " "Info: Instantiated megafunction \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction LEFT " "Info: Parameter \"lpm_direction\" = \"LEFT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_SHIFTREG " "Info: Parameter \"lpm_type\" = \"LPM_SHIFTREG\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Info: Parameter \"lpm_width\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "../ReplaceXilinxComponent/LPMSHIFTREG16.vhd" "" { Text "T:/ReplaceXilinxComponent/LPMSHIFTREG16.vhd" 74 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MUX16to1 aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1 " "Info: Elaborating entity \"MUX16to1\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\"" {  } { { "../ReplaceXilinxComponent/SRL16.vhd" "MUX_16to1" { Text "T:/ReplaceXilinxComponent/SRL16.vhd" 65 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_MUX aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component " "Info: Elaborating entity \"LPM_MUX\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\"" {  } { { "../ReplaceXilinxComponent/MUX16to1.vhd" "lpm_mux_component" { Text "T:/ReplaceXilinxComponent/MUX16to1.vhd" 127 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component " "Info: Elaborated megafunction instantiation \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\"" {  } { { "../ReplaceXilinxComponent/MUX16to1.vhd" "" { Text "T:/ReplaceXilinxComponent/MUX16to1.vhd" 127 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component " "Info: Instantiated megafunction \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 16 " "Info: Parameter \"LPM_SIZE\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 4 " "Info: Parameter \"LPM_WIDTHS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 0 " "Info: Parameter \"LPM_PIPELINE\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MUX " "Info: Parameter \"LPM_TYPE\" = \"LPM_MUX\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Info: Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "../ReplaceXilinxComponent/MUX16to1.vhd" "" { Text "T:/ReplaceXilinxComponent/MUX16to1.vhd" 127 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_76e.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_76e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_76e " "Info: Found entity 1: mux_76e" {  } { { "db/mux_76e.tdf" "" { Text "T:/V6aurora_3125M_156M/db/mux_76e.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_76e aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\|mux_76e:auto_generated " "Info: Elaborating entity \"mux_76e\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_0_i\|MUX16to1:MUX_16to1\|LPM_MUX:lpm_mux_component\|mux_76e:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "c:/altera/10.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_CHANNEL_ERR_DETECT aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_CHANNEL_ERR_DETECT\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" "channel_err_detect_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_global_logic.vhd" 293 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_TX_LL aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_TX_LL\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "tx_ll_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 762 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_TX_LL_DATAPATH aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_TX_LL_DATAPATH\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" "tx_ll_datapath_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" 213 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_TX_LL_CONTROL aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_TX_LL_CONTROL\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_TX_LL:tx_ll_i\|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" "tx_ll_control_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll.vhd" 246 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "channel_full_c aurora_8b10b_v5_2_tx_ll_control.vhd(153) " "Warning (10036): Verilog HDL or VHDL warning at aurora_8b10b_v5_2_tx_ll_control.vhd(153): object \"channel_full_c\" assigned a value but never read" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_tx_ll_control.vhd" 153 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_RX_LL aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_RX_LL:rx_ll_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_RX_LL\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_RX_LL:rx_ll_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" "rx_ll_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2.vhd" 802 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_RX_LL:rx_ll_i\|aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH\" for hierarchy \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_RX_LL:rx_ll_i\|aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i\"" {  } { { "aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" "rx_ll_pdu_datapath_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/src/aurora_8b10b_v5_2_rx_ll.vhd" 167 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_STANDARD_CC_MODULE aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_STANDARD_CC_MODULE\" for hierarchy \"aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "standard_cc_module_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 663 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aurora_8b10b_v5_2_RESET_LOGIC aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i " "Info: Elaborating entity \"aurora_8b10b_v5_2_RESET_LOGIC\" for hierarchy \"aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "reset_logic_i" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 680 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vo14.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vo14.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vo14 " "Info: Found entity 1: altsyncram_vo14" {  } { { "db/altsyncram_vo14.tdf" "" { Text "T:/V6aurora_3125M_156M/db/altsyncram_vo14.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_opc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_opc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_opc " "Info: Found entity 1: mux_opc" {  } { { "db/mux_opc.tdf" "" { Text "T:/V6aurora_3125M_156M/db/mux_opc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_asf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_asf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_asf " "Info: Found entity 1: decode_asf" {  } { { "db/decode_asf.tdf" "" { Text "T:/V6aurora_3125M_156M/db/decode_asf.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rdi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_rdi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_rdi " "Info: Found entity 1: cntr_rdi" {  } { { "db/cntr_rdi.tdf" "" { Text "T:/V6aurora_3125M_156M/db/cntr_rdi.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_pdc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_pdc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_pdc " "Info: Found entity 1: cmpr_pdc" {  } { { "db/cmpr_pdc.tdf" "" { Text "T:/V6aurora_3125M_156M/db/cmpr_pdc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_d6j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_d6j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_d6j " "Info: Found entity 1: cntr_d6j" {  } { { "db/cntr_d6j.tdf" "" { Text "T:/V6aurora_3125M_156M/db/cntr_d6j.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_bdi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_bdi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_bdi " "Info: Found entity 1: cntr_bdi" {  } { { "db/cntr_bdi.tdf" "" { Text "T:/V6aurora_3125M_156M/db/cntr_bdi.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_odc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_odc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_odc " "Info: Found entity 1: cmpr_odc" {  } { { "db/cmpr_odc.tdf" "" { Text "T:/V6aurora_3125M_156M/db/cmpr_odc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_vvi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_vvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_vvi " "Info: Found entity 1: cntr_vvi" {  } { { "db/cntr_vvi.tdf" "" { Text "T:/V6aurora_3125M_156M/db/cntr_vvi.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_kdc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_kdc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_kdc " "Info: Found entity 1: cmpr_kdc" {  } { { "db/cmpr_kdc.tdf" "" { Text "T:/V6aurora_3125M_156M/db/cmpr_kdc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 0 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Warning: Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "PLL " "Warning: Synthesized away the following PLL node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\|wire_pll1_clk\[0\] " "Warning (14320): Synthesized away node \"PLL_LA:LA_PLL\|altpll:altpll_component\|PLL_LA_altpll:auto_generated\|wire_pll1_clk\[0\]\"" {  } { { "db/pll_la_altpll.v" "" { Text "T:/V6aurora_3125M_156M/db/pll_la_altpll.v" 77 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/10.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } { "PLL_LA.vhd" "" { Text "T:/V6aurora_3125M_156M/PLL_LA.vhd" 135 0 0 } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 488 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1}  } {  } 0 0 "Synthesized away the following node(s):" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "aurora_8b10b_v5_2:aurora_module_i\|comb~synth " "Warning: Converted tri-state buffer \"aurora_8b10b_v5_2:aurora_module_i\|comb~synth\" feeding internal logic into a wire" {  } {  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "aurora_8b10b_v5_2:aurora_module_i\|comb~synth " "Warning: Converted tri-state buffer \"aurora_8b10b_v5_2:aurora_module_i\|comb~synth\" feeding internal logic into a wire" {  } {  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "aurora_8b10b_v5_2:aurora_module_i\|comb~synth " "Warning: Converted tri-state buffer \"aurora_8b10b_v5_2:aurora_module_i\|comb~synth\" feeding internal logic into a wire" {  } {  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "aurora_8b10b_v5_2:aurora_module_i\|comb~synth " "Warning: Converted tri-state buffer \"aurora_8b10b_v5_2:aurora_module_i\|comb~synth\" feeding internal logic into a wire" {  } {  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 -1}  } {  } 0 0 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DIS_TX_CLK GND " "Warning (13410): Pin \"DIS_TX_CLK\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 79 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "TXN GND " "Warning (13410): Pin \"TXN\" is stuck at GND" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 101 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Info: Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 0 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_1_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[15\] " "Info: Register \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i\|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i\|SRL16:ver_counter_1_i\|LPMSHIFTREG16:lpm_shiftreg16\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_signaltap:auto_signaltap_0 " "Info: Timing-Driven Synthesis is running on partition \"sld_signaltap:auto_signaltap_0\"" {  } {  } 0 0 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "IAMERGE_SLD_INSTANCE_WITH_FULL_CONNECTIONS" "auto_signaltap_0 39 " "Info: Succesfully connected in-system debug instance \"auto_signaltap_0\" to all 39 required data inputs, trigger inputs, acquisition clocks, and dynamic pins" {  } {  } 0 0 "Succesfully connected in-system debug instance \"%1!s!\" to all %2!d! required data inputs, trigger inputs, acquisition clocks, and dynamic pins" 0 0 "" 0 -1}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info: Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pcs0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pcs0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pma0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pma0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pcs0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pcs0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pma0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pma0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|ch_clk_div0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|ch_clk_div0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_pll0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_pll0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_cdr_pll0 " "Info: Adding node \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_cdr_pll0\"" {  } {  } 0 0 "Adding node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "RXN " "Warning (15610): No output dependent on input pin \"RXN\"" {  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 99 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1552 " "Info: Implemented 1552 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "1475 " "Info: Implemented 1475 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "37 " "Info: Implemented 37 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 40 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 40 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "519 " "Info: Peak virtual memory: 519 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 18 13:08:21 2011 " "Info: Processing ended: Fri Mar 18 13:08:21 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:41 " "Info: Elapsed time: 00:00:41" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Info: Total CPU time (on all processors): 00:00:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 18 13:08:21 2011 " "Info: Processing started: Fri Mar 18 13:08:21 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "aurora_8b10b_v5_2_example_design EP4SGX230KF40C2 " "Info: Selected device EP4SGX230KF40C2 for design \"aurora_8b10b_v5_2_example_design\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4SGX180KF40C2 " "Info: Device EP4SGX180KF40C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4SGX290KF40C2 " "Info: Device EP4SGX290KF40C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4SGX360KF40C2 " "Info: Device EP4SGX360KF40C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4SGX530KH40C2 " "Info: Device EP4SGX530KH40C2 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ W30 " "Info: Pin ~ALTERA_DATA0~ is reserved at location W30" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 21903 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Warning" "WFSAC_FSAC_COMPLEMENT_PIN_CREATED_GROUP" "3 " "Warning: Following 3 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins." { { "Warning" "WFSAC_FSAC_COMPLEMENT_PIN_CREATED" "TXP TXP(n) " "Warning: Pin \"TXP\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"TXP(n)\"" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { TXP } } } { "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TXP" } { 0 "TXP(n)" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 100 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TXP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 119 5147 6155 0} { 0 { 0 ""} 0 162 5147 6155 0}  }  } } { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { TXP(n) } } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TXP(n) } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"%2!s!\"" 0 0 "" 0 -1} { "Warning" "WFSAC_FSAC_COMPLEMENT_PIN_CREATED" "RXP RXP(n) " "Warning: Pin \"RXP\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"RXP(n)\"" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { RXP } } } { "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "RXP" } { 0 "RXP(n)" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 98 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RXP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 117 5147 6155 0} { 0 { 0 ""} 0 161 5147 6155 0}  }  } } { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { RXP(n) } } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RXP(n) } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"%2!s!\"" 0 0 "" 0 -1} { "Warning" "WFSAC_FSAC_COMPLEMENT_PIN_CREATED" "GTXQ4 GTXQ4(n) " "Warning: Pin \"GTXQ4\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"GTXQ4(n)\"" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { GTXQ4 } } } { "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GTXQ4" } { 0 "GTXQ4(n)" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 94 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GTXQ4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 116 5147 6155 0} { 0 { 0 ""} 0 160 5147 6155 0}  }  } } { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { GTXQ4(n) } } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GTXQ4(n) } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin \"%2!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins." 0 0 "" 0 -1}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "14 25 " "Critical Warning: No exact pin location assignment(s) for 14 pins of 25 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DIS_USER_CLK " "Info: Pin DIS_USER_CLK not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { DIS_USER_CLK } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 78 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DIS_USER_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 104 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "HARD_ERR " "Info: Pin HARD_ERR not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { HARD_ERR } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 83 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { HARD_ERR } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 109 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SOFT_ERR " "Info: Pin SOFT_ERR not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { SOFT_ERR } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 84 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SOFT_ERR } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 110 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FRAME_ERR " "Info: Pin FRAME_ERR not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { FRAME_ERR } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 85 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FRAME_ERR } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 111 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[7\] " "Info: Pin ERR_COUNT\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ERR_COUNT[7] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 96 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[6\] " "Info: Pin ERR_COUNT\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ERR_COUNT[6] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 97 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[5\] " "Info: Pin ERR_COUNT\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ERR_COUNT[5] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 98 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[4\] " "Info: Pin ERR_COUNT\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ERR_COUNT[4] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 99 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[3\] " "Info: Pin ERR_COUNT\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ERR_COUNT[3] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 100 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[2\] " "Info: Pin ERR_COUNT\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ERR_COUNT[2] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 101 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[1\] " "Info: Pin ERR_COUNT\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ERR_COUNT[1] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 102 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ERR_COUNT\[0\] " "Info: Pin ERR_COUNT\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { ERR_COUNT[0] } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 86 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ERR_COUNT[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 103 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RXN " "Info: Pin RXN not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { RXN } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 99 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RXN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 118 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TXN " "Info: Pin TXN not assigned to an exact location on the device" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { TXN } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 101 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TXN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 120 5147 6155 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Critical Warning" "WFHSSI_FHSSI_CMU_MUST_HAVE_RECONFIG" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 RX offset cancellation " "Critical Warning: GXB Central Management Unit (CMU) aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 is not connected to a GXB reconfig logic block, but the RX offset cancellation feature requires that it must be" {  } {  } 1 0 "GXB Central Management Unit (CMU) %1!s! is not connected to a GXB reconfig logic block, but the %2!s! feature requires that it must be" 0 0 "" 0 -1}
{ "Info" "IFHSSI_FHSSI_PLL_COMP_CAL_CLK_IN_PERIOD_RANGE_INFO" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0 10.0 MHz 125.0 MHz " "Info: Clock input frequency of GXB Calibration block atom \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0\" must be in the frequency range of 10.0 MHz to 125.0 MHz" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1517 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|cal_blk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 4380 5147 6155 0}  }  } }  } 0 0 "Clock input frequency of GXB Calibration block atom \"%1!s!\" must be in the frequency range of %2!s! to %3!s!" 0 0 "" 0 -1}
{ "Info" "IFHSSI_FHSSI_MERGING_COMPLETE" "" "Info: GXB Quad Optimizer operation is complete" {  } {  } 0 0 "GXB Quad Optimizer operation is complete" 0 0 "" 0 -1}
{ "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Current transceiver placement " "Info: Current transceiver placement" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "QUAD_SIDE_LEFT " "Info: QUAD_SIDE_LEFT" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PCIEHIP_X0_Y3_N134            " "Info: PCIEHIP_X0_Y3_N134           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CALIBRATIONBLOCK_X0_Y2_N135  aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0 " "Info: CALIBRATIONBLOCK_X0_Y2_N135  aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1517 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|cal_blk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 4380 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CALIBRATIONBLOCK_X0_Y89_N135   " "Info: CALIBRATIONBLOCK_X0_Y89_N135  " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "ATX LCTANK_X0_Y25_N135 " "Info: ATX LCTANK_X0_Y25_N135" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X0_Y25_N137               " "Info: CMU_X0_Y25_N137              " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y25_N135           " "Info: HSSIPLL_X0_Y25_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y25_N136      " "Info: CLOCKDIVIDER_X0_Y25_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QL0 " "Info: Atoms placed to IOBANK_QL0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X0_Y10_N139               " "Info: CMU_X0_Y10_N139              " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 0 " "Info: Regular Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AU38                      " "Info: PIN_AU38                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y4_N137              " "Info: RXPMA_X0_Y4_N137             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y4_N139              " "Info: RXPCS_X0_Y4_N139             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y4_N135            " "Info: HSSIPLL_X0_Y4_N135           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y4_N136       " "Info: CLOCKDIVIDER_X0_Y4_N136      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y4_N140              " "Info: TXPCS_X0_Y4_N140             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y4_N138              " "Info: TXPMA_X0_Y4_N138             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AT36                      " "Info: PIN_AT36                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 1 " "Info: Regular Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AR38                      " "Info: PIN_AR38                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y7_N137              " "Info: RXPMA_X0_Y7_N137             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y7_N139              " "Info: RXPCS_X0_Y7_N139             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y7_N135            " "Info: HSSIPLL_X0_Y7_N135           " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y7_N136       " "Info: CLOCKDIVIDER_X0_Y7_N136      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y7_N140              " "Info: TXPCS_X0_Y7_N140             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y7_N138              " "Info: TXPMA_X0_Y7_N138             " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AP36                      " "Info: PIN_AP36                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 0 " "Info: Central Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AN38                      " "Info: PIN_AN38                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y10_N137             " "Info: RXPMA_X0_Y10_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y10_N135           " "Info: HSSIPLL_X0_Y10_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y10_N136      " "Info: CLOCKDIVIDER_X0_Y10_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y10_N138             " "Info: TXPMA_X0_Y10_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AM36                      " "Info: PIN_AM36                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 1 " "Info: Central Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AL38                      " "Info: PIN_AL38                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y13_N137             " "Info: RXPMA_X0_Y13_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y13_N135           " "Info: HSSIPLL_X0_Y13_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y13_N136      " "Info: CLOCKDIVIDER_X0_Y13_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y13_N138             " "Info: TXPMA_X0_Y13_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AK36                      " "Info: PIN_AK36                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 2 " "Info: Regular Channel 2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AJ38                      " "Info: PIN_AJ38                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y16_N137             " "Info: RXPMA_X0_Y16_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y16_N139             " "Info: RXPCS_X0_Y16_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y16_N135           " "Info: HSSIPLL_X0_Y16_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y16_N136      " "Info: CLOCKDIVIDER_X0_Y16_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y16_N140             " "Info: TXPCS_X0_Y16_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y16_N138             " "Info: TXPMA_X0_Y16_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AH36                      " "Info: PIN_AH36                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 3 " "Info: Regular Channel 3" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AG38                      " "Info: PIN_AG38                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y19_N137             " "Info: RXPMA_X0_Y19_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y19_N139             " "Info: RXPCS_X0_Y19_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y19_N135           " "Info: HSSIPLL_X0_Y19_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y19_N136      " "Info: CLOCKDIVIDER_X0_Y19_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y19_N140             " "Info: TXPCS_X0_Y19_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y19_N138             " "Info: TXPMA_X0_Y19_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AF36                      " "Info: PIN_AF36                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QL1 " "Info: Atoms placed to IOBANK_QL1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X0_Y41_N139              aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 " "Info: CMU_X0_Y41_N139              aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1575 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_cent_unit0_dprioout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 4396 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 0 " "Info: Regular Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AE38                     RXP " "Info: PIN_AE38                     RXP" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { RXP } } } { "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "RXP" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 98 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RXP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 117 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y35_N137            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pma0 " "Info: RXPMA_X0_Y35_N137            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pma0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1867 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|rx_pma_dataout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3583 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y35_N139            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pcs0 " "Info: RXPCS_X0_Y35_N139            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|receive_pcs0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1725 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y35_N135          aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_cdr_pll0 " "Info: HSSIPLL_X0_Y35_N135          aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_cdr_pll0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1660 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|pll_ch_dataout_wire[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 2547 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y35_N136     aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|ch_clk_div0 " "Info: CLOCKDIVIDER_X0_Y35_N136     aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|ch_clk_div0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1524 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|ch_clk_div0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 4385 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y35_N140            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pcs0 " "Info: TXPCS_X0_Y35_N140            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pcs0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1932 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_transmit_pma0_datain[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3909 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y35_N138            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pma0 " "Info: TXPMA_X0_Y35_N138            aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|transmit_pma0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 2012 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_transmit_pma0_dataout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 18346 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AD36                     TXP " "Info: PIN_AD36                     TXP" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { TXP } } } { "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TXP" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 100 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TXP } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 119 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 1 " "Info: Regular Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AC38                      " "Info: PIN_AC38                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y38_N137             " "Info: RXPMA_X0_Y38_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y38_N139             " "Info: RXPCS_X0_Y38_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y38_N135           " "Info: HSSIPLL_X0_Y38_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y38_N136      " "Info: CLOCKDIVIDER_X0_Y38_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y38_N140             " "Info: TXPCS_X0_Y38_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y38_N138             " "Info: TXPMA_X0_Y38_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AB36                      " "Info: PIN_AB36                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 0 " "Info: Central Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AA38                      " "Info: PIN_AA38                     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y41_N137             " "Info: RXPMA_X0_Y41_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y41_N135          aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_pll0 " "Info: HSSIPLL_X0_Y41_N135          aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_pll0" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1692 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|tx_pll0~DATAOUT0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 17950 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y41_N136      " "Info: CLOCKDIVIDER_X0_Y41_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y41_N138             " "Info: TXPMA_X0_Y41_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_Y36                       " "Info: PIN_Y36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 1 " "Info: Central Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_W38                       " "Info: PIN_W38                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y44_N137             " "Info: RXPMA_X0_Y44_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y44_N135           " "Info: HSSIPLL_X0_Y44_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y44_N136      " "Info: CLOCKDIVIDER_X0_Y44_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y44_N138             " "Info: TXPMA_X0_Y44_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_V36                       " "Info: PIN_V36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 2 " "Info: Regular Channel 2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_U38                       " "Info: PIN_U38                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y47_N137             " "Info: RXPMA_X0_Y47_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y47_N139             " "Info: RXPCS_X0_Y47_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y47_N135           " "Info: HSSIPLL_X0_Y47_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y47_N136      " "Info: CLOCKDIVIDER_X0_Y47_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y47_N140             " "Info: TXPCS_X0_Y47_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y47_N138             " "Info: TXPMA_X0_Y47_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_T36                       " "Info: PIN_T36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 3 " "Info: Regular Channel 3" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_R38                       " "Info: PIN_R38                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y50_N137             " "Info: RXPMA_X0_Y50_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y50_N139             " "Info: RXPCS_X0_Y50_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y50_N135           " "Info: HSSIPLL_X0_Y50_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y50_N136      " "Info: CLOCKDIVIDER_X0_Y50_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y50_N140             " "Info: TXPCS_X0_Y50_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y50_N138             " "Info: TXPMA_X0_Y50_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_P36                       " "Info: PIN_P36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QL2 " "Info: Atoms placed to IOBANK_QL2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X0_Y69_N139               " "Info: CMU_X0_Y69_N139              " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 0 " "Info: Regular Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_N38                       " "Info: PIN_N38                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y63_N137             " "Info: RXPMA_X0_Y63_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y63_N139             " "Info: RXPCS_X0_Y63_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y63_N135           " "Info: HSSIPLL_X0_Y63_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y63_N136      " "Info: CLOCKDIVIDER_X0_Y63_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y63_N140             " "Info: TXPCS_X0_Y63_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y63_N138             " "Info: TXPMA_X0_Y63_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_M36                       " "Info: PIN_M36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 1 " "Info: Regular Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_L38                       " "Info: PIN_L38                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y66_N137             " "Info: RXPMA_X0_Y66_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y66_N139             " "Info: RXPCS_X0_Y66_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y66_N135           " "Info: HSSIPLL_X0_Y66_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y66_N136      " "Info: CLOCKDIVIDER_X0_Y66_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y66_N140             " "Info: TXPCS_X0_Y66_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y66_N138             " "Info: TXPMA_X0_Y66_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_K36                       " "Info: PIN_K36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 0 " "Info: Central Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_J38                       " "Info: PIN_J38                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y69_N137             " "Info: RXPMA_X0_Y69_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y69_N135           " "Info: HSSIPLL_X0_Y69_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y69_N136      " "Info: CLOCKDIVIDER_X0_Y69_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y69_N138             " "Info: TXPMA_X0_Y69_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_H36                       " "Info: PIN_H36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 1 " "Info: Central Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_G38                      GTXQ4 " "Info: PIN_G38                      GTXQ4" {  } { { "c:/altera/10.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/10.1/quartus/bin64/pin_planner.ppl" { GTXQ4 } } } { "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/10.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GTXQ4" } } } } { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 94 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GTXQ4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 116 5147 6155 0}  }  } }  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y72_N137             " "Info: RXPMA_X0_Y72_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y72_N135           " "Info: HSSIPLL_X0_Y72_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y72_N136      " "Info: CLOCKDIVIDER_X0_Y72_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y72_N138             " "Info: TXPMA_X0_Y72_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_F36                       " "Info: PIN_F36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 2 " "Info: Regular Channel 2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_E38                       " "Info: PIN_E38                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y75_N137             " "Info: RXPMA_X0_Y75_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y75_N139             " "Info: RXPCS_X0_Y75_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y75_N135           " "Info: HSSIPLL_X0_Y75_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y75_N136      " "Info: CLOCKDIVIDER_X0_Y75_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y75_N140             " "Info: TXPCS_X0_Y75_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y75_N138             " "Info: TXPMA_X0_Y75_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_D36                       " "Info: PIN_D36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 3 " "Info: Regular Channel 3" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_C38                       " "Info: PIN_C38                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X0_Y78_N137             " "Info: RXPMA_X0_Y78_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X0_Y78_N139             " "Info: RXPCS_X0_Y78_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X0_Y78_N135           " "Info: HSSIPLL_X0_Y78_N135          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X0_Y78_N136      " "Info: CLOCKDIVIDER_X0_Y78_N136     " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X0_Y78_N140             " "Info: TXPCS_X0_Y78_N140            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X0_Y78_N138             " "Info: TXPMA_X0_Y78_N138            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_B36                       " "Info: PIN_B36                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "QUAD_SIDE_RIGHT " "Info: QUAD_SIDE_RIGHT" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PCIEHIP_X119_Y3_N134          " "Info: PCIEHIP_X119_Y3_N134         " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CALIBRATIONBLOCK_X119_Y2_N135   " "Info: CALIBRATIONBLOCK_X119_Y2_N135  " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CALIBRATIONBLOCK_X119_Y89_N135   " "Info: CALIBRATIONBLOCK_X119_Y89_N135  " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "ATX LCTANK_X119_Y25_N135 " "Info: ATX LCTANK_X119_Y25_N135" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X119_Y25_N137             " "Info: CMU_X119_Y25_N137            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y25_N135         " "Info: HSSIPLL_X119_Y25_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y25_N136    " "Info: CLOCKDIVIDER_X119_Y25_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QR0 " "Info: Atoms placed to IOBANK_QR0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X119_Y10_N139             " "Info: CMU_X119_Y10_N139            " {  } { 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0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 0 " "Info: Central Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AN2                       " "Info: PIN_AN2                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y10_N137           " "Info: RXPMA_X119_Y10_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y10_N135         " "Info: HSSIPLL_X119_Y10_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y10_N136    " "Info: CLOCKDIVIDER_X119_Y10_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y10_N138           " "Info: TXPMA_X119_Y10_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AM4                       " "Info: PIN_AM4                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 1 " "Info: Central Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AL2                       " "Info: PIN_AL2                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y13_N137           " "Info: RXPMA_X119_Y13_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y13_N135         " "Info: HSSIPLL_X119_Y13_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y13_N136    " "Info: CLOCKDIVIDER_X119_Y13_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y13_N138           " "Info: TXPMA_X119_Y13_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AK4                       " "Info: PIN_AK4                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 2 " "Info: Regular Channel 2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AJ2                       " "Info: PIN_AJ2                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y16_N137           " "Info: RXPMA_X119_Y16_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y16_N139           " "Info: RXPCS_X119_Y16_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y16_N135         " "Info: HSSIPLL_X119_Y16_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y16_N136    " "Info: CLOCKDIVIDER_X119_Y16_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y16_N140           " "Info: TXPCS_X119_Y16_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y16_N138           " "Info: TXPMA_X119_Y16_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AH4                       " "Info: PIN_AH4                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 3 " "Info: Regular Channel 3" { { "Info" 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"Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y19_N138           " "Info: TXPMA_X119_Y19_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AF4                       " "Info: PIN_AF4                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QR1 " "Info: Atoms placed to IOBANK_QR1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X119_Y41_N139             " "Info: CMU_X119_Y41_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 0 " "Info: Regular Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AE2                       " "Info: PIN_AE2                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y35_N137           " "Info: RXPMA_X119_Y35_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y35_N139           " "Info: RXPCS_X119_Y35_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y35_N135         " "Info: HSSIPLL_X119_Y35_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y35_N136    " "Info: CLOCKDIVIDER_X119_Y35_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y35_N140           " "Info: TXPCS_X119_Y35_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y35_N138           " "Info: TXPMA_X119_Y35_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AD4                       " "Info: PIN_AD4                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 1 " "Info: Regular Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AC2                       " "Info: PIN_AC2                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y38_N137           " "Info: RXPMA_X119_Y38_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y38_N139           " "Info: RXPCS_X119_Y38_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y38_N135         " "Info: HSSIPLL_X119_Y38_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y38_N136    " "Info: CLOCKDIVIDER_X119_Y38_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y38_N140           " "Info: TXPCS_X119_Y38_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y38_N138           " "Info: TXPMA_X119_Y38_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AB4                       " "Info: PIN_AB4                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 0 " "Info: Central Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_AA2                       " "Info: PIN_AA2                      " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y41_N137           " "Info: RXPMA_X119_Y41_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y41_N135         " "Info: HSSIPLL_X119_Y41_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y41_N136    " "Info: CLOCKDIVIDER_X119_Y41_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y41_N138           " "Info: TXPMA_X119_Y41_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_Y4                        " "Info: PIN_Y4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 1 " "Info: Central Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_W2                        " "Info: PIN_W2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y44_N137           " "Info: RXPMA_X119_Y44_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y44_N135         " "Info: HSSIPLL_X119_Y44_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y44_N136    " "Info: CLOCKDIVIDER_X119_Y44_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y44_N138           " "Info: TXPMA_X119_Y44_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_V4                        " "Info: PIN_V4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 2 " "Info: Regular Channel 2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_U2                        " "Info: PIN_U2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y47_N137           " "Info: RXPMA_X119_Y47_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y47_N139           " "Info: RXPCS_X119_Y47_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y47_N135         " "Info: HSSIPLL_X119_Y47_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y47_N136    " "Info: CLOCKDIVIDER_X119_Y47_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y47_N140           " "Info: TXPCS_X119_Y47_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y47_N138           " "Info: TXPMA_X119_Y47_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_T4                        " "Info: PIN_T4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 3 " "Info: Regular Channel 3" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_R2                        " "Info: PIN_R2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y50_N137           " "Info: RXPMA_X119_Y50_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y50_N139           " "Info: RXPCS_X119_Y50_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y50_N135         " "Info: HSSIPLL_X119_Y50_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y50_N136    " "Info: CLOCKDIVIDER_X119_Y50_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y50_N140           " "Info: TXPCS_X119_Y50_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y50_N138           " "Info: TXPMA_X119_Y50_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_P4                        " "Info: PIN_P4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Atoms placed to IOBANK_QR2 " "Info: Atoms placed to IOBANK_QR2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CMU_X119_Y69_N139             " "Info: CMU_X119_Y69_N139            " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 0 " "Info: Regular Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_N2                        " "Info: PIN_N2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y63_N137           " "Info: RXPMA_X119_Y63_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y63_N139           " "Info: RXPCS_X119_Y63_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y63_N135         " "Info: HSSIPLL_X119_Y63_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y63_N136    " "Info: CLOCKDIVIDER_X119_Y63_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y63_N140           " "Info: TXPCS_X119_Y63_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y63_N138           " "Info: TXPMA_X119_Y63_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_M4                        " "Info: PIN_M4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 1 " "Info: Regular Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_L2                        " "Info: PIN_L2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y66_N137           " "Info: RXPMA_X119_Y66_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y66_N139           " "Info: RXPCS_X119_Y66_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y66_N135         " "Info: HSSIPLL_X119_Y66_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y66_N136    " "Info: CLOCKDIVIDER_X119_Y66_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y66_N140           " "Info: TXPCS_X119_Y66_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y66_N138           " "Info: TXPMA_X119_Y66_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_K4                        " "Info: PIN_K4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 0 " "Info: Central Channel 0" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_J2                        " "Info: PIN_J2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y69_N137           " "Info: RXPMA_X119_Y69_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y69_N135         " "Info: HSSIPLL_X119_Y69_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y69_N136    " "Info: CLOCKDIVIDER_X119_Y69_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y69_N138           " "Info: TXPMA_X119_Y69_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_H4                        " "Info: PIN_H4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Central Channel 1 " "Info: Central Channel 1" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_G2                        " "Info: PIN_G2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y72_N137           " "Info: RXPMA_X119_Y72_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y72_N135         " "Info: HSSIPLL_X119_Y72_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y72_N136    " "Info: CLOCKDIVIDER_X119_Y72_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y72_N138           " "Info: TXPMA_X119_Y72_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_F4                        " "Info: PIN_F4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 2 " "Info: Regular Channel 2" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_E2                        " "Info: PIN_E2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y75_N137           " "Info: RXPMA_X119_Y75_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y75_N139           " "Info: RXPCS_X119_Y75_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y75_N135         " "Info: HSSIPLL_X119_Y75_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y75_N136    " "Info: CLOCKDIVIDER_X119_Y75_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y75_N140           " "Info: TXPCS_X119_Y75_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y75_N138           " "Info: TXPMA_X119_Y75_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_D4                        " "Info: PIN_D4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "Regular Channel 3 " "Info: Regular Channel 3" { { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_C2                        " "Info: PIN_C2                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPMA_X119_Y78_N137           " "Info: RXPMA_X119_Y78_N137          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "RXPCS_X119_Y78_N139           " "Info: RXPCS_X119_Y78_N139          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "HSSIPLL_X119_Y78_N135         " "Info: HSSIPLL_X119_Y78_N135        " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "CLOCKDIVIDER_X119_Y78_N136    " "Info: CLOCKDIVIDER_X119_Y78_N136   " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPCS_X119_Y78_N140           " "Info: TXPCS_X119_Y78_N140          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "TXPMA_X119_Y78_N138           " "Info: TXPMA_X119_Y78_N138          " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IFHSSI_FHSSI_FINAL_ATOM_AND_BIN_PLACEMENT_MESSAGE" "PIN_B4                        " "Info: PIN_B4                       " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "aurora_8b10b_v5_2_example_design.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'aurora_8b10b_v5_2_example_design.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "INIT_CLK " "Warning: Node: INIT_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "Info: No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 0 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 0 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Info: Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " "Info:  100.000 altera_reserved_tck" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\] (placed in RXPCS_X0_Y35_N139) " "Info: Automatically promoted node aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\] (placed in RXPCS_X0_Y35_N139)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1725 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_receive_pcs0_dataout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\] (placed in TXPCS_X0_Y35_N140) " "Info: Automatically promoted node aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\] (placed in TXPCS_X0_Y35_N140)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Periphery Clock CLKCTRL_X0_Y34_N127 " "Info: Automatically promoted destinations to use location or clock signal Periphery Clock CLKCTRL_X0_Y34_N127" { { "Info" "IFSAC_FSAC_ASSIGN_REGION_TO_SIGNAL_FANOUTS" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\] Periphery Clock 0 25 59 48 " "Info: Assigned fan-out of node aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\] to Periphery Clock region from (0, 25) to (59, 48)" {  } {  } 0 0 "Assigned fan-out of node %1!s! to %2!s! region from (%3!d!, %4!d!) to (%5!d!, %6!d!)" 0 0 "" 0 -1}  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1932 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|wire_transmit_pma0_datain[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3909 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "INIT_CLK~input (placed in PIN AR22 (CLK4p, DIFFIO_RX_B24p, DIFFOUT_B48p)) " "Info: Automatically promoted node INIT_CLK~input (placed in PIN AR22 (CLK4p, DIFFIO_RX_B24p, DIFFOUT_B48p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_example_design.vhd" 89 0 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { INIT_CLK~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 21787 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 19355 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|status_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|status_buf_read_reset" {  } { { "sld_buffer_manager.vhd" "" { Text "c:/altera/10.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 629 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|status_buf_read_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 19855 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "sld_buffer_manager.vhd" "" { Text "c:/altera/10.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 627 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 19851 5147 6155 0}  }  } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1}  } { { "sld_signaltap.vhd" "" { Text "c:/altera/10.1/quartus/libraries/megafunctions/sld_signaltap.vhd" 831 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 20357 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i\|GT_RESET_OUT  " "Info: Automatically promoted node aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i\|GT_RESET_OUT " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G12 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G12" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" "" { Text "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2/example_design/aurora_8b10b_v5_2_reset_logic.vhd" 77 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i|GT_RESET_OUT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 177 5147 6155 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "14 unused 2.5V 1 13 0 " "Info: Number of I/O pins in group: 14 (unused VREF, 2.5V VCCIO, 1 input, 13 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "Info: I/O standards used: 2.5 V." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 5 48 " "Info: I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1C does not use undetermined 1 41 " "Info: I/O bank number 1C does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  41 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2C does not use undetermined 0 42 " "Info: I/O bank number 2C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2A does not use 2.5V 2 46 " "Info: I/O bank number 2A does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  46 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 3 37 " "Info: I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used --  37 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3B does not use undetermined 0 24 " "Info: I/O bank number 3B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3C does not use undetermined 1 31 " "Info: I/O bank number 3C does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  31 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4C does not use undetermined 0 32 " "Info: I/O bank number 4C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  32 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4B does not use undetermined 0 24 " "Info: I/O bank number 4B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4A does not use undetermined 0 40 " "Info: I/O bank number 4A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5A does not use undetermined 0 48 " "Info: I/O bank number 5A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5C does not use undetermined 0 42 " "Info: I/O bank number 5C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6C does not use undetermined 0 42 " "Info: I/O bank number 6C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6A does not use undetermined 0 48 " "Info: I/O bank number 6A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7A does not use undetermined 0 40 " "Info: I/O bank number 7A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7B does not use undetermined 0 24 " "Info: I/O bank number 7B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7C does not use undetermined 0 32 " "Info: I/O bank number 7C does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  32 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8C does not use 2.5V 2 30 " "Info: I/O bank number 8C does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8B does not use undetermined 0 24 " "Info: I/O bank number 8B does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 40 " "Info: I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL11 does not use undetermined 0 0 " "Info: I/O bank number QL11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL2 does not use undetermined 2 0 " "Info: I/O bank number QL2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL1 does not use undetermined 4 0 " "Info: I/O bank number QL1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "Info: I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL10 does not use undetermined 0 0 " "Info: I/O bank number QL10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR10 does not use undetermined 0 0 " "Info: I/O bank number QR10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR0 does not use undetermined 0 0 " "Info: I/O bank number QR0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR1 does not use undetermined 0 0 " "Info: I/O bank number QR1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR2 does not use undetermined 0 0 " "Info: I/O bank number QR2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QR11 does not use undetermined 0 0 " "Info: I/O bank number QR11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Critical Warning" "WFHSSI_FHSSI_CMU_MUST_HAVE_RECONFIG" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 RX offset cancellation " "Critical Warning: GXB Central Management Unit (CMU) aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 is not connected to a GXB reconfig logic block, but the RX offset cancellation feature requires that it must be" {  } {  } 1 0 "GXB Central Management Unit (CMU) %1!s! is not connected to a GXB reconfig logic block, but the %2!s! feature requires that it must be" 0 0 "" 0 -1}
{ "Info" "IFHSSI_FHSSI_PLL_COMP_CAL_CLK_IN_PERIOD_RANGE_INFO" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0 10.0 MHz 125.0 MHz " "Info: Clock input frequency of GXB Calibration block atom \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cal_blk0\" must be in the frequency range of 10.0 MHz to 125.0 MHz" {  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 1517 -1 0 } } { "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/10.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0|cal_blk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 4380 5147 6155 0}  }  } }  } 0 0 "Clock input frequency of GXB Calibration block atom \"%1!s!\" must be in the frequency range of %2!s! to %3!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WFHSSI_FHSSI_CMU_MUST_HAVE_RECONFIG" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 DPRIO Reconfiguration " "Critical Warning: GXB Central Management Unit (CMU) aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|cent_unit0 is not connected to a GXB reconfig logic block, but the DPRIO Reconfiguration feature requires that it must be" {  } {  } 1 0 "GXB Central Management Unit (CMU) %1!s! is not connected to a GXB reconfig logic block, but the %2!s! feature requires that it must be" 0 0 "" 0 -1}
{ "Critical Warning" "" "" "Critical Warning: Register-to-register paths between different clock domains is not recommended if one of the clocks is from GXB transmitter channel." { { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[0\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[0\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[1\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[1\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[2\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[2\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[2\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[3\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[3\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[2\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[3\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[4\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[4\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[3\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[5\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[5\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[6\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[6\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[7\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[7\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[8\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[8\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[8\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[9\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[9\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[8\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[10\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[10\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[10\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[11\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[11\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[10\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[12\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[12\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[13\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[13\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[2\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[14\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[14\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[2\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[3\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[15\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[15\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[3\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[16\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[16\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[17\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[17\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[18\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[18\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[19\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[19\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[8\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[20\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[20\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[8\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[9\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[21\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[21\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[9\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[10\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[22\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:info_data_shift_out\|dffs\[22\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:last_trigger_address_var\[10\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|buffer_write_enable_delayed from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[1\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[1\] from clock: altera_reserved_tck" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|buffer_write_enable_delayed from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[0\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[0\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[0\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[0\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[1\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[1\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[1\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[1\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:is_buffer_wrapped from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:is_buffer_wrapped from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[2\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[2\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[2\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[2\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[2\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[2\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[2\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[2\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[3\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[3\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[3\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[3\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[3\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[3\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[3\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[3\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[4\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[4\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[4\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[4\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[5\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[5\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[5\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[5\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[6\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[6\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[6\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[6\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[7\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[7\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[7\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[7\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[8\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[8\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[8\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[8\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[8\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[8\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[8\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[8\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[9\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[9\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[9\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[9\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[9\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[9\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[9\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[9\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[10\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[10\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[10\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[10\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[10\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[10\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[10\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[10\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[11\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[11\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[11\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[11\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[11\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[11\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[11\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[11\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[12\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[12\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[12\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[12\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[12\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[12\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[12\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[12\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[13\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[13\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[13\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[13\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[13\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[13\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[13\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[13\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[14\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[14\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[14\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[14\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[14\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[14\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[14\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[14\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[15\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[15\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[15\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[15\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[15\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[15\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[15\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[15\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[16\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[16\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[16\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[16\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[16\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[16\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[16\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[16\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[17\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[17\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[17\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[17\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[17\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[17\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[17\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[17\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[18\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[18\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[18\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[18\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[18\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[18\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[18\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[18\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[19\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[19\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[19\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[19\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[19\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[19\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[19\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[19\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[20\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[20\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[20\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[20\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[20\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[20\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[20\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[20\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[21\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[21\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[21\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[21\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[21\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[21\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[21\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[21\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[22\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[22\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[22\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[1\]\[22\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[22\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[22\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|xq\[22\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem\|cells\[0\]\[22\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:collecting_post_data_var from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[0\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[0\] from clock: altera_reserved_tck" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:collecting_post_data_var from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|run from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[0\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[0\] from clock: altera_reserved_tck" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[1\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[1\] from clock: altera_reserved_tck" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|run from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:done from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[1\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[1\] from clock: altera_reserved_tck" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[2\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|\\buffer_manager:done from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|current_segment_delayed\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[4\] from clock: altera_reserved_tck" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|lpm_shiftreg:status_register\|dffs\[4\] from clock: altera_reserved_tck" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|current_segment_delayed\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Register-to-register paths between different clock domains is not recommended if one of the clocks is from GXB transmitter channel." 0 0 "" 0 -1}
{ "Critical Warning" "" "" "Critical Warning: Register-to-register paths between different clock domains is not recommended if one of the clocks is from GXB receiver channel." { { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_phfifooverflow from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_phfifooverflow from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_phfifounderflow from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_phfifounderflow from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_syncstatus\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|polarity_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|polarity_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|begin_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|begin_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|realign_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|realign_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_syncstatus\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_syncstatus\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|polarity_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|polarity_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|begin_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|begin_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|realign_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|realign_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_syncstatus\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_patterndetect\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|RX_CHAR_IS_COMMA_R\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|RX_CHAR_IS_COMMA_R\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[5\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_patterndetect\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_patterndetect\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|RX_CHAR_IS_COMMA_R\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|RX_CHAR_IS_COMMA_R\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[4\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_patterndetect\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_ctrldetect\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|word_aligned_control_bits_r\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|word_aligned_control_bits_r\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|word_aligned_control_bits_r\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|word_aligned_control_bits_r\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[7\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_ctrldetect\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_ctrldetect\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|word_aligned_control_bits_r\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|word_aligned_control_bits_r\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|word_aligned_control_bits_r\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|word_aligned_control_bits_r\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[6\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_ctrldetect\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_errdetect\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|soft_err_r\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|soft_err_r\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_errdetect\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_errdetect\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|soft_err_r\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|soft_err_r\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_errdetect\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_disperr\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|soft_err_r\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|soft_err_r\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_disperr\[0\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_disperr\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" { { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|soft_err_r\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|soft_err_r\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1} { "Critical Warning" "" "" "Critical Warning: Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" {  } {  } 1 0 "Destination Node: aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Source Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_disperr\[1\] from clock: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|rx_coreclk_in\[0\]" 0 0 "" 0 -1}  } {  } 1 0 "Register-to-register paths between different clock domains is not recommended if one of the clocks is from GXB receiver channel." 0 0 "" 0 -1}
{ "Critical Warning" "WDRC_NO_SYNZER_IN_ASYNC_CLK_DOMAIN_RX" "Data bits are not synchronized when transferred between asynchronous clock domains and one of the blocks is RX 2 0 " "Critical Warning: (High) Data bits are not synchronized when transferred between asynchronous clock domains and one of the blocks is RX. (Value defined:2). Found 0 asynchronous clock domain interface structure(s) related to this rule." { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_phfifooverflow " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_phfifooverflow\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_phfifounderflow " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_phfifounderflow\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_syncstatus\[0\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_syncstatus\[0\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 160 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_syncstatus\[1\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_syncstatus\[1\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i\|hard_err_flop_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 160 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_patterndetect\[0\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_patterndetect\[0\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|RX_CHAR_IS_COMMA_R\[0\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|RX_CHAR_IS_COMMA_R\[0\]\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 154 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_patterndetect\[1\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_patterndetect\[1\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|RX_CHAR_IS_COMMA_R\[1\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|RX_CHAR_IS_COMMA_R\[1\]\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 154 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_ctrldetect\[0\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_ctrldetect\[0\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 148 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_ctrldetect\[1\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_ctrldetect\[1\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i\|left_aligned_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 148 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_errdetect\[0\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_errdetect\[0\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 152 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_errdetect\[1\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_errdetect\[1\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 152 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_disperr\[0\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_disperr\[0\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 150 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_disperr\[1\] " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|wire_receive_pcs0_disperr\[1\]\"" { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r " "Critical Warning: Node  \"aurora_8b10b_v5_2:aurora_module_i\|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i\|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i\|reset_count_r\"" {  } {  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } { { "MGT.vhd" "" { Text "T:/V6aurora_3125M_156M/MGT.vhd" 150 -1 0 } } { "temporary_test_loc" "" { Generic "T:/V6aurora_3125M_156M/" { { 0 { 0 ""} 0 3155 5147 6155 0}  }  } }  } 1 0 "Node %1!s! \"%2!s!\"" 0 0 "" 0 -1}  } {  } 1 0 "(High) %1!s!. (Value defined:%2!d!). Found %3!d! asynchronous clock domain interface structure(s) related to this rule." 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:08 " "Info: Fitter preparation operations ending: elapsed time is 00:00:08" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Info: Fitter placement operations ending: elapsed time is 00:00:07" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X24_Y36 X35_Y47 " "Info: Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X24_Y36 to location X35_Y47" {  } {  } 0 0 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "T:/V6aurora_3125M_156M/aurora_8b10b_v5_2_example_design.fit.smsg " "Info: Generated suppressed messages file T:/V6aurora_3125M_156M/aurora_8b10b_v5_2_example_design.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 240 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Fitter was successful. 0 errors, 240 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1009 " "Info: Peak virtual memory: 1009 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 18 13:09:28 2011 " "Info: Processing ended: Fri Mar 18 13:09:28 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:01:07 " "Info: Elapsed time: 00:01:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:56 " "Info: Total CPU time (on all processors): 00:00:56" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 18 13:09:29 2011 " "Info: Processing started: Fri Mar 18 13:09:29 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version " "Info: Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 18 13:09:29 2011 " "Info: Processing started: Fri Mar 18 13:09:29 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design " "Info: Command: quartus_sta aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #4" {  } {  } 0 0 "qsta_default_script.tcl version: #4" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "aurora_8b10b_v5_2_example_design.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'aurora_8b10b_v5_2_example_design.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]~clkctrlFMAX_CAP_FF " "Warning: Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]~clkctrlFMAX_CAP_FF was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "INIT_CLK " "Warning: Node: INIT_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "Info: No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 0 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 900mV 85C Model" {  } {  } 0 0 "Analyzing Slow 900mV 85C Model" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.680 " "Info: Worst-case setup slack is 47.680" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   47.680         0.000 altera_reserved_tck  " "Info:    47.680         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.262 " "Info: Worst-case hold slack is 0.262" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.262         0.000 altera_reserved_tck  " "Info:     0.262         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.761 " "Info: Worst-case recovery slack is 48.761" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.761         0.000 altera_reserved_tck  " "Info:    48.761         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.480 " "Info: Worst-case removal slack is 0.480" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.480         0.000 altera_reserved_tck  " "Info:     0.480         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.308 " "Info: Worst-case minimum pulse width slack is 49.308" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.308         0.000 altera_reserved_tck  " "Info:    49.308         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 900mV 0C Model" {  } {  } 0 0 "Analyzing Slow 900mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]~clkctrlFMAX_CAP_FF " "Warning: Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]~clkctrlFMAX_CAP_FF was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "INIT_CLK " "Warning: Node: INIT_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.720 " "Info: Worst-case setup slack is 47.720" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   47.720         0.000 altera_reserved_tck  " "Info:    47.720         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.255 " "Info: Worst-case hold slack is 0.255" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.255         0.000 altera_reserved_tck  " "Info:     0.255         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.770 " "Info: Worst-case recovery slack is 48.770" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.770         0.000 altera_reserved_tck  " "Info:    48.770         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.467 " "Info: Worst-case removal slack is 0.467" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.467         0.000 altera_reserved_tck  " "Info:     0.467         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.264 " "Info: Worst-case minimum pulse width slack is 49.264" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.264         0.000 altera_reserved_tck  " "Info:    49.264         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Fast 900mV 0C Model" {  } {  } 0 0 "Analyzing Fast 900mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]~clkctrlFMAX_CAP_FF " "Warning: Node: aurora_8b10b_v5_2:aurora_module_i\|MGT_alt4gxb:MGT_0\|tx_coreclk_in\[0\]~clkctrlFMAX_CAP_FF was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "INIT_CLK " "Warning: Node: INIT_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.949 " "Info: Worst-case setup slack is 48.949" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.949         0.000 altera_reserved_tck  " "Info:    48.949         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.144 " "Info: Worst-case hold slack is 0.144" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.144         0.000 altera_reserved_tck  " "Info:     0.144         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 49.549 " "Info: Worst-case recovery slack is 49.549" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.549         0.000 altera_reserved_tck  " "Info:    49.549         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.272 " "Info: Worst-case removal slack is 0.272" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.272         0.000 altera_reserved_tck  " "Info:     0.272         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.132 " "Info: Worst-case minimum pulse width slack is 49.132" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.132         0.000 altera_reserved_tck  " "Info:    49.132         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 16 s Quartus II 64-Bit " "Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "588 " "Info: Peak virtual memory: 588 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 18 13:09:48 2011 " "Info: Processing ended: Fri Mar 18 13:09:48 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "886 " "Info: Peak virtual memory: 886 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 18 13:09:57 2011 " "Info: Processing ended: Fri Mar 18 13:09:57 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Info: Total CPU time (on all processors): 00:00:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 296 s " "Info: Quartus II Full Compilation was successful. 0 errors, 296 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
