library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.all;

entity MUXCY is
        port (

                O  : out std_logic;
                CI : in std_logic;
                DI : in std_logic;
                S  : in std_logic

             );
end MUXCY;

architecture MAPPED of MUXCY is

begin
	
	O <= '1' when ((S='0' and DI='1')or(S='1' and CI='1')) else '0';

end MAPPED;