library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FD is
	generic(INIT :  std_logic := '0');
    port (
            Q : out std_logic := INIT;
            C : in  std_logic;
            D : in  std_logic
         );	
end FD;

architecture MAIN of FD is

begin

	process (C) 
	begin 
		if (C' event and C = '1') then 
			Q <= D;
		end if; 
	end process;

end MAIN;