{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 23 01:47:18 2010 " "Info: Processing started: Thu Dec 23 01:47:18 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design " "Info: Command: quartus_sta aurora_8b10b_v5_2_example_design -c aurora_8b10b_v5_2_example_design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #2" {  } {  } 0 0 "qsta_default_script.tcl version: #2" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 0.9V " "Info: Core supply voltage is 0.9V" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Info: Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "Info: set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "Info: create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Warning: Overwriting existing clock: altera_reserved_tck" {  } {  } 0 0 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "aurora_8b10b_v5_2_example_design.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'aurora_8b10b_v5_2_example_design.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "INIT_CLK " "Warning: Node: INIT_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "Info: The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a0\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a0~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a0\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a0~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a12\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a12~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a12\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a12~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a16\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a16~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a16\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a16~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a20\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a20~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a20\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a20~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a24\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a24~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a24\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a24~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a28\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a28~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a28\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a28~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a32\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a32~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a32\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a32~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a36\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a36~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a36\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a36~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a40\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a40~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a40\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a40~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a44\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a44~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a44\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a44~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a48\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a48~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a48\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a48~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a4\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a4~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a4\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a4~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a52\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a52~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a52\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a52~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a56\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a56~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a56\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a56~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a60\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a60~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a60\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a60~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a64\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a64~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a64\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a64~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a68\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a68~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a68\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a68~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a72\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a72~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a72\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a72~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a8\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a8~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a8\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a8~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "" 0 -1}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "Info: No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 0 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_CLOCK_UNCERTAINTY_NUMBERS_ARE_PRELIMINARY" "Stratix IV " "Warning: Clock uncertainty characteristics of the Stratix IV device family are preliminary" {  } {  } 0 0 "Clock uncertainty characteristics of the %1!s! device family are preliminary" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: LA_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 6.400 " "Warning: Node: LA_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 6.400" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 900mV 85C Model" {  } {  } 0 0 "Analyzing Slow 900mV 85C Model" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.989 " "Info: Worst-case setup slack is 46.989" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   46.989         0.000 altera_reserved_tck  " "Info:    46.989         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.748 " "Info: Worst-case hold slack is 0.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.748         0.000 altera_reserved_tck  " "Info:     0.748         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.962 " "Info: Worst-case recovery slack is 48.962" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.962         0.000 altera_reserved_tck  " "Info:    48.962         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.077 " "Info: Worst-case removal slack is 1.077" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.077         0.000 altera_reserved_tck  " "Info:     1.077         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.297 " "Info: Worst-case minimum pulse width slack is 49.297" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.297         0.000 altera_reserved_tck  " "Info:    49.297         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Slow 900mV 0C Model" {  } {  } 0 0 "Analyzing Slow 900mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP4SGX230KF40C2 " "Warning: Timing characteristics of device EP4SGX230KF40C2 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "INIT_CLK " "Warning: Node: INIT_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "Info: The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a0\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a0~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a0\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a0~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a12\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a12~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a12\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a12~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a16\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a16~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a16\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a16~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a20\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a20~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a20\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a20~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a24\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a24~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a24\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a24~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a28\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a28~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a28\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a28~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a32\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a32~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a32\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a32~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a36\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a36~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a36\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a36~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a40\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a40~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a40\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a40~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a44\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a44~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a44\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a44~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a48\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a48~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a48\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a48~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a4\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a4~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a4\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a4~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a52\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a52~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a52\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a52~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a56\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a56~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a56\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a56~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a60\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a60~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a60\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a60~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a64\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a64~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a64\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a64~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a68\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a68~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a68\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a68~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a72\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a72~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a72\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a72~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a8\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a8~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a8\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a8~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "" 0 -1}
{ "Warning" "WSTA_CLOCK_UNCERTAINTY_NUMBERS_ARE_PRELIMINARY" "Stratix IV " "Warning: Clock uncertainty characteristics of the Stratix IV device family are preliminary" {  } {  } 0 0 "Clock uncertainty characteristics of the %1!s! device family are preliminary" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: LA_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 6.400 " "Warning: Node: LA_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 6.400" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.019 " "Info: Worst-case setup slack is 47.019" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   47.019         0.000 altera_reserved_tck  " "Info:    47.019         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.726 " "Info: Worst-case hold slack is 0.726" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.726         0.000 altera_reserved_tck  " "Info:     0.726         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.959 " "Info: Worst-case recovery slack is 48.959" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.959         0.000 altera_reserved_tck  " "Info:    48.959         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.041 " "Info: Worst-case removal slack is 1.041" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.041         0.000 altera_reserved_tck  " "Info:     1.041         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.263 " "Info: Worst-case minimum pulse width slack is 49.263" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.263         0.000 altera_reserved_tck  " "Info:    49.263         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: Analyzing Fast 900mV 0C Model" {  } {  } 0 0 "Analyzing Fast 900mV 0C Model" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP4SGX230KF40C2 " "Warning: Timing characteristics of device EP4SGX230KF40C2 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0 -1}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "INIT_CLK " "Warning: Node: INIT_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 0 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "" 0 -1}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "Info: The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a0\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a0~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a0\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a0~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a12\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a12~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a12\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a12~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a16\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a16~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a16\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a16~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a20\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a20~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a20\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a20~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a24\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a24~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a24\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a24~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a28\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a28~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a28\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a28~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a32\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a32~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a32\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a32~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a36\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a36~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a36\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a36~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a40\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a40~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a40\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a40~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a44\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a44~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a44\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a44~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a48\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a48~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a48\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a48~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a4\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a4~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a4\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a4~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a52\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a52~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a52\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a52~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a56\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a56~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a56\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a56~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a60\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a60~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a60\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a60~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a64\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a64~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a64\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a64~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a68\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a68~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a68\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a68~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a72\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a72~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a72\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a72~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CLOCK_MGR_INFO" "From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a8\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a8~portb_memory_reg " "Info: From: auto_signaltap_0\|sld_signaltap_body\|\\stp_non_zero_ram_gen:stp_buffer_ram\|auto_generated\|ram_block1a8\|clk1  to: sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_sos3:auto_generated\|ram_block1a8~portb_memory_reg" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "" 0 -1}
{ "Warning" "WSTA_CLOCK_UNCERTAINTY_NUMBERS_ARE_PRELIMINARY" "Stratix IV " "Warning: Clock uncertainty characteristics of the Stratix IV device family are preliminary" {  } {  } 0 0 "Clock uncertainty characteristics of the %1!s! device family are preliminary" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty " "Info: Deriving Clock Uncertainty" { { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -setup 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -rise_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -rise_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020 " "Info: set_clock_uncertainty -fall_from \[get_clocks \{altera_reserved_tck\}\] -fall_to \[get_clocks \{altera_reserved_tck\}\] -hold 0.020" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "Warning: PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: LA_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 6.400 " "Warning: Node: LA_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 6.400" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|rx_cdr_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Warning" "WSTA_GENERIC_WARNING" "Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640 " "Warning: Node: aurora_module_i\|MGT_0\|tx_pll0\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 0.640" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.547 " "Info: Worst-case setup slack is 48.547" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.547         0.000 altera_reserved_tck  " "Info:    48.547         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.412 " "Info: Worst-case hold slack is 0.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.412         0.000 altera_reserved_tck  " "Info:     0.412         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 49.726 " "Info: Worst-case recovery slack is 49.726" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.726         0.000 altera_reserved_tck  " "Info:    49.726         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.605 " "Info: Worst-case removal slack is 0.605" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.605         0.000 altera_reserved_tck  " "Info:     0.605         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.140 " "Info: Worst-case minimum pulse width slack is 49.140" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "Info:     Slack End Point TNS Clock " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "Info: ========= ============= =====================" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.140         0.000 altera_reserved_tck  " "Info:    49.140         0.000 altera_reserved_tck " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" {  } {  } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 22 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "377 " "Info: Peak virtual memory: 377 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 23 01:47:35 2010 " "Info: Processing ended: Thu Dec 23 01:47:35 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Info: Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
