Quartus II 64-Bit
Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
46
3480
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
aurora_8b10b_v5_2_example_design
# storage
db|aurora_8b10b_v5_2_example_design.(0).cnf
db|aurora_8b10b_v5_2_example_design.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|example_design|aurora_8b10b_v5_2_example_design.vhd
93366f66e3837524d47cc3bbb384cb89
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
USE_CHIPSCOPE
0
PARAMETER_SIGNED_DEC
DEF
SIM_GTXRESET_SPEEDUP
1
PARAMETER_SIGNED_DEC
DEF
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
|
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altpll
# storage
db|aurora_8b10b_v5_2_example_design.(2).cnf
db|aurora_8b10b_v5_2_example_design.(2).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altpll.tdf
86b75138429c7354c383e2cca01ca9f6
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
LPM_HINT
CBX_MODULE_PREFIX=PLL_LA
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
6400
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
USR
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
16
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
5
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
PLL_LA_altpll
PARAMETER_UNKNOWN
USR
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
10
PARAMETER_SIGNED_DEC
USR
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk0
-1
3
clk0
-1
3
inclk1
-1
1
}
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_FRAME_CHECK
# storage
db|aurora_8b10b_v5_2_example_design.(4).cnf
db|aurora_8b10b_v5_2_example_design.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|example_design|traffic_gen_check|aurora_8b10b_v5_2_frame_check.vhd
8350bf1ee232391be931dfb27129144e
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(rx_d)
0 to 15
PARAMETER_STRING
USR
 constraint(err_count)
0 to 7
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_FRAME_GEN
# storage
db|aurora_8b10b_v5_2_example_design.(5).cnf
db|aurora_8b10b_v5_2_example_design.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|example_design|traffic_gen_check|aurora_8b10b_v5_2_frame_gen.vhd
5d656e7accb1a62af8608423aa519654
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(tx_d)
0 to 15
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2
# storage
db|aurora_8b10b_v5_2_example_design.(6).cnf
db|aurora_8b10b_v5_2_example_design.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|example_design|aurora_8b10b_v5_2.vhd
6d1c17362f258969bae670f48e1337
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sim_gtxreset_speedup
1
PARAMETER_SIGNED_DEC
USR
 constraint(tx_d)
0 to 15
PARAMETER_STRING
USR
 constraint(rx_d)
0 to 15
PARAMETER_STRING
USR
 constraint(loopback)
2 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_AURORA_LANE
# storage
db|aurora_8b10b_v5_2_example_design.(7).cnf
db|aurora_8b10b_v5_2_example_design.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_lane.vhd
2a17acc72b8e2091b940ea83ed3d842
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(rx_data)
15 downto 0
PARAMETER_STRING
USR
 constraint(rx_not_in_table)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_disp_err)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_char_is_k)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_char_is_comma)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_status)
5 downto 0
PARAMETER_STRING
USR
 constraint(tx_char_is_k)
1 downto 0
PARAMETER_STRING
USR
 constraint(tx_data)
15 downto 0
PARAMETER_STRING
USR
 constraint(tx_pe_data)
0 to 15
PARAMETER_STRING
USR
 constraint(rx_pe_data)
0 to 15
PARAMETER_STRING
USR
 constraint(gen_k)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_r)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_v)
0 to 1
PARAMETER_STRING
USR
 constraint(got_a)
0 to 1
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_CHBOND_COUNT_DEC
# storage
db|aurora_8b10b_v5_2_example_design.(10).cnf
db|aurora_8b10b_v5_2_example_design.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_chbond_count_dec.vhd
b2ec2463d8e4d208e372af4de9e7ff0
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(rx_status)
5 downto 0
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_SYM_GEN
# storage
db|aurora_8b10b_v5_2_example_design.(11).cnf
db|aurora_8b10b_v5_2_example_design.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_sym_gen.vhd
8e1a1613c7691c3a75d1e38689c2e2c
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(tx_pe_data)
0 to 15
PARAMETER_STRING
USR
 constraint(gen_k)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_r)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_v)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_sp_data)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_spa_data)
0 to 1
PARAMETER_STRING
USR
 constraint(tx_char_is_k)
1 downto 0
PARAMETER_STRING
USR
 constraint(tx_data)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_SYM_DEC
# storage
db|aurora_8b10b_v5_2_example_design.(12).cnf
db|aurora_8b10b_v5_2_example_design.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_sym_dec.vhd
218683ad9b3ecbc256c7aa3aeeccaae
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(rx_pe_data)
0 to 15
PARAMETER_STRING
USR
 constraint(got_a)
0 to 1
PARAMETER_STRING
USR
 constraint(rx_data)
15 downto 0
PARAMETER_STRING
USR
 constraint(rx_char_is_k)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_char_is_comma)
1 downto 0
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_ERR_DETECT
# storage
db|aurora_8b10b_v5_2_example_design.(13).cnf
db|aurora_8b10b_v5_2_example_design.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_err_detect.vhd
332f2eb0fcec99f98191f7de55b35a5
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(rx_disp_err)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_not_in_table)
1 downto 0
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
MGT_alt4gxb
# storage
db|aurora_8b10b_v5_2_example_design.(14).cnf
db|aurora_8b10b_v5_2_example_design.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
mgt.vhd
1778acd765ea4f9f55f3a189a214e
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
starting_channel_number
0
PARAMETER_SIGNED_DEC
DEF
 constraint(gxb_powerdown)
0 downto 0
PARAMETER_STRING
USR
 constraint(pll_locked)
0 downto 0
PARAMETER_STRING
USR
 constraint(pll_powerdown)
0 downto 0
PARAMETER_STRING
USR
 constraint(reconfig_fromgxb)
16 downto 0
PARAMETER_STRING
USR
 constraint(reconfig_togxb)
3 downto 0
PARAMETER_STRING
USR
 constraint(rx_clkout)
0 downto 0
PARAMETER_STRING
USR
 constraint(rx_ctrldetect)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_datain)
0 downto 0
PARAMETER_STRING
USR
 constraint(rx_dataout)
15 downto 0
PARAMETER_STRING
USR
 constraint(rx_digitalreset)
0 downto 0
PARAMETER_STRING
USR
 constraint(rx_disperr)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_enapatternalign)
0 downto 0
PARAMETER_STRING
USR
 constraint(rx_errdetect)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_invpolarity)
0 downto 0
PARAMETER_STRING
USR
 constraint(rx_patterndetect)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_phase_comp_fifo_error)
0 downto 0
PARAMETER_STRING
USR
 constraint(rx_syncstatus)
1 downto 0
PARAMETER_STRING
USR
 constraint(tx_clkout)
0 downto 0
PARAMETER_STRING
USR
 constraint(tx_ctrlenable)
1 downto 0
PARAMETER_STRING
USR
 constraint(tx_datain)
15 downto 0
PARAMETER_STRING
USR
 constraint(tx_dataout)
0 downto 0
PARAMETER_STRING
USR
 constraint(tx_digitalreset)
0 downto 0
PARAMETER_STRING
USR
 constraint(tx_phase_comp_fifo_error)
0 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_GLOBAL_LOGIC
# storage
db|aurora_8b10b_v5_2_example_design.(15).cnf
db|aurora_8b10b_v5_2_example_design.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_global_logic.vhd
99947c94af59aceb4fdfa2fae570a346
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(got_a)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_k)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_r)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_v)
0 to 1
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(21).cnf
db|aurora_8b10b_v5_2_example_design.(21).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
16
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
LEFT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
LPM_MUX
# storage
db|aurora_8b10b_v5_2_example_design.(23).cnf
db|aurora_8b10b_v5_2_example_design.(23).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_mux.tdf
d2c33760a4359bf0707ac9e7afb311f2
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
1
PARAMETER_SIGNED_DEC
USR
LPM_SIZE
16
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHS
4
PARAMETER_SIGNED_DEC
USR
LPM_PIPELINE
0
PARAMETER_SIGNED_DEC
USR
CBXI_PARAMETER
mux_76e
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
}
# used_port {
SEL3
-1
3
SEL2
-1
3
SEL1
-1
3
SEL0
-1
3
RESULT0
-1
3
DATA9_0
-1
3
DATA8_0
-1
3
DATA7_0
-1
3
DATA6_0
-1
3
DATA5_0
-1
3
DATA4_0
-1
3
DATA3_0
-1
3
DATA2_0
-1
3
DATA1_0
-1
3
DATA15_0
-1
3
DATA14_0
-1
3
DATA13_0
-1
3
DATA12_0
-1
3
DATA11_0
-1
3
DATA10_0
-1
3
DATA0_0
-1
3
}
# macro_sequence

# end
# entity
mux_76e
# storage
db|aurora_8b10b_v5_2_example_design.(24).cnf
db|aurora_8b10b_v5_2_example_design.(24).cnf
# case_insensitive
# source_file
db|mux_76e.tdf
7c9468ea108bed4b0dc4fe2266bb068
7
# used_port {
sel3
-1
3
sel2
-1
3
sel1
-1
3
sel0
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|lpm_mux:lpm_mux_component|mux_76e:auto_generated
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1|lpm_mux:lpm_mux_component|mux_76e:auto_generated
}
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_CHANNEL_ERR_DETECT
# storage
db|aurora_8b10b_v5_2_example_design.(25).cnf
db|aurora_8b10b_v5_2_example_design.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_channel_err_detect.vhd
24ff4a4b909c381725fedbd24b12cb3
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_TX_LL
# storage
db|aurora_8b10b_v5_2_example_design.(26).cnf
db|aurora_8b10b_v5_2_example_design.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_tx_ll.vhd
747fb8e5f03f34a940733581b79b13a1
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(tx_d)
0 to 15
PARAMETER_STRING
USR
 constraint(tx_pe_data)
0 to 15
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_TX_LL_DATAPATH
# storage
db|aurora_8b10b_v5_2_example_design.(27).cnf
db|aurora_8b10b_v5_2_example_design.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_tx_ll_datapath.vhd
e0d933a5e8fc2b29c44e49f9a2f179
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(tx_d)
0 to 15
PARAMETER_STRING
USR
 constraint(tx_pe_data)
0 to 15
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_RX_LL
# storage
db|aurora_8b10b_v5_2_example_design.(29).cnf
db|aurora_8b10b_v5_2_example_design.(29).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_rx_ll.vhd
158b49ecc8b05651801c52aea8b211
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(rx_d)
0 to 15
PARAMETER_STRING
USR
 constraint(rx_pe_data)
0 to 15
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_RX_LL:rx_ll_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH
# storage
db|aurora_8b10b_v5_2_example_design.(30).cnf
db|aurora_8b10b_v5_2_example_design.(30).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_rx_ll_pdu_datapath.vhd
537c91175efaa2caea9a143a68818dfb
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(pdu_data)
0 to 15
PARAMETER_STRING
USR
 constraint(rx_d)
0 to 15
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_RX_LL:rx_ll_i|aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_STANDARD_CC_MODULE
# storage
db|aurora_8b10b_v5_2_example_design.(31).cnf
db|aurora_8b10b_v5_2_example_design.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|example_design|cc_manager|aurora_8b10b_v5_2_standard_cc_module.vhd
70ed6f665362aa378f27211a56dbae9
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_RESET_LOGIC
# storage
db|aurora_8b10b_v5_2_example_design.(32).cnf
db|aurora_8b10b_v5_2_example_design.(32).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|example_design|aurora_8b10b_v5_2_reset_logic.vhd
307e6e8e1bc057f0b4abb8ab4575dafe
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(33).cnf
db|aurora_8b10b_v5_2_example_design.(33).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
75
PARAMETER_UNKNOWN
USR
sld_trigger_bits
75
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
47053
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
5216
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
250
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(34).cnf
db|aurora_8b10b_v5_2_example_design.(34).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
75
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
75
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
47053
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
5216
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
250
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 249
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
74 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
74 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
74 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
74 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(35).cnf
db|aurora_8b10b_v5_2_example_design.(35).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
75
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
sample_depth
2048
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
249 downto 249
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
74 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(36).cnf
db|aurora_8b10b_v5_2_example_design.(36).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
4
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(37).cnf
db|aurora_8b10b_v5_2_example_design.(37).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
75
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
74 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(38).cnf
db|aurora_8b10b_v5_2_example_design.(38).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
225
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q99
-1
3
Q98
-1
3
Q97
-1
3
Q96
-1
3
Q95
-1
3
Q94
-1
3
Q93
-1
3
Q92
-1
3
Q91
-1
3
Q90
-1
3
Q9
-1
3
Q89
-1
3
Q88
-1
3
Q87
-1
3
Q86
-1
3
Q85
-1
3
Q84
-1
3
Q83
-1
3
Q82
-1
3
Q81
-1
3
Q80
-1
3
Q8
-1
3
Q79
-1
3
Q78
-1
3
Q77
-1
3
Q76
-1
3
Q75
-1
3
Q74
-1
3
Q73
-1
3
Q72
-1
3
Q71
-1
3
Q70
-1
3
Q7
-1
3
Q69
-1
3
Q68
-1
3
Q67
-1
3
Q66
-1
3
Q65
-1
3
Q64
-1
3
Q63
-1
3
Q62
-1
3
Q61
-1
3
Q60
-1
3
Q6
-1
3
Q59
-1
3
Q58
-1
3
Q57
-1
3
Q56
-1
3
Q55
-1
3
Q54
-1
3
Q53
-1
3
Q52
-1
3
Q51
-1
3
Q50
-1
3
Q5
-1
3
Q49
-1
3
Q48
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q32
-1
3
Q31
-1
3
Q30
-1
3
Q3
-1
3
Q29
-1
3
Q28
-1
3
Q27
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q224
-1
3
Q223
-1
3
Q222
-1
3
Q221
-1
3
Q220
-1
3
Q22
-1
3
Q219
-1
3
Q218
-1
3
Q217
-1
3
Q216
-1
3
Q215
-1
3
Q214
-1
3
Q213
-1
3
Q212
-1
3
Q211
-1
3
Q210
-1
3
Q21
-1
3
Q209
-1
3
Q208
-1
3
Q207
-1
3
Q206
-1
3
Q205
-1
3
Q204
-1
3
Q203
-1
3
Q202
-1
3
Q201
-1
3
Q200
-1
3
Q20
-1
3
Q2
-1
3
Q199
-1
3
Q198
-1
3
Q197
-1
3
Q196
-1
3
Q195
-1
3
Q194
-1
3
Q193
-1
3
Q192
-1
3
Q191
-1
3
Q190
-1
3
Q19
-1
3
Q189
-1
3
Q188
-1
3
Q187
-1
3
Q186
-1
3
Q185
-1
3
Q184
-1
3
Q183
-1
3
Q182
-1
3
Q181
-1
3
Q180
-1
3
Q18
-1
3
Q179
-1
3
Q178
-1
3
Q177
-1
3
Q176
-1
3
Q175
-1
3
Q174
-1
3
Q173
-1
3
Q172
-1
3
Q171
-1
3
Q170
-1
3
Q17
-1
3
Q169
-1
3
Q168
-1
3
Q167
-1
3
Q166
-1
3
Q165
-1
3
Q164
-1
3
Q163
-1
3
Q162
-1
3
Q161
-1
3
Q160
-1
3
Q16
-1
3
Q159
-1
3
Q158
-1
3
Q157
-1
3
Q156
-1
3
Q155
-1
3
Q154
-1
3
Q153
-1
3
Q152
-1
3
Q151
-1
3
Q150
-1
3
Q15
-1
3
Q149
-1
3
Q148
-1
3
Q147
-1
3
Q146
-1
3
Q145
-1
3
Q144
-1
3
Q143
-1
3
Q142
-1
3
Q141
-1
3
Q140
-1
3
Q14
-1
3
Q139
-1
3
Q138
-1
3
Q137
-1
3
Q136
-1
3
Q135
-1
3
Q134
-1
3
Q133
-1
3
Q132
-1
3
Q131
-1
3
Q130
-1
3
Q13
-1
3
Q129
-1
3
Q128
-1
3
Q127
-1
3
Q126
-1
3
Q125
-1
3
Q124
-1
3
Q123
-1
3
Q122
-1
3
Q121
-1
3
Q120
-1
3
Q12
-1
3
Q119
-1
3
Q118
-1
3
Q117
-1
3
Q116
-1
3
Q115
-1
3
Q114
-1
3
Q113
-1
3
Q112
-1
3
Q111
-1
3
Q110
-1
3
Q11
-1
3
Q109
-1
3
Q108
-1
3
Q107
-1
3
Q106
-1
3
Q105
-1
3
Q104
-1
3
Q103
-1
3
Q102
-1
3
Q101
-1
3
Q100
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(39).cnf
db|aurora_8b10b_v5_2_example_design.(39).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
75
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
74 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
224 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_sbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(40).cnf
db|aurora_8b10b_v5_2_example_design.(40).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_trigger_flow_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(41).cnf
db|aurora_8b10b_v5_2_example_design.(41).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_trigger_flow_mgr.vhd
54b4e96651b97ec28a57c8b6d87fce
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(condition_met)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(42).cnf
db|aurora_8b10b_v5_2_example_design.(42).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
10
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_buffer_manager
# storage
db|aurora_8b10b_v5_2_example_design.(43).cnf
db|aurora_8b10b_v5_2_example_design.(43).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
address_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
num_segments_bits
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(address)
10 downto 0
PARAMETER_STRING
USR
 constraint(post_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_segment)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_offset)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_trigger_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(44).cnf
db|aurora_8b10b_v5_2_example_design.(44).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
11
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(45).cnf
db|aurora_8b10b_v5_2_example_design.(45).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
75
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
75
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_3p14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_3p14
# storage
db|aurora_8b10b_v5_2_example_design.(46).cnf
db|aurora_8b10b_v5_2_example_design.(46).cnf
# case_insensitive
# source_file
db|altsyncram_3p14.tdf
82eb44d7b697edd5a0a9b32c2c8c970
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altdpram
# storage
db|aurora_8b10b_v5_2_example_design.(47).cnf
db|aurora_8b10b_v5_2_example_design.(47).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altdpram.tdf
2c2259fdcccd62fa8105010b956d34
7
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
WIDTH
23
PARAMETER_SIGNED_DEC
USR
WIDTHAD
1
PARAMETER_SIGNED_DEC
USR
NUMWORDS
0
PARAMETER_SIGNED_DEC
USR
FILE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
DEF
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
BYTE_SIZE
0
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA
1
PARAMETER_SIGNED_DEC
USR
DISABLE_LE_RAM_LIMIT_CHECK
on
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
-1
3
wraddress0
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclocken
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
lpm_mux
# storage
db|aurora_8b10b_v5_2_example_design.(48).cnf
db|aurora_8b10b_v5_2_example_design.(48).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_mux.tdf
d2c33760a4359bf0707ac9e7afb311f2
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
23
PARAMETER_UNKNOWN
USR
LPM_SIZE
2
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_opc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
}
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data1_9
-1
3
data1_8
-1
3
data1_7
-1
3
data1_6
-1
3
data1_5
-1
3
data1_4
-1
3
data1_3
-1
3
data1_22
-1
3
data1_21
-1
3
data1_20
-1
3
data1_2
-1
3
data1_19
-1
3
data1_18
-1
3
data1_17
-1
3
data1_16
-1
3
data1_15
-1
3
data1_14
-1
3
data1_13
-1
3
data1_12
-1
3
data1_11
-1
3
data1_10
-1
3
data1_1
-1
3
data1_0
-1
3
data0_9
-1
3
data0_8
-1
3
data0_7
-1
3
data0_6
-1
3
data0_5
-1
3
data0_4
-1
3
data0_3
-1
3
data0_22
-1
3
data0_21
-1
3
data0_20
-1
3
data0_2
-1
3
data0_19
-1
3
data0_18
-1
3
data0_17
-1
3
data0_16
-1
3
data0_15
-1
3
data0_14
-1
3
data0_13
-1
3
data0_12
-1
3
data0_11
-1
3
data0_10
-1
3
data0_1
-1
3
data0_0
-1
3
}
# macro_sequence

# end
# entity
mux_opc
# storage
db|aurora_8b10b_v5_2_example_design.(49).cnf
db|aurora_8b10b_v5_2_example_design.(49).cnf
# case_insensitive
# source_file
db|mux_opc.tdf
a8a0c947dca72f64d080bd8facde1080
7
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data45
-1
3
data44
-1
3
data43
-1
3
data42
-1
3
data41
-1
3
data40
-1
3
data4
-1
3
data39
-1
3
data38
-1
3
data37
-1
3
data36
-1
3
data35
-1
3
data34
-1
3
data33
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
lpm_decode
# storage
db|aurora_8b10b_v5_2_example_design.(50).cnf
db|aurora_8b10b_v5_2_example_design.(50).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_decode.tdf
61bb7230fce64482977996ae7bdd7ec8
7
# user_parameter {
LPM_WIDTH
1
PARAMETER_UNKNOWN
USR
LPM_DECODES
2
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_asf
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
eq1
-1
3
eq0
-1
3
enable
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
decode_asf
# storage
db|aurora_8b10b_v5_2_example_design.(51).cnf
db|aurora_8b10b_v5_2_example_design.(51).cnf
# case_insensitive
# source_file
db|decode_asf.tdf
cd9a63459c7fa84565eb07928c48b49
7
# used_port {
eq1
-1
3
eq0
-1
3
enable
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(52).cnf
db|aurora_8b10b_v5_2_example_design.(52).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
2048
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
75
PARAMETER_SIGNED_DEC
USR
status_bits
23
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
7
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
74 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
22 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(53).cnf
db|aurora_8b10b_v5_2_example_design.(53).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
7
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
75
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_kdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_kdi
# storage
db|aurora_8b10b_v5_2_example_design.(54).cnf
db|aurora_8b10b_v5_2_example_design.(54).cnf
# case_insensitive
# source_file
db|cntr_kdi.tdf
1a3875d596a941c531b8694a6ed6
7
# used_port {
sclr
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_qdc
# storage
db|aurora_8b10b_v5_2_example_design.(55).cnf
db|aurora_8b10b_v5_2_example_design.(55).cnf
# case_insensitive
# source_file
db|cmpr_qdc.tdf
1b1c37b9b2a89b5e2d85e3e4f229b16
7
# used_port {
datab5
-1
3
datab4
-1
3
datab2
-1
3
datab0
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab6
-1
2
datab3
-1
2
datab1
-1
2
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(56).cnf
db|aurora_8b10b_v5_2_example_design.(56).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
11
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
2048
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_d6j
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
CLK_EN
-1
3
}
# macro_sequence

# end
# entity
cntr_d6j
# storage
db|aurora_8b10b_v5_2_example_design.(57).cnf
db|aurora_8b10b_v5_2_example_design.(57).cnf
# case_insensitive
# source_file
db|cntr_d6j.tdf
505d7ec7c186e66bef71b11b0b1d26a
7
# used_port {
sclr
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(58).cnf
db|aurora_8b10b_v5_2_example_design.(58).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
75
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA74
-1
3
DATA73
-1
3
DATA72
-1
3
DATA71
-1
3
DATA70
-1
3
DATA7
-1
3
DATA69
-1
3
DATA68
-1
3
DATA67
-1
3
DATA66
-1
3
DATA65
-1
3
DATA64
-1
3
DATA63
-1
3
DATA62
-1
3
DATA61
-1
3
DATA60
-1
3
DATA6
-1
3
DATA59
-1
3
DATA58
-1
3
DATA57
-1
3
DATA56
-1
3
DATA55
-1
3
DATA54
-1
3
DATA53
-1
3
DATA52
-1
3
DATA51
-1
3
DATA50
-1
3
DATA5
-1
3
DATA49
-1
3
DATA48
-1
3
DATA47
-1
3
DATA46
-1
3
DATA45
-1
3
DATA44
-1
3
DATA43
-1
3
DATA42
-1
3
DATA41
-1
3
DATA40
-1
3
DATA4
-1
3
DATA39
-1
3
DATA38
-1
3
DATA37
-1
3
DATA36
-1
3
DATA35
-1
3
DATA34
-1
3
DATA33
-1
3
DATA32
-1
3
DATA31
-1
3
DATA30
-1
3
DATA3
-1
3
DATA29
-1
3
DATA28
-1
3
DATA27
-1
3
DATA26
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(59).cnf
db|aurora_8b10b_v5_2_example_design.(59).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
23
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
ENABLE
-1
2
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(60).cnf
db|aurora_8b10b_v5_2_example_design.(60).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
5
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
23
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_bdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_bdi
# storage
db|aurora_8b10b_v5_2_example_design.(61).cnf
db|aurora_8b10b_v5_2_example_design.(61).cnf
# case_insensitive
# source_file
db|cntr_bdi.tdf
e12b3a9a353359181bd8376a4f9a531
7
# used_port {
sclr
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_odc
# storage
db|aurora_8b10b_v5_2_example_design.(62).cnf
db|aurora_8b10b_v5_2_example_design.(62).cnf
# case_insensitive
# source_file
db|cmpr_odc.tdf
b5a8fd1152ae30674532ca5d75349
7
# used_port {
datab3
-1
3
datab0
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab4
-1
2
datab2
-1
2
datab1
-1
2
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(63).cnf
db|aurora_8b10b_v5_2_example_design.(63).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
1
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
1
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_vvi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q0
-1
3
CLOCK
-1
3
CLK_EN
-1
3
}
# macro_sequence

# end
# entity
cntr_vvi
# storage
db|aurora_8b10b_v5_2_example_design.(64).cnf
db|aurora_8b10b_v5_2_example_design.(64).cnf
# case_insensitive
# source_file
db|cntr_vvi.tdf
f63252371d443b3b48feb38e8d35c638
7
# used_port {
sclr
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
}
# macro_sequence

# end
# entity
cmpr_kdc
# storage
db|aurora_8b10b_v5_2_example_design.(65).cnf
db|aurora_8b10b_v5_2_example_design.(65).cnf
# case_insensitive
# source_file
db|cmpr_kdc.tdf
a85e27142f81783aa3a63806f4e9
7
# used_port {
datab0
-1
3
dataa0
-1
3
aeb
-1
3
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(66).cnf
db|aurora_8b10b_v5_2_example_design.(66).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
23
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|aurora_8b10b_v5_2_example_design.(67).cnf
db|aurora_8b10b_v5_2_example_design.(67).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_rom_sr.vhd
c8a299171b404a8be9d59988f836b14
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
32
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
31 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(68).cnf
db|aurora_8b10b_v5_2_example_design.(68).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
17
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
LOAD
-1
3
ENABLE
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
sld_hub
# storage
db|aurora_8b10b_v5_2_example_design.(69).cnf
db|aurora_8b10b_v5_2_example_design.(69).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_hub.vhd
7a79487a6e8170b43b1767a2ea68
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
4
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Stratix IV
PARAMETER_UNKNOWN
USR
n_nodes
1
PARAMETER_UNKNOWN
USR
n_sel_bits
1
PARAMETER_UNKNOWN
USR
n_node_ir_bits
8
PARAMETER_UNKNOWN
USR
node_info
00110000000000000110111000000000
PARAMETER_UNSIGNED_BIN
USR
compilation_mode
1
PARAMETER_UNKNOWN
USR
BROADCAST_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
FORCE_IR_CAPTURE_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_shadow_jsm
# storage
db|aurora_8b10b_v5_2_example_design.(70).cnf
db|aurora_8b10b_v5_2_example_design.(70).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_hub.vhd
7a79487a6e8170b43b1767a2ea68
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
1
PARAMETER_SIGNED_DEC
USR
ip_minor_version
4
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
 constraint(jtag_state)
15 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|aurora_8b10b_v5_2_example_design.(71).cnf
db|aurora_8b10b_v5_2_example_design.(71).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_rom_sr.vhd
c8a299171b404a8be9d59988f836b14
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
64
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
63 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(72).cnf
db|aurora_8b10b_v5_2_example_design.(72).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
113
PARAMETER_UNKNOWN
USR
sld_trigger_bits
113
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
17217
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
18035
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
364
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(73).cnf
db|aurora_8b10b_v5_2_example_design.(73).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
113
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
113
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
17217
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
18035
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
364
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 363
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
112 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(74).cnf
db|aurora_8b10b_v5_2_example_design.(74).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
113
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
sample_depth
2048
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
363 downto 363
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(75).cnf
db|aurora_8b10b_v5_2_example_design.(75).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
113
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(76).cnf
db|aurora_8b10b_v5_2_example_design.(76).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
339
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q99
-1
3
Q98
-1
3
Q97
-1
3
Q96
-1
3
Q95
-1
3
Q94
-1
3
Q93
-1
3
Q92
-1
3
Q91
-1
3
Q90
-1
3
Q9
-1
3
Q89
-1
3
Q88
-1
3
Q87
-1
3
Q86
-1
3
Q85
-1
3
Q84
-1
3
Q83
-1
3
Q82
-1
3
Q81
-1
3
Q80
-1
3
Q8
-1
3
Q79
-1
3
Q78
-1
3
Q77
-1
3
Q76
-1
3
Q75
-1
3
Q74
-1
3
Q73
-1
3
Q72
-1
3
Q71
-1
3
Q70
-1
3
Q7
-1
3
Q69
-1
3
Q68
-1
3
Q67
-1
3
Q66
-1
3
Q65
-1
3
Q64
-1
3
Q63
-1
3
Q62
-1
3
Q61
-1
3
Q60
-1
3
Q6
-1
3
Q59
-1
3
Q58
-1
3
Q57
-1
3
Q56
-1
3
Q55
-1
3
Q54
-1
3
Q53
-1
3
Q52
-1
3
Q51
-1
3
Q50
-1
3
Q5
-1
3
Q49
-1
3
Q48
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q338
-1
3
Q337
-1
3
Q336
-1
3
Q335
-1
3
Q334
-1
3
Q333
-1
3
Q332
-1
3
Q331
-1
3
Q330
-1
3
Q33
-1
3
Q329
-1
3
Q328
-1
3
Q327
-1
3
Q326
-1
3
Q325
-1
3
Q324
-1
3
Q323
-1
3
Q322
-1
3
Q321
-1
3
Q320
-1
3
Q32
-1
3
Q319
-1
3
Q318
-1
3
Q317
-1
3
Q316
-1
3
Q315
-1
3
Q314
-1
3
Q313
-1
3
Q312
-1
3
Q311
-1
3
Q310
-1
3
Q31
-1
3
Q309
-1
3
Q308
-1
3
Q307
-1
3
Q306
-1
3
Q305
-1
3
Q304
-1
3
Q303
-1
3
Q302
-1
3
Q301
-1
3
Q300
-1
3
Q30
-1
3
Q3
-1
3
Q299
-1
3
Q298
-1
3
Q297
-1
3
Q296
-1
3
Q295
-1
3
Q294
-1
3
Q293
-1
3
Q292
-1
3
Q291
-1
3
Q290
-1
3
Q29
-1
3
Q289
-1
3
Q288
-1
3
Q287
-1
3
Q286
-1
3
Q285
-1
3
Q284
-1
3
Q283
-1
3
Q282
-1
3
Q281
-1
3
Q280
-1
3
Q28
-1
3
Q279
-1
3
Q278
-1
3
Q277
-1
3
Q276
-1
3
Q275
-1
3
Q274
-1
3
Q273
-1
3
Q272
-1
3
Q271
-1
3
Q270
-1
3
Q27
-1
3
Q269
-1
3
Q268
-1
3
Q267
-1
3
Q266
-1
3
Q265
-1
3
Q264
-1
3
Q263
-1
3
Q262
-1
3
Q261
-1
3
Q260
-1
3
Q26
-1
3
Q259
-1
3
Q258
-1
3
Q257
-1
3
Q256
-1
3
Q255
-1
3
Q254
-1
3
Q253
-1
3
Q252
-1
3
Q251
-1
3
Q250
-1
3
Q25
-1
3
Q249
-1
3
Q248
-1
3
Q247
-1
3
Q246
-1
3
Q245
-1
3
Q244
-1
3
Q243
-1
3
Q242
-1
3
Q241
-1
3
Q240
-1
3
Q24
-1
3
Q239
-1
3
Q238
-1
3
Q237
-1
3
Q236
-1
3
Q235
-1
3
Q234
-1
3
Q233
-1
3
Q232
-1
3
Q231
-1
3
Q230
-1
3
Q23
-1
3
Q229
-1
3
Q228
-1
3
Q227
-1
3
Q226
-1
3
Q225
-1
3
Q224
-1
3
Q223
-1
3
Q222
-1
3
Q221
-1
3
Q220
-1
3
Q22
-1
3
Q219
-1
3
Q218
-1
3
Q217
-1
3
Q216
-1
3
Q215
-1
3
Q214
-1
3
Q213
-1
3
Q212
-1
3
Q211
-1
3
Q210
-1
3
Q21
-1
3
Q209
-1
3
Q208
-1
3
Q207
-1
3
Q206
-1
3
Q205
-1
3
Q204
-1
3
Q203
-1
3
Q202
-1
3
Q201
-1
3
Q200
-1
3
Q20
-1
3
Q2
-1
3
Q199
-1
3
Q198
-1
3
Q197
-1
3
Q196
-1
3
Q195
-1
3
Q194
-1
3
Q193
-1
3
Q192
-1
3
Q191
-1
3
Q190
-1
3
Q19
-1
3
Q189
-1
3
Q188
-1
3
Q187
-1
3
Q186
-1
3
Q185
-1
3
Q184
-1
3
Q183
-1
3
Q182
-1
3
Q181
-1
3
Q180
-1
3
Q18
-1
3
Q179
-1
3
Q178
-1
3
Q177
-1
3
Q176
-1
3
Q175
-1
3
Q174
-1
3
Q173
-1
3
Q172
-1
3
Q171
-1
3
Q170
-1
3
Q17
-1
3
Q169
-1
3
Q168
-1
3
Q167
-1
3
Q166
-1
3
Q165
-1
3
Q164
-1
3
Q163
-1
3
Q162
-1
3
Q161
-1
3
Q160
-1
3
Q16
-1
3
Q159
-1
3
Q158
-1
3
Q157
-1
3
Q156
-1
3
Q155
-1
3
Q154
-1
3
Q153
-1
3
Q152
-1
3
Q151
-1
3
Q150
-1
3
Q15
-1
3
Q149
-1
3
Q148
-1
3
Q147
-1
3
Q146
-1
3
Q145
-1
3
Q144
-1
3
Q143
-1
3
Q142
-1
3
Q141
-1
3
Q140
-1
3
Q14
-1
3
Q139
-1
3
Q138
-1
3
Q137
-1
3
Q136
-1
3
Q135
-1
3
Q134
-1
3
Q133
-1
3
Q132
-1
3
Q131
-1
3
Q130
-1
3
Q13
-1
3
Q129
-1
3
Q128
-1
3
Q127
-1
3
Q126
-1
3
Q125
-1
3
Q124
-1
3
Q123
-1
3
Q122
-1
3
Q121
-1
3
Q120
-1
3
Q12
-1
3
Q119
-1
3
Q118
-1
3
Q117
-1
3
Q116
-1
3
Q115
-1
3
Q114
-1
3
Q113
-1
3
Q112
-1
3
Q111
-1
3
Q110
-1
3
Q11
-1
3
Q109
-1
3
Q108
-1
3
Q107
-1
3
Q106
-1
3
Q105
-1
3
Q104
-1
3
Q103
-1
3
Q102
-1
3
Q101
-1
3
Q100
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(77).cnf
db|aurora_8b10b_v5_2_example_design.(77).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
113
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
338 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(78).cnf
db|aurora_8b10b_v5_2_example_design.(78).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
113
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
113
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_lr14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b99
-1
3
q_b98
-1
3
q_b97
-1
3
q_b96
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b112
-1
3
q_b111
-1
3
q_b110
-1
3
q_b11
-1
3
q_b109
-1
3
q_b108
-1
3
q_b107
-1
3
q_b106
-1
3
q_b105
-1
3
q_b104
-1
3
q_b103
-1
3
q_b102
-1
3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a112
-1
3
data_a111
-1
3
data_a110
-1
3
data_a11
-1
3
data_a109
-1
3
data_a108
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_lr14
# storage
db|aurora_8b10b_v5_2_example_design.(79).cnf
db|aurora_8b10b_v5_2_example_design.(79).cnf
# case_insensitive
# source_file
db|altsyncram_lr14.tdf
24ec47286f23d88a5514f9e03f4814
7
# used_port {
wren_a
-1
3
q_b99
-1
3
q_b98
-1
3
q_b97
-1
3
q_b96
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b112
-1
3
q_b111
-1
3
q_b110
-1
3
q_b11
-1
3
q_b109
-1
3
q_b108
-1
3
q_b107
-1
3
q_b106
-1
3
q_b105
-1
3
q_b104
-1
3
q_b103
-1
3
q_b102
-1
3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a112
-1
3
data_a111
-1
3
data_a110
-1
3
data_a11
-1
3
data_a109
-1
3
data_a108
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(80).cnf
db|aurora_8b10b_v5_2_example_design.(80).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
2048
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
113
PARAMETER_SIGNED_DEC
USR
status_bits
23
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
7
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
112 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
22 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(81).cnf
db|aurora_8b10b_v5_2_example_design.(81).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
7
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
113
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_tei
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_tei
# storage
db|aurora_8b10b_v5_2_example_design.(82).cnf
db|aurora_8b10b_v5_2_example_design.(82).cnf
# case_insensitive
# source_file
db|cntr_tei.tdf
7b1ac35d68c115ad54eea7e17c8a2da
7
# used_port {
sclr
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_qdc
# storage
db|aurora_8b10b_v5_2_example_design.(83).cnf
db|aurora_8b10b_v5_2_example_design.(83).cnf
# case_insensitive
# source_file
db|cmpr_qdc.tdf
1b1c37b9b2a89b5e2d85e3e4f229b16
7
# used_port {
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab6
-1
2
datab5
-1
2
datab4
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(84).cnf
db|aurora_8b10b_v5_2_example_design.(84).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
113
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA99
-1
3
DATA98
-1
3
DATA97
-1
3
DATA96
-1
3
DATA95
-1
3
DATA94
-1
3
DATA93
-1
3
DATA92
-1
3
DATA91
-1
3
DATA90
-1
3
DATA9
-1
3
DATA89
-1
3
DATA88
-1
3
DATA87
-1
3
DATA86
-1
3
DATA85
-1
3
DATA84
-1
3
DATA83
-1
3
DATA82
-1
3
DATA81
-1
3
DATA80
-1
3
DATA8
-1
3
DATA79
-1
3
DATA78
-1
3
DATA77
-1
3
DATA76
-1
3
DATA75
-1
3
DATA74
-1
3
DATA73
-1
3
DATA72
-1
3
DATA71
-1
3
DATA70
-1
3
DATA7
-1
3
DATA69
-1
3
DATA68
-1
3
DATA67
-1
3
DATA66
-1
3
DATA65
-1
3
DATA64
-1
3
DATA63
-1
3
DATA62
-1
3
DATA61
-1
3
DATA60
-1
3
DATA6
-1
3
DATA59
-1
3
DATA58
-1
3
DATA57
-1
3
DATA56
-1
3
DATA55
-1
3
DATA54
-1
3
DATA53
-1
3
DATA52
-1
3
DATA51
-1
3
DATA50
-1
3
DATA5
-1
3
DATA49
-1
3
DATA48
-1
3
DATA47
-1
3
DATA46
-1
3
DATA45
-1
3
DATA44
-1
3
DATA43
-1
3
DATA42
-1
3
DATA41
-1
3
DATA40
-1
3
DATA4
-1
3
DATA39
-1
3
DATA38
-1
3
DATA37
-1
3
DATA36
-1
3
DATA35
-1
3
DATA34
-1
3
DATA33
-1
3
DATA32
-1
3
DATA31
-1
3
DATA30
-1
3
DATA3
-1
3
DATA29
-1
3
DATA28
-1
3
DATA27
-1
3
DATA26
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA112
-1
3
DATA111
-1
3
DATA110
-1
3
DATA11
-1
3
DATA109
-1
3
DATA108
-1
3
DATA107
-1
3
DATA106
-1
3
DATA105
-1
3
DATA104
-1
3
DATA103
-1
3
DATA102
-1
3
DATA101
-1
3
DATA100
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(85).cnf
db|aurora_8b10b_v5_2_example_design.(85).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
113
PARAMETER_UNKNOWN
USR
sld_trigger_bits
113
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
19899
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
18035
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
512
PARAMETER_UNKNOWN
USR
sld_segment_size
512
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
362
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(86).cnf
db|aurora_8b10b_v5_2_example_design.(86).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
113
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
113
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
19899
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
18035
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
512
PARAMETER_SIGNED_DEC
USR
sld_segment_size
512
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
362
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 361
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
112 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(87).cnf
db|aurora_8b10b_v5_2_example_design.(87).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
113
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
9
PARAMETER_SIGNED_DEC
USR
sample_depth
512
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
9
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
361 downto 361
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
8 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_trigger_flow_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(88).cnf
db|aurora_8b10b_v5_2_example_design.(88).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_trigger_flow_mgr.vhd
54b4e96651b97ec28a57c8b6d87fce
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
segment_size_bits
9
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(condition_met)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
8 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_buffer_manager
# storage
db|aurora_8b10b_v5_2_example_design.(89).cnf
db|aurora_8b10b_v5_2_example_design.(89).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
address_bits
9
PARAMETER_SIGNED_DEC
USR
segment_size_bits
9
PARAMETER_SIGNED_DEC
USR
num_segments_bits
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(address)
8 downto 0
PARAMETER_STRING
USR
 constraint(post_count)
8 downto 0
PARAMETER_STRING
USR
 constraint(current_segment)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_offset)
8 downto 0
PARAMETER_STRING
USR
 constraint(last_trigger_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
8 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(90).cnf
db|aurora_8b10b_v5_2_example_design.(90).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
9
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(91).cnf
db|aurora_8b10b_v5_2_example_design.(91).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
113
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
113
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_4p14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b99
-1
3
q_b98
-1
3
q_b97
-1
3
q_b96
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b112
-1
3
q_b111
-1
3
q_b110
-1
3
q_b11
-1
3
q_b109
-1
3
q_b108
-1
3
q_b107
-1
3
q_b106
-1
3
q_b105
-1
3
q_b104
-1
3
q_b103
-1
3
q_b102
-1
3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a112
-1
3
data_a111
-1
3
data_a110
-1
3
data_a11
-1
3
data_a109
-1
3
data_a108
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_4p14
# storage
db|aurora_8b10b_v5_2_example_design.(92).cnf
db|aurora_8b10b_v5_2_example_design.(92).cnf
# case_insensitive
# source_file
db|altsyncram_4p14.tdf
b2a52d64e6619e771cb6146bb56afce1
7
# used_port {
wren_a
-1
3
q_b99
-1
3
q_b98
-1
3
q_b97
-1
3
q_b96
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b112
-1
3
q_b111
-1
3
q_b110
-1
3
q_b11
-1
3
q_b109
-1
3
q_b108
-1
3
q_b107
-1
3
q_b106
-1
3
q_b105
-1
3
q_b104
-1
3
q_b103
-1
3
q_b102
-1
3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a112
-1
3
data_a111
-1
3
data_a110
-1
3
data_a11
-1
3
data_a109
-1
3
data_a108
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altdpram
# storage
db|aurora_8b10b_v5_2_example_design.(93).cnf
db|aurora_8b10b_v5_2_example_design.(93).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altdpram.tdf
2c2259fdcccd62fa8105010b956d34
7
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
WIDTH
19
PARAMETER_SIGNED_DEC
USR
WIDTHAD
1
PARAMETER_SIGNED_DEC
USR
NUMWORDS
0
PARAMETER_SIGNED_DEC
USR
FILE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
DEF
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
BYTE_SIZE
0
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA
1
PARAMETER_SIGNED_DEC
USR
DISABLE_LE_RAM_LIMIT_CHECK
on
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
-1
3
wraddress0
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclocken
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
lpm_mux
# storage
db|aurora_8b10b_v5_2_example_design.(94).cnf
db|aurora_8b10b_v5_2_example_design.(94).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_mux.tdf
d2c33760a4359bf0707ac9e7afb311f2
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
19
PARAMETER_UNKNOWN
USR
LPM_SIZE
2
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_tpc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
}
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data1_9
-1
3
data1_8
-1
3
data1_7
-1
3
data1_6
-1
3
data1_5
-1
3
data1_4
-1
3
data1_3
-1
3
data1_2
-1
3
data1_18
-1
3
data1_17
-1
3
data1_16
-1
3
data1_15
-1
3
data1_14
-1
3
data1_13
-1
3
data1_12
-1
3
data1_11
-1
3
data1_10
-1
3
data1_1
-1
3
data1_0
-1
3
data0_9
-1
3
data0_8
-1
3
data0_7
-1
3
data0_6
-1
3
data0_5
-1
3
data0_4
-1
3
data0_3
-1
3
data0_2
-1
3
data0_18
-1
3
data0_17
-1
3
data0_16
-1
3
data0_15
-1
3
data0_14
-1
3
data0_13
-1
3
data0_12
-1
3
data0_11
-1
3
data0_10
-1
3
data0_1
-1
3
data0_0
-1
3
}
# macro_sequence

# end
# entity
mux_tpc
# storage
db|aurora_8b10b_v5_2_example_design.(95).cnf
db|aurora_8b10b_v5_2_example_design.(95).cnf
# case_insensitive
# source_file
db|mux_tpc.tdf
c548d2c2cff026bfd998908dceb0cac0
7
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data37
-1
3
data36
-1
3
data35
-1
3
data34
-1
3
data33
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(96).cnf
db|aurora_8b10b_v5_2_example_design.(96).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
512
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
9
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
113
PARAMETER_SIGNED_DEC
USR
status_bits
19
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
7
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
112 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
18 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
8 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(97).cnf
db|aurora_8b10b_v5_2_example_design.(97).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
9
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
512
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_e3j
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
CLK_EN
-1
3
}
# macro_sequence

# end
# entity
cntr_e3j
# storage
db|aurora_8b10b_v5_2_example_design.(98).cnf
db|aurora_8b10b_v5_2_example_design.(98).cnf
# case_insensitive
# source_file
db|cntr_e3j.tdf
36c295ebd6a46459e327ad3f4b791d1c
7
# used_port {
sclr
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(99).cnf
db|aurora_8b10b_v5_2_example_design.(99).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
19
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
ENABLE
-1
2
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(100).cnf
db|aurora_8b10b_v5_2_example_design.(100).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
5
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
19
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_idi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_idi
# storage
db|aurora_8b10b_v5_2_example_design.(101).cnf
db|aurora_8b10b_v5_2_example_design.(101).cnf
# case_insensitive
# source_file
db|cntr_idi.tdf
224a6f8249d06462e78654f726cd3b6
7
# used_port {
sclr
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_odc
# storage
db|aurora_8b10b_v5_2_example_design.(102).cnf
db|aurora_8b10b_v5_2_example_design.(102).cnf
# case_insensitive
# source_file
db|cmpr_odc.tdf
b5a8fd1152ae30674532ca5d75349
7
# used_port {
datab3
-1
3
datab2
-1
3
datab0
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab4
-1
2
datab1
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(103).cnf
db|aurora_8b10b_v5_2_example_design.(103).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
19
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(104).cnf
db|aurora_8b10b_v5_2_example_design.(104).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
113
PARAMETER_UNKNOWN
USR
sld_trigger_bits
113
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
42041
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
18035
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
256
PARAMETER_UNKNOWN
USR
sld_segment_size
256
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
361
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(105).cnf
db|aurora_8b10b_v5_2_example_design.(105).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
113
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
113
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
42041
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
18035
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
256
PARAMETER_SIGNED_DEC
USR
sld_segment_size
256
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
361
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 360
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
112 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
112 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(106).cnf
db|aurora_8b10b_v5_2_example_design.(106).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
113
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
8
PARAMETER_SIGNED_DEC
USR
sample_depth
256
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
8
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
360 downto 360
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
112 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
7 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_trigger_flow_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(107).cnf
db|aurora_8b10b_v5_2_example_design.(107).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_trigger_flow_mgr.vhd
54b4e96651b97ec28a57c8b6d87fce
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
segment_size_bits
8
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(condition_met)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
7 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_buffer_manager
# storage
db|aurora_8b10b_v5_2_example_design.(108).cnf
db|aurora_8b10b_v5_2_example_design.(108).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
address_bits
8
PARAMETER_SIGNED_DEC
USR
segment_size_bits
8
PARAMETER_SIGNED_DEC
USR
num_segments_bits
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(address)
7 downto 0
PARAMETER_STRING
USR
 constraint(post_count)
7 downto 0
PARAMETER_STRING
USR
 constraint(current_segment)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_offset)
7 downto 0
PARAMETER_STRING
USR
 constraint(last_trigger_address)
7 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
7 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
7 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(109).cnf
db|aurora_8b10b_v5_2_example_design.(109).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
8
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(110).cnf
db|aurora_8b10b_v5_2_example_design.(110).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
113
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
113
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_1p14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b99
-1
3
q_b98
-1
3
q_b97
-1
3
q_b96
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b112
-1
3
q_b111
-1
3
q_b110
-1
3
q_b11
-1
3
q_b109
-1
3
q_b108
-1
3
q_b107
-1
3
q_b106
-1
3
q_b105
-1
3
q_b104
-1
3
q_b103
-1
3
q_b102
-1
3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a112
-1
3
data_a111
-1
3
data_a110
-1
3
data_a11
-1
3
data_a109
-1
3
data_a108
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_1p14
# storage
db|aurora_8b10b_v5_2_example_design.(111).cnf
db|aurora_8b10b_v5_2_example_design.(111).cnf
# case_insensitive
# source_file
db|altsyncram_1p14.tdf
d136ccea2bcedfa4f9c3cf03a3515ce
7
# used_port {
wren_a
-1
3
q_b99
-1
3
q_b98
-1
3
q_b97
-1
3
q_b96
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b112
-1
3
q_b111
-1
3
q_b110
-1
3
q_b11
-1
3
q_b109
-1
3
q_b108
-1
3
q_b107
-1
3
q_b106
-1
3
q_b105
-1
3
q_b104
-1
3
q_b103
-1
3
q_b102
-1
3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a112
-1
3
data_a111
-1
3
data_a110
-1
3
data_a11
-1
3
data_a109
-1
3
data_a108
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altdpram
# storage
db|aurora_8b10b_v5_2_example_design.(112).cnf
db|aurora_8b10b_v5_2_example_design.(112).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altdpram.tdf
2c2259fdcccd62fa8105010b956d34
7
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
WIDTH
17
PARAMETER_SIGNED_DEC
USR
WIDTHAD
1
PARAMETER_SIGNED_DEC
USR
NUMWORDS
0
PARAMETER_SIGNED_DEC
USR
FILE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
DEF
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
BYTE_SIZE
0
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA
1
PARAMETER_SIGNED_DEC
USR
DISABLE_LE_RAM_LIMIT_CHECK
on
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
-1
3
wraddress0
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclocken
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
lpm_mux
# storage
db|aurora_8b10b_v5_2_example_design.(113).cnf
db|aurora_8b10b_v5_2_example_design.(113).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_mux.tdf
d2c33760a4359bf0707ac9e7afb311f2
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
17
PARAMETER_UNKNOWN
USR
LPM_SIZE
2
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_rpc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
}
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data1_9
-1
3
data1_8
-1
3
data1_7
-1
3
data1_6
-1
3
data1_5
-1
3
data1_4
-1
3
data1_3
-1
3
data1_2
-1
3
data1_16
-1
3
data1_15
-1
3
data1_14
-1
3
data1_13
-1
3
data1_12
-1
3
data1_11
-1
3
data1_10
-1
3
data1_1
-1
3
data1_0
-1
3
data0_9
-1
3
data0_8
-1
3
data0_7
-1
3
data0_6
-1
3
data0_5
-1
3
data0_4
-1
3
data0_3
-1
3
data0_2
-1
3
data0_16
-1
3
data0_15
-1
3
data0_14
-1
3
data0_13
-1
3
data0_12
-1
3
data0_11
-1
3
data0_10
-1
3
data0_1
-1
3
data0_0
-1
3
}
# macro_sequence

# end
# entity
mux_rpc
# storage
db|aurora_8b10b_v5_2_example_design.(114).cnf
db|aurora_8b10b_v5_2_example_design.(114).cnf
# case_insensitive
# source_file
db|mux_rpc.tdf
7bd2be4ba919be59195c329587a92
7
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data33
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(115).cnf
db|aurora_8b10b_v5_2_example_design.(115).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
256
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
8
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
113
PARAMETER_SIGNED_DEC
USR
status_bits
17
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
7
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
112 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
16 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
7 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
7 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
7 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(116).cnf
db|aurora_8b10b_v5_2_example_design.(116).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
8
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
256
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_i3j
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
CLK_EN
-1
3
}
# macro_sequence

# end
# entity
cntr_i3j
# storage
db|aurora_8b10b_v5_2_example_design.(117).cnf
db|aurora_8b10b_v5_2_example_design.(117).cnf
# case_insensitive
# source_file
db|cntr_i3j.tdf
c4c0133fbfa0a1e89ada3339bfa0ebd4
7
# used_port {
sclr
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(118).cnf
db|aurora_8b10b_v5_2_example_design.(118).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
17
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
ENABLE
-1
2
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(119).cnf
db|aurora_8b10b_v5_2_example_design.(119).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
5
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
17
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_jdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_jdi
# storage
db|aurora_8b10b_v5_2_example_design.(120).cnf
db|aurora_8b10b_v5_2_example_design.(120).cnf
# case_insensitive
# source_file
db|cntr_jdi.tdf
58e727c4b11aa4d9606e72d3a2b84c89
7
# used_port {
sclr
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_odc
# storage
db|aurora_8b10b_v5_2_example_design.(121).cnf
db|aurora_8b10b_v5_2_example_design.(121).cnf
# case_insensitive
# source_file
db|cmpr_odc.tdf
b5a8fd1152ae30674532ca5d75349
7
# used_port {
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab4
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(122).cnf
db|aurora_8b10b_v5_2_example_design.(122).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
17
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
PLL_LA
# storage
db|aurora_8b10b_v5_2_example_design.(1).cnf
db|aurora_8b10b_v5_2_example_design.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
pll_la.vhd
9ed7228c206cebf634ea76d2c5b536d
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
PLL_LA:LA_PLL
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altpll
# storage
db|aurora_8b10b_v5_2_example_design.(123).cnf
db|aurora_8b10b_v5_2_example_design.(123).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altpll.tdf
86b75138429c7354c383e2cca01ca9f6
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
LPM_HINT
CBX_MODULE_PREFIX=PLL_LA
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
6400
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
USR
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
2
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
PLL_LA_altpll
PARAMETER_UNKNOWN
USR
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
10
PARAMETER_SIGNED_DEC
USR
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk0
-1
3
clk0
-1
3
inclk1
-1
1
}
# macro_sequence

# end
# entity
PLL_LA_altpll
# storage
db|aurora_8b10b_v5_2_example_design.(124).cnf
db|aurora_8b10b_v5_2_example_design.(124).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
db|pll_la_altpll.v
28de7b3aeebb28d2227f7ea85e4d0c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
PLL_LA:LA_PLL|altpll:altpll_component|PLL_LA_altpll:auto_generated
}
# macro_sequence
ALTERA_RESERVED_QISALTERA_RESERVED_QIS
# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(125).cnf
db|aurora_8b10b_v5_2_example_design.(125).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
16
PARAMETER_UNKNOWN
USR
sld_trigger_bits
16
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
53553
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
57874
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
1024
PARAMETER_UNKNOWN
USR
sld_segment_size
1024
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
72
PARAMETER_UNKNOWN
USR
sld_inversion_mask
000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(126).cnf
db|aurora_8b10b_v5_2_example_design.(126).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
16
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
16
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
53553
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
57874
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
1024
PARAMETER_SIGNED_DEC
USR
sld_segment_size
1024
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
72
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 71
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
15 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
15 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
15 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
15 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(127).cnf
db|aurora_8b10b_v5_2_example_design.(127).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
16
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
10
PARAMETER_SIGNED_DEC
USR
sample_depth
1024
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
10
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
71 downto 71
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
15 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
9 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(128).cnf
db|aurora_8b10b_v5_2_example_design.(128).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
16
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
15 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(129).cnf
db|aurora_8b10b_v5_2_example_design.(129).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
48
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q32
-1
3
Q31
-1
3
Q30
-1
3
Q3
-1
3
Q29
-1
3
Q28
-1
3
Q27
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q22
-1
3
Q21
-1
3
Q20
-1
3
Q2
-1
3
Q19
-1
3
Q18
-1
3
Q17
-1
3
Q16
-1
3
Q15
-1
3
Q14
-1
3
Q13
-1
3
Q12
-1
3
Q11
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(130).cnf
db|aurora_8b10b_v5_2_example_design.(130).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
16
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
15 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
47 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_trigger_flow_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(131).cnf
db|aurora_8b10b_v5_2_example_design.(131).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_trigger_flow_mgr.vhd
54b4e96651b97ec28a57c8b6d87fce
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
segment_size_bits
10
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(condition_met)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
9 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_buffer_manager
# storage
db|aurora_8b10b_v5_2_example_design.(132).cnf
db|aurora_8b10b_v5_2_example_design.(132).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
address_bits
10
PARAMETER_SIGNED_DEC
USR
segment_size_bits
10
PARAMETER_SIGNED_DEC
USR
num_segments_bits
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(address)
9 downto 0
PARAMETER_STRING
USR
 constraint(post_count)
9 downto 0
PARAMETER_STRING
USR
 constraint(current_segment)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_offset)
9 downto 0
PARAMETER_STRING
USR
 constraint(last_trigger_address)
9 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
9 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
9 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(133).cnf
db|aurora_8b10b_v5_2_example_design.(133).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
10
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(134).cnf
db|aurora_8b10b_v5_2_example_design.(134).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_no14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_no14
# storage
db|aurora_8b10b_v5_2_example_design.(135).cnf
db|aurora_8b10b_v5_2_example_design.(135).cnf
# case_insensitive
# source_file
db|altsyncram_no14.tdf
b1dad7d39e6b1625fbb839deaa74d32
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altdpram
# storage
db|aurora_8b10b_v5_2_example_design.(136).cnf
db|aurora_8b10b_v5_2_example_design.(136).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altdpram.tdf
2c2259fdcccd62fa8105010b956d34
7
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
WIDTH
21
PARAMETER_SIGNED_DEC
USR
WIDTHAD
1
PARAMETER_SIGNED_DEC
USR
NUMWORDS
0
PARAMETER_SIGNED_DEC
USR
FILE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
DEF
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
BYTE_SIZE
0
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA
1
PARAMETER_SIGNED_DEC
USR
DISABLE_LE_RAM_LIMIT_CHECK
on
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
-1
3
wraddress0
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclocken
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
lpm_mux
# storage
db|aurora_8b10b_v5_2_example_design.(137).cnf
db|aurora_8b10b_v5_2_example_design.(137).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_mux.tdf
d2c33760a4359bf0707ac9e7afb311f2
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
21
PARAMETER_UNKNOWN
USR
LPM_SIZE
2
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_mpc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
}
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data1_9
-1
3
data1_8
-1
3
data1_7
-1
3
data1_6
-1
3
data1_5
-1
3
data1_4
-1
3
data1_3
-1
3
data1_20
-1
3
data1_2
-1
3
data1_19
-1
3
data1_18
-1
3
data1_17
-1
3
data1_16
-1
3
data1_15
-1
3
data1_14
-1
3
data1_13
-1
3
data1_12
-1
3
data1_11
-1
3
data1_10
-1
3
data1_1
-1
3
data1_0
-1
3
data0_9
-1
3
data0_8
-1
3
data0_7
-1
3
data0_6
-1
3
data0_5
-1
3
data0_4
-1
3
data0_3
-1
3
data0_20
-1
3
data0_2
-1
3
data0_19
-1
3
data0_18
-1
3
data0_17
-1
3
data0_16
-1
3
data0_15
-1
3
data0_14
-1
3
data0_13
-1
3
data0_12
-1
3
data0_11
-1
3
data0_10
-1
3
data0_1
-1
3
data0_0
-1
3
}
# macro_sequence

# end
# entity
mux_mpc
# storage
db|aurora_8b10b_v5_2_example_design.(138).cnf
db|aurora_8b10b_v5_2_example_design.(138).cnf
# case_insensitive
# source_file
db|mux_mpc.tdf
ab731373476a68dcebec22b739979fc8
7
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data41
-1
3
data40
-1
3
data4
-1
3
data39
-1
3
data38
-1
3
data37
-1
3
data36
-1
3
data35
-1
3
data34
-1
3
data33
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(139).cnf
db|aurora_8b10b_v5_2_example_design.(139).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
1024
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
10
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
16
PARAMETER_SIGNED_DEC
USR
status_bits
21
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
15 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
20 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
9 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
9 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
9 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(140).cnf
db|aurora_8b10b_v5_2_example_design.(140).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
16
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_cdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_cdi
# storage
db|aurora_8b10b_v5_2_example_design.(141).cnf
db|aurora_8b10b_v5_2_example_design.(141).cnf
# case_insensitive
# source_file
db|cntr_cdi.tdf
fa73bfbc1b1e858887ef898fa3b2d5
7
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(142).cnf
db|aurora_8b10b_v5_2_example_design.(142).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
10
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
1024
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_56j
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
CLK_EN
-1
3
}
# macro_sequence

# end
# entity
cntr_56j
# storage
db|aurora_8b10b_v5_2_example_design.(143).cnf
db|aurora_8b10b_v5_2_example_design.(143).cnf
# case_insensitive
# source_file
db|cntr_56j.tdf
f18bf056d18757d3d37cf0dd6cafdf2a
7
# used_port {
sclr
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(144).cnf
db|aurora_8b10b_v5_2_example_design.(144).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
16
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(145).cnf
db|aurora_8b10b_v5_2_example_design.(145).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
21
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
ENABLE
-1
2
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(146).cnf
db|aurora_8b10b_v5_2_example_design.(146).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
5
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
21
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_9di
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_9di
# storage
db|aurora_8b10b_v5_2_example_design.(147).cnf
db|aurora_8b10b_v5_2_example_design.(147).cnf
# case_insensitive
# source_file
db|cntr_9di.tdf
2273cac428184c705a22ef769a57e
7
# used_port {
sclr
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_odc
# storage
db|aurora_8b10b_v5_2_example_design.(148).cnf
db|aurora_8b10b_v5_2_example_design.(148).cnf
# case_insensitive
# source_file
db|cmpr_odc.tdf
b5a8fd1152ae30674532ca5d75349
7
# used_port {
datab3
-1
3
datab1
-1
3
datab0
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab4
-1
2
datab2
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(149).cnf
db|aurora_8b10b_v5_2_example_design.(149).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
21
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(3).cnf
db|aurora_8b10b_v5_2_example_design.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
16
PARAMETER_UNKNOWN
USR
sld_trigger_bits
16
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
39011
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
57874
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
64
PARAMETER_UNKNOWN
USR
sld_segment_size
64
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
68
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(150).cnf
db|aurora_8b10b_v5_2_example_design.(150).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
16
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
16
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
39011
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
57874
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
64
PARAMETER_SIGNED_DEC
USR
sld_segment_size
64
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
68
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 67
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
15 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
15 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
15 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
15 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(151).cnf
db|aurora_8b10b_v5_2_example_design.(151).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
16
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
sample_depth
64
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
67 downto 67
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
15 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_trigger_flow_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(152).cnf
db|aurora_8b10b_v5_2_example_design.(152).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_trigger_flow_mgr.vhd
54b4e96651b97ec28a57c8b6d87fce
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(condition_met)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_buffer_manager
# storage
db|aurora_8b10b_v5_2_example_design.(153).cnf
db|aurora_8b10b_v5_2_example_design.(153).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
address_bits
6
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
num_segments_bits
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(address)
5 downto 0
PARAMETER_STRING
USR
 constraint(post_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_segment)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_offset)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_trigger_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
5 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(154).cnf
db|aurora_8b10b_v5_2_example_design.(154).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
6
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(155).cnf
db|aurora_8b10b_v5_2_example_design.(155).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
16
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_1m14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_1m14
# storage
db|aurora_8b10b_v5_2_example_design.(156).cnf
db|aurora_8b10b_v5_2_example_design.(156).cnf
# case_insensitive
# source_file
db|altsyncram_1m14.tdf
53b39fc7f5fcc4afd7966a96a62f23dc
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altdpram
# storage
db|aurora_8b10b_v5_2_example_design.(157).cnf
db|aurora_8b10b_v5_2_example_design.(157).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altdpram.tdf
2c2259fdcccd62fa8105010b956d34
7
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
WIDTH
13
PARAMETER_SIGNED_DEC
USR
WIDTHAD
1
PARAMETER_SIGNED_DEC
USR
NUMWORDS
0
PARAMETER_SIGNED_DEC
USR
FILE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
DEF
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
BYTE_SIZE
0
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA
1
PARAMETER_SIGNED_DEC
USR
DISABLE_LE_RAM_LIMIT_CHECK
on
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
-1
3
wraddress0
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclocken
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
lpm_mux
# storage
db|aurora_8b10b_v5_2_example_design.(158).cnf
db|aurora_8b10b_v5_2_example_design.(158).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_mux.tdf
d2c33760a4359bf0707ac9e7afb311f2
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
13
PARAMETER_UNKNOWN
USR
LPM_SIZE
2
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_npc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
}
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data1_9
-1
3
data1_8
-1
3
data1_7
-1
3
data1_6
-1
3
data1_5
-1
3
data1_4
-1
3
data1_3
-1
3
data1_2
-1
3
data1_12
-1
3
data1_11
-1
3
data1_10
-1
3
data1_1
-1
3
data1_0
-1
3
data0_9
-1
3
data0_8
-1
3
data0_7
-1
3
data0_6
-1
3
data0_5
-1
3
data0_4
-1
3
data0_3
-1
3
data0_2
-1
3
data0_12
-1
3
data0_11
-1
3
data0_10
-1
3
data0_1
-1
3
data0_0
-1
3
}
# macro_sequence

# end
# entity
mux_npc
# storage
db|aurora_8b10b_v5_2_example_design.(159).cnf
db|aurora_8b10b_v5_2_example_design.(159).cnf
# case_insensitive
# source_file
db|mux_npc.tdf
365e2054a49e84247a5bc2124ff2b71
7
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(160).cnf
db|aurora_8b10b_v5_2_example_design.(160).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
64
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
16
PARAMETER_SIGNED_DEC
USR
status_bits
13
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
15 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
12 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(161).cnf
db|aurora_8b10b_v5_2_example_design.(161).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
6
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
64
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_t1j
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
CLK_EN
-1
3
}
# macro_sequence

# end
# entity
cntr_t1j
# storage
db|aurora_8b10b_v5_2_example_design.(162).cnf
db|aurora_8b10b_v5_2_example_design.(162).cnf
# case_insensitive
# source_file
db|cntr_t1j.tdf
a2cd5f5c522d46fed130b84921cfb4c5
7
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
clk_en
-1
3
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(163).cnf
db|aurora_8b10b_v5_2_example_design.(163).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
13
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
ENABLE
-1
2
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(164).cnf
db|aurora_8b10b_v5_2_example_design.(164).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
13
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_adi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_adi
# storage
db|aurora_8b10b_v5_2_example_design.(165).cnf
db|aurora_8b10b_v5_2_example_design.(165).cnf
# case_insensitive
# source_file
db|cntr_adi.tdf
57ad18a5a2ad62507b6f92838bd9ec1c
7
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_ndc
# storage
db|aurora_8b10b_v5_2_example_design.(166).cnf
db|aurora_8b10b_v5_2_example_design.(166).cnf
# case_insensitive
# source_file
db|cmpr_ndc.tdf
495846b521707960f0f941d5a9e0d354
7
# used_port {
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab3
-1
2
datab2
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(167).cnf
db|aurora_8b10b_v5_2_example_design.(167).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
13
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(168).cnf
db|aurora_8b10b_v5_2_example_design.(168).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
108
PARAMETER_UNKNOWN
USR
sld_trigger_bits
108
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
17584
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
8650
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
64
PARAMETER_UNKNOWN
USR
sld_segment_size
64
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
344
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(169).cnf
db|aurora_8b10b_v5_2_example_design.(169).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
108
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
108
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
17584
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
8650
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
64
PARAMETER_SIGNED_DEC
USR
sld_segment_size
64
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
344
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 343
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
107 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
107 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
107 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
107 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(170).cnf
db|aurora_8b10b_v5_2_example_design.(170).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
108
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
sample_depth
64
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
343 downto 343
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
107 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(171).cnf
db|aurora_8b10b_v5_2_example_design.(171).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
108
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
107 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(172).cnf
db|aurora_8b10b_v5_2_example_design.(172).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
324
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q99
-1
3
Q98
-1
3
Q97
-1
3
Q96
-1
3
Q95
-1
3
Q94
-1
3
Q93
-1
3
Q92
-1
3
Q91
-1
3
Q90
-1
3
Q9
-1
3
Q89
-1
3
Q88
-1
3
Q87
-1
3
Q86
-1
3
Q85
-1
3
Q84
-1
3
Q83
-1
3
Q82
-1
3
Q81
-1
3
Q80
-1
3
Q8
-1
3
Q79
-1
3
Q78
-1
3
Q77
-1
3
Q76
-1
3
Q75
-1
3
Q74
-1
3
Q73
-1
3
Q72
-1
3
Q71
-1
3
Q70
-1
3
Q7
-1
3
Q69
-1
3
Q68
-1
3
Q67
-1
3
Q66
-1
3
Q65
-1
3
Q64
-1
3
Q63
-1
3
Q62
-1
3
Q61
-1
3
Q60
-1
3
Q6
-1
3
Q59
-1
3
Q58
-1
3
Q57
-1
3
Q56
-1
3
Q55
-1
3
Q54
-1
3
Q53
-1
3
Q52
-1
3
Q51
-1
3
Q50
-1
3
Q5
-1
3
Q49
-1
3
Q48
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q323
-1
3
Q322
-1
3
Q321
-1
3
Q320
-1
3
Q32
-1
3
Q319
-1
3
Q318
-1
3
Q317
-1
3
Q316
-1
3
Q315
-1
3
Q314
-1
3
Q313
-1
3
Q312
-1
3
Q311
-1
3
Q310
-1
3
Q31
-1
3
Q309
-1
3
Q308
-1
3
Q307
-1
3
Q306
-1
3
Q305
-1
3
Q304
-1
3
Q303
-1
3
Q302
-1
3
Q301
-1
3
Q300
-1
3
Q30
-1
3
Q3
-1
3
Q299
-1
3
Q298
-1
3
Q297
-1
3
Q296
-1
3
Q295
-1
3
Q294
-1
3
Q293
-1
3
Q292
-1
3
Q291
-1
3
Q290
-1
3
Q29
-1
3
Q289
-1
3
Q288
-1
3
Q287
-1
3
Q286
-1
3
Q285
-1
3
Q284
-1
3
Q283
-1
3
Q282
-1
3
Q281
-1
3
Q280
-1
3
Q28
-1
3
Q279
-1
3
Q278
-1
3
Q277
-1
3
Q276
-1
3
Q275
-1
3
Q274
-1
3
Q273
-1
3
Q272
-1
3
Q271
-1
3
Q270
-1
3
Q27
-1
3
Q269
-1
3
Q268
-1
3
Q267
-1
3
Q266
-1
3
Q265
-1
3
Q264
-1
3
Q263
-1
3
Q262
-1
3
Q261
-1
3
Q260
-1
3
Q26
-1
3
Q259
-1
3
Q258
-1
3
Q257
-1
3
Q256
-1
3
Q255
-1
3
Q254
-1
3
Q253
-1
3
Q252
-1
3
Q251
-1
3
Q250
-1
3
Q25
-1
3
Q249
-1
3
Q248
-1
3
Q247
-1
3
Q246
-1
3
Q245
-1
3
Q244
-1
3
Q243
-1
3
Q242
-1
3
Q241
-1
3
Q240
-1
3
Q24
-1
3
Q239
-1
3
Q238
-1
3
Q237
-1
3
Q236
-1
3
Q235
-1
3
Q234
-1
3
Q233
-1
3
Q232
-1
3
Q231
-1
3
Q230
-1
3
Q23
-1
3
Q229
-1
3
Q228
-1
3
Q227
-1
3
Q226
-1
3
Q225
-1
3
Q224
-1
3
Q223
-1
3
Q222
-1
3
Q221
-1
3
Q220
-1
3
Q22
-1
3
Q219
-1
3
Q218
-1
3
Q217
-1
3
Q216
-1
3
Q215
-1
3
Q214
-1
3
Q213
-1
3
Q212
-1
3
Q211
-1
3
Q210
-1
3
Q21
-1
3
Q209
-1
3
Q208
-1
3
Q207
-1
3
Q206
-1
3
Q205
-1
3
Q204
-1
3
Q203
-1
3
Q202
-1
3
Q201
-1
3
Q200
-1
3
Q20
-1
3
Q2
-1
3
Q199
-1
3
Q198
-1
3
Q197
-1
3
Q196
-1
3
Q195
-1
3
Q194
-1
3
Q193
-1
3
Q192
-1
3
Q191
-1
3
Q190
-1
3
Q19
-1
3
Q189
-1
3
Q188
-1
3
Q187
-1
3
Q186
-1
3
Q185
-1
3
Q184
-1
3
Q183
-1
3
Q182
-1
3
Q181
-1
3
Q180
-1
3
Q18
-1
3
Q179
-1
3
Q178
-1
3
Q177
-1
3
Q176
-1
3
Q175
-1
3
Q174
-1
3
Q173
-1
3
Q172
-1
3
Q171
-1
3
Q170
-1
3
Q17
-1
3
Q169
-1
3
Q168
-1
3
Q167
-1
3
Q166
-1
3
Q165
-1
3
Q164
-1
3
Q163
-1
3
Q162
-1
3
Q161
-1
3
Q160
-1
3
Q16
-1
3
Q159
-1
3
Q158
-1
3
Q157
-1
3
Q156
-1
3
Q155
-1
3
Q154
-1
3
Q153
-1
3
Q152
-1
3
Q151
-1
3
Q150
-1
3
Q15
-1
3
Q149
-1
3
Q148
-1
3
Q147
-1
3
Q146
-1
3
Q145
-1
3
Q144
-1
3
Q143
-1
3
Q142
-1
3
Q141
-1
3
Q140
-1
3
Q14
-1
3
Q139
-1
3
Q138
-1
3
Q137
-1
3
Q136
-1
3
Q135
-1
3
Q134
-1
3
Q133
-1
3
Q132
-1
3
Q131
-1
3
Q130
-1
3
Q13
-1
3
Q129
-1
3
Q128
-1
3
Q127
-1
3
Q126
-1
3
Q125
-1
3
Q124
-1
3
Q123
-1
3
Q122
-1
3
Q121
-1
3
Q120
-1
3
Q12
-1
3
Q119
-1
3
Q118
-1
3
Q117
-1
3
Q116
-1
3
Q115
-1
3
Q114
-1
3
Q113
-1
3
Q112
-1
3
Q111
-1
3
Q110
-1
3
Q11
-1
3
Q109
-1
3
Q108
-1
3
Q107
-1
3
Q106
-1
3
Q105
-1
3
Q104
-1
3
Q103
-1
3
Q102
-1
3
Q101
-1
3
Q100
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(173).cnf
db|aurora_8b10b_v5_2_example_design.(173).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
108
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
107 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
323 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(174).cnf
db|aurora_8b10b_v5_2_example_design.(174).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
108
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
108
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_5p14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b99
-1
3
q_b98
-1
3
q_b97
-1
3
q_b96
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b107
-1
3
q_b106
-1
3
q_b105
-1
3
q_b104
-1
3
q_b103
-1
3
q_b102
-1
3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_5p14
# storage
db|aurora_8b10b_v5_2_example_design.(175).cnf
db|aurora_8b10b_v5_2_example_design.(175).cnf
# case_insensitive
# source_file
db|altsyncram_5p14.tdf
d51f96d1cd34fc84214eeb397c79d3b
7
# used_port {
wren_a
-1
3
q_b99
-1
3
q_b98
-1
3
q_b97
-1
3
q_b96
-1
3
q_b95
-1
3
q_b94
-1
3
q_b93
-1
3
q_b92
-1
3
q_b91
-1
3
q_b90
-1
3
q_b9
-1
3
q_b89
-1
3
q_b88
-1
3
q_b87
-1
3
q_b86
-1
3
q_b85
-1
3
q_b84
-1
3
q_b83
-1
3
q_b82
-1
3
q_b81
-1
3
q_b80
-1
3
q_b8
-1
3
q_b79
-1
3
q_b78
-1
3
q_b77
-1
3
q_b76
-1
3
q_b75
-1
3
q_b74
-1
3
q_b73
-1
3
q_b72
-1
3
q_b71
-1
3
q_b70
-1
3
q_b7
-1
3
q_b69
-1
3
q_b68
-1
3
q_b67
-1
3
q_b66
-1
3
q_b65
-1
3
q_b64
-1
3
q_b63
-1
3
q_b62
-1
3
q_b61
-1
3
q_b60
-1
3
q_b6
-1
3
q_b59
-1
3
q_b58
-1
3
q_b57
-1
3
q_b56
-1
3
q_b55
-1
3
q_b54
-1
3
q_b53
-1
3
q_b52
-1
3
q_b51
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b107
-1
3
q_b106
-1
3
q_b105
-1
3
q_b104
-1
3
q_b103
-1
3
q_b102
-1
3
q_b101
-1
3
q_b100
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a99
-1
3
data_a98
-1
3
data_a97
-1
3
data_a96
-1
3
data_a95
-1
3
data_a94
-1
3
data_a93
-1
3
data_a92
-1
3
data_a91
-1
3
data_a90
-1
3
data_a9
-1
3
data_a89
-1
3
data_a88
-1
3
data_a87
-1
3
data_a86
-1
3
data_a85
-1
3
data_a84
-1
3
data_a83
-1
3
data_a82
-1
3
data_a81
-1
3
data_a80
-1
3
data_a8
-1
3
data_a79
-1
3
data_a78
-1
3
data_a77
-1
3
data_a76
-1
3
data_a75
-1
3
data_a74
-1
3
data_a73
-1
3
data_a72
-1
3
data_a71
-1
3
data_a70
-1
3
data_a7
-1
3
data_a69
-1
3
data_a68
-1
3
data_a67
-1
3
data_a66
-1
3
data_a65
-1
3
data_a64
-1
3
data_a63
-1
3
data_a62
-1
3
data_a61
-1
3
data_a60
-1
3
data_a6
-1
3
data_a59
-1
3
data_a58
-1
3
data_a57
-1
3
data_a56
-1
3
data_a55
-1
3
data_a54
-1
3
data_a53
-1
3
data_a52
-1
3
data_a51
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a107
-1
3
data_a106
-1
3
data_a105
-1
3
data_a104
-1
3
data_a103
-1
3
data_a102
-1
3
data_a101
-1
3
data_a100
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(176).cnf
db|aurora_8b10b_v5_2_example_design.(176).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
64
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
108
PARAMETER_SIGNED_DEC
USR
status_bits
13
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
7
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
107 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
12 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(177).cnf
db|aurora_8b10b_v5_2_example_design.(177).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
7
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
108
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_1fi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_1fi
# storage
db|aurora_8b10b_v5_2_example_design.(178).cnf
db|aurora_8b10b_v5_2_example_design.(178).cnf
# case_insensitive
# source_file
db|cntr_1fi.tdf
8617648f3a70f1b5dc6cb5334db03332
7
# used_port {
sclr
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_qdc
# storage
db|aurora_8b10b_v5_2_example_design.(179).cnf
db|aurora_8b10b_v5_2_example_design.(179).cnf
# case_insensitive
# source_file
db|cmpr_qdc.tdf
1b1c37b9b2a89b5e2d85e3e4f229b16
7
# used_port {
datab4
-1
3
datab2
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab6
-1
2
datab5
-1
2
datab3
-1
2
datab1
-1
2
datab0
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(180).cnf
db|aurora_8b10b_v5_2_example_design.(180).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
108
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA99
-1
3
DATA98
-1
3
DATA97
-1
3
DATA96
-1
3
DATA95
-1
3
DATA94
-1
3
DATA93
-1
3
DATA92
-1
3
DATA91
-1
3
DATA90
-1
3
DATA9
-1
3
DATA89
-1
3
DATA88
-1
3
DATA87
-1
3
DATA86
-1
3
DATA85
-1
3
DATA84
-1
3
DATA83
-1
3
DATA82
-1
3
DATA81
-1
3
DATA80
-1
3
DATA8
-1
3
DATA79
-1
3
DATA78
-1
3
DATA77
-1
3
DATA76
-1
3
DATA75
-1
3
DATA74
-1
3
DATA73
-1
3
DATA72
-1
3
DATA71
-1
3
DATA70
-1
3
DATA7
-1
3
DATA69
-1
3
DATA68
-1
3
DATA67
-1
3
DATA66
-1
3
DATA65
-1
3
DATA64
-1
3
DATA63
-1
3
DATA62
-1
3
DATA61
-1
3
DATA60
-1
3
DATA6
-1
3
DATA59
-1
3
DATA58
-1
3
DATA57
-1
3
DATA56
-1
3
DATA55
-1
3
DATA54
-1
3
DATA53
-1
3
DATA52
-1
3
DATA51
-1
3
DATA50
-1
3
DATA5
-1
3
DATA49
-1
3
DATA48
-1
3
DATA47
-1
3
DATA46
-1
3
DATA45
-1
3
DATA44
-1
3
DATA43
-1
3
DATA42
-1
3
DATA41
-1
3
DATA40
-1
3
DATA4
-1
3
DATA39
-1
3
DATA38
-1
3
DATA37
-1
3
DATA36
-1
3
DATA35
-1
3
DATA34
-1
3
DATA33
-1
3
DATA32
-1
3
DATA31
-1
3
DATA30
-1
3
DATA3
-1
3
DATA29
-1
3
DATA28
-1
3
DATA27
-1
3
DATA26
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA107
-1
3
DATA106
-1
3
DATA105
-1
3
DATA104
-1
3
DATA103
-1
3
DATA102
-1
3
DATA101
-1
3
DATA100
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(181).cnf
db|aurora_8b10b_v5_2_example_design.(181).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
14
PARAMETER_UNKNOWN
USR
sld_trigger_bits
14
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
48101
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
29646
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
64
PARAMETER_UNKNOWN
USR
sld_segment_size
64
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
62
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(182).cnf
db|aurora_8b10b_v5_2_example_design.(182).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
14
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
14
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
48101
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
29646
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
64
PARAMETER_SIGNED_DEC
USR
sld_segment_size
64
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
62
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 61
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
13 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
13 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
13 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
13 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(183).cnf
db|aurora_8b10b_v5_2_example_design.(183).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
14
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
sample_depth
64
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
61 downto 61
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
13 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(184).cnf
db|aurora_8b10b_v5_2_example_design.(184).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
14
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
13 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(185).cnf
db|aurora_8b10b_v5_2_example_design.(185).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
42
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q32
-1
3
Q31
-1
3
Q30
-1
3
Q3
-1
3
Q29
-1
3
Q28
-1
3
Q27
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q22
-1
3
Q21
-1
3
Q20
-1
3
Q2
-1
3
Q19
-1
3
Q18
-1
3
Q17
-1
3
Q16
-1
3
Q15
-1
3
Q14
-1
3
Q13
-1
3
Q12
-1
3
Q11
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(186).cnf
db|aurora_8b10b_v5_2_example_design.(186).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
14
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
13 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
41 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(187).cnf
db|aurora_8b10b_v5_2_example_design.(187).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
14
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
14
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_tl14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_tl14
# storage
db|aurora_8b10b_v5_2_example_design.(188).cnf
db|aurora_8b10b_v5_2_example_design.(188).cnf
# case_insensitive
# source_file
db|altsyncram_tl14.tdf
77f3c4b4c88c074765624a086f8c387
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(189).cnf
db|aurora_8b10b_v5_2_example_design.(189).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
64
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
14
PARAMETER_SIGNED_DEC
USR
status_bits
13
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
13 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
12 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(190).cnf
db|aurora_8b10b_v5_2_example_design.(190).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
14
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_ldi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_ldi
# storage
db|aurora_8b10b_v5_2_example_design.(191).cnf
db|aurora_8b10b_v5_2_example_design.(191).cnf
# case_insensitive
# source_file
db|cntr_ldi.tdf
8e96f128da46aadaeb150b3d2abb28
7
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_ndc
# storage
db|aurora_8b10b_v5_2_example_design.(192).cnf
db|aurora_8b10b_v5_2_example_design.(192).cnf
# case_insensitive
# source_file
db|cmpr_ndc.tdf
495846b521707960f0f941d5a9e0d354
7
# used_port {
datab1
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab3
-1
2
datab2
-1
2
datab0
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(193).cnf
db|aurora_8b10b_v5_2_example_design.(193).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
14
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(194).cnf
db|aurora_8b10b_v5_2_example_design.(194).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
26
PARAMETER_UNKNOWN
USR
sld_trigger_bits
26
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
27536
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
8069
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
64
PARAMETER_UNKNOWN
USR
sld_segment_size
64
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
98
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(195).cnf
db|aurora_8b10b_v5_2_example_design.(195).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
26
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
26
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
27536
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
8069
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
64
PARAMETER_SIGNED_DEC
USR
sld_segment_size
64
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
98
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 97
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
25 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
25 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
25 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
25 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(196).cnf
db|aurora_8b10b_v5_2_example_design.(196).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
26
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
sample_depth
64
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
97 downto 97
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
25 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(197).cnf
db|aurora_8b10b_v5_2_example_design.(197).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
26
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
25 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(198).cnf
db|aurora_8b10b_v5_2_example_design.(198).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
78
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q9
-1
3
Q8
-1
3
Q77
-1
3
Q76
-1
3
Q75
-1
3
Q74
-1
3
Q73
-1
3
Q72
-1
3
Q71
-1
3
Q70
-1
3
Q7
-1
3
Q69
-1
3
Q68
-1
3
Q67
-1
3
Q66
-1
3
Q65
-1
3
Q64
-1
3
Q63
-1
3
Q62
-1
3
Q61
-1
3
Q60
-1
3
Q6
-1
3
Q59
-1
3
Q58
-1
3
Q57
-1
3
Q56
-1
3
Q55
-1
3
Q54
-1
3
Q53
-1
3
Q52
-1
3
Q51
-1
3
Q50
-1
3
Q5
-1
3
Q49
-1
3
Q48
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q32
-1
3
Q31
-1
3
Q30
-1
3
Q3
-1
3
Q29
-1
3
Q28
-1
3
Q27
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q22
-1
3
Q21
-1
3
Q20
-1
3
Q2
-1
3
Q19
-1
3
Q18
-1
3
Q17
-1
3
Q16
-1
3
Q15
-1
3
Q14
-1
3
Q13
-1
3
Q12
-1
3
Q11
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(199).cnf
db|aurora_8b10b_v5_2_example_design.(199).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
26
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
25 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
77 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(200).cnf
db|aurora_8b10b_v5_2_example_design.(200).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
26
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
26
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_3m14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_3m14
# storage
db|aurora_8b10b_v5_2_example_design.(201).cnf
db|aurora_8b10b_v5_2_example_design.(201).cnf
# case_insensitive
# source_file
db|altsyncram_3m14.tdf
9c9d685dc780de966a72387b91b51c31
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(202).cnf
db|aurora_8b10b_v5_2_example_design.(202).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
64
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
26
PARAMETER_SIGNED_DEC
USR
status_bits
13
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
25 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
12 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(203).cnf
db|aurora_8b10b_v5_2_example_design.(203).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
5
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
26
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_odi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_odi
# storage
db|aurora_8b10b_v5_2_example_design.(204).cnf
db|aurora_8b10b_v5_2_example_design.(204).cnf
# case_insensitive
# source_file
db|cntr_odi.tdf
8bbd8d508ecc851b3a27ab2d84f4d97b
7
# used_port {
sclr
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_odc
# storage
db|aurora_8b10b_v5_2_example_design.(205).cnf
db|aurora_8b10b_v5_2_example_design.(205).cnf
# case_insensitive
# source_file
db|cmpr_odc.tdf
b5a8fd1152ae30674532ca5d75349
7
# used_port {
datab2
-1
3
datab1
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab4
-1
2
datab3
-1
2
datab0
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(206).cnf
db|aurora_8b10b_v5_2_example_design.(206).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
26
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(207).cnf
db|aurora_8b10b_v5_2_example_design.(207).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
51
PARAMETER_UNKNOWN
USR
sld_trigger_bits
51
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
59501
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
55289
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
64
PARAMETER_UNKNOWN
USR
sld_segment_size
64
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
173
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(208).cnf
db|aurora_8b10b_v5_2_example_design.(208).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
51
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
51
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
59501
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
55289
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
64
PARAMETER_SIGNED_DEC
USR
sld_segment_size
64
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
173
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 172
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
50 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
50 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
50 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
50 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(209).cnf
db|aurora_8b10b_v5_2_example_design.(209).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
51
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
sample_depth
64
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
172 downto 172
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
50 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(210).cnf
db|aurora_8b10b_v5_2_example_design.(210).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
51
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
50 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(211).cnf
db|aurora_8b10b_v5_2_example_design.(211).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
153
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q99
-1
3
Q98
-1
3
Q97
-1
3
Q96
-1
3
Q95
-1
3
Q94
-1
3
Q93
-1
3
Q92
-1
3
Q91
-1
3
Q90
-1
3
Q9
-1
3
Q89
-1
3
Q88
-1
3
Q87
-1
3
Q86
-1
3
Q85
-1
3
Q84
-1
3
Q83
-1
3
Q82
-1
3
Q81
-1
3
Q80
-1
3
Q8
-1
3
Q79
-1
3
Q78
-1
3
Q77
-1
3
Q76
-1
3
Q75
-1
3
Q74
-1
3
Q73
-1
3
Q72
-1
3
Q71
-1
3
Q70
-1
3
Q7
-1
3
Q69
-1
3
Q68
-1
3
Q67
-1
3
Q66
-1
3
Q65
-1
3
Q64
-1
3
Q63
-1
3
Q62
-1
3
Q61
-1
3
Q60
-1
3
Q6
-1
3
Q59
-1
3
Q58
-1
3
Q57
-1
3
Q56
-1
3
Q55
-1
3
Q54
-1
3
Q53
-1
3
Q52
-1
3
Q51
-1
3
Q50
-1
3
Q5
-1
3
Q49
-1
3
Q48
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q32
-1
3
Q31
-1
3
Q30
-1
3
Q3
-1
3
Q29
-1
3
Q28
-1
3
Q27
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q22
-1
3
Q21
-1
3
Q20
-1
3
Q2
-1
3
Q19
-1
3
Q18
-1
3
Q17
-1
3
Q16
-1
3
Q152
-1
3
Q151
-1
3
Q150
-1
3
Q15
-1
3
Q149
-1
3
Q148
-1
3
Q147
-1
3
Q146
-1
3
Q145
-1
3
Q144
-1
3
Q143
-1
3
Q142
-1
3
Q141
-1
3
Q140
-1
3
Q14
-1
3
Q139
-1
3
Q138
-1
3
Q137
-1
3
Q136
-1
3
Q135
-1
3
Q134
-1
3
Q133
-1
3
Q132
-1
3
Q131
-1
3
Q130
-1
3
Q13
-1
3
Q129
-1
3
Q128
-1
3
Q127
-1
3
Q126
-1
3
Q125
-1
3
Q124
-1
3
Q123
-1
3
Q122
-1
3
Q121
-1
3
Q120
-1
3
Q12
-1
3
Q119
-1
3
Q118
-1
3
Q117
-1
3
Q116
-1
3
Q115
-1
3
Q114
-1
3
Q113
-1
3
Q112
-1
3
Q111
-1
3
Q110
-1
3
Q11
-1
3
Q109
-1
3
Q108
-1
3
Q107
-1
3
Q106
-1
3
Q105
-1
3
Q104
-1
3
Q103
-1
3
Q102
-1
3
Q101
-1
3
Q100
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(212).cnf
db|aurora_8b10b_v5_2_example_design.(212).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
51
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
50 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
152 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(213).cnf
db|aurora_8b10b_v5_2_example_design.(213).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
51
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
51
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_vl14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_vl14
# storage
db|aurora_8b10b_v5_2_example_design.(214).cnf
db|aurora_8b10b_v5_2_example_design.(214).cnf
# case_insensitive
# source_file
db|altsyncram_vl14.tdf
a51bc95dd1635b060a5eb45b21d5f7
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b50
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a50
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(215).cnf
db|aurora_8b10b_v5_2_example_design.(215).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
64
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
51
PARAMETER_SIGNED_DEC
USR
status_bits
13
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
6
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
50 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
12 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(216).cnf
db|aurora_8b10b_v5_2_example_design.(216).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
6
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
51
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_pdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_pdi
# storage
db|aurora_8b10b_v5_2_example_design.(217).cnf
db|aurora_8b10b_v5_2_example_design.(217).cnf
# case_insensitive
# source_file
db|cntr_pdi.tdf
6170feede95991fac2977f3b8c39f1
7
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_pdc
# storage
db|aurora_8b10b_v5_2_example_design.(218).cnf
db|aurora_8b10b_v5_2_example_design.(218).cnf
# case_insensitive
# source_file
db|cmpr_pdc.tdf
2a699a9daa415c42a9f26a5559b622aa
7
# used_port {
datab3
-1
3
datab2
-1
3
datab0
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab5
-1
2
datab4
-1
2
datab1
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(219).cnf
db|aurora_8b10b_v5_2_example_design.(219).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
51
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA50
-1
3
DATA5
-1
3
DATA49
-1
3
DATA48
-1
3
DATA47
-1
3
DATA46
-1
3
DATA45
-1
3
DATA44
-1
3
DATA43
-1
3
DATA42
-1
3
DATA41
-1
3
DATA40
-1
3
DATA4
-1
3
DATA39
-1
3
DATA38
-1
3
DATA37
-1
3
DATA36
-1
3
DATA35
-1
3
DATA34
-1
3
DATA33
-1
3
DATA32
-1
3
DATA31
-1
3
DATA30
-1
3
DATA3
-1
3
DATA29
-1
3
DATA28
-1
3
DATA27
-1
3
DATA26
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(220).cnf
db|aurora_8b10b_v5_2_example_design.(220).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
9
PARAMETER_UNKNOWN
USR
sld_trigger_bits
9
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
3933
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
41733
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
64
PARAMETER_UNKNOWN
USR
sld_segment_size
64
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
47
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(221).cnf
db|aurora_8b10b_v5_2_example_design.(221).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
9
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
9
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
3933
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
41733
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
64
PARAMETER_SIGNED_DEC
USR
sld_segment_size
64
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
47
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 46
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
8 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
8 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
8 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
8 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(222).cnf
db|aurora_8b10b_v5_2_example_design.(222).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
9
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
sample_depth
64
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
46 downto 46
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
8 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(223).cnf
db|aurora_8b10b_v5_2_example_design.(223).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
9
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
8 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(224).cnf
db|aurora_8b10b_v5_2_example_design.(224).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
27
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q22
-1
3
Q21
-1
3
Q20
-1
3
Q2
-1
3
Q19
-1
3
Q18
-1
3
Q17
-1
3
Q16
-1
3
Q15
-1
3
Q14
-1
3
Q13
-1
3
Q12
-1
3
Q11
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(225).cnf
db|aurora_8b10b_v5_2_example_design.(225).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
9
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
8 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
26 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(226).cnf
db|aurora_8b10b_v5_2_example_design.(226).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
9
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
9
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_5j14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_5j14
# storage
db|aurora_8b10b_v5_2_example_design.(227).cnf
db|aurora_8b10b_v5_2_example_design.(227).cnf
# case_insensitive
# source_file
db|altsyncram_5j14.tdf
d5a0ad02e389d046e670d9eb399abb
7
# used_port {
wren_a
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(228).cnf
db|aurora_8b10b_v5_2_example_design.(228).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
64
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
9
PARAMETER_SIGNED_DEC
USR
status_bits
13
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
8 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
12 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(229).cnf
db|aurora_8b10b_v5_2_example_design.(229).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
4
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
9
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_ubi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_ubi
# storage
db|aurora_8b10b_v5_2_example_design.(230).cnf
db|aurora_8b10b_v5_2_example_design.(230).cnf
# case_insensitive
# source_file
db|cntr_ubi.tdf
23fd1d49f728f452e75f322620bf7e90
7
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_ndc
# storage
db|aurora_8b10b_v5_2_example_design.(231).cnf
db|aurora_8b10b_v5_2_example_design.(231).cnf
# case_insensitive
# source_file
db|cmpr_ndc.tdf
495846b521707960f0f941d5a9e0d354
7
# used_port {
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab3
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(232).cnf
db|aurora_8b10b_v5_2_example_design.(232).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
9
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(233).cnf
db|aurora_8b10b_v5_2_example_design.(233).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
9
PARAMETER_UNKNOWN
USR
sld_trigger_bits
1
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
2389
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
47347
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
64
PARAMETER_UNKNOWN
USR
sld_segment_size
64
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
23
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(234).cnf
db|aurora_8b10b_v5_2_example_design.(234).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
9
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
1
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
2389
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
47347
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
64
PARAMETER_SIGNED_DEC
USR
sld_segment_size
64
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
23
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 22
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
8 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
8 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(235).cnf
db|aurora_8b10b_v5_2_example_design.(235).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
1
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
sample_depth
64
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
22 downto 22
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(236).cnf
db|aurora_8b10b_v5_2_example_design.(236).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(237).cnf
db|aurora_8b10b_v5_2_example_design.(237).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
3
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(238).cnf
db|aurora_8b10b_v5_2_example_design.(238).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
1
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
2 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(239).cnf
db|aurora_8b10b_v5_2_example_design.(239).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
50
PARAMETER_UNKNOWN
USR
sld_trigger_bits
50
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
63918
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
12778
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
64
PARAMETER_UNKNOWN
USR
sld_segment_size
64
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
170
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(240).cnf
db|aurora_8b10b_v5_2_example_design.(240).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
50
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
50
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
63918
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
12778
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
64
PARAMETER_SIGNED_DEC
USR
sld_segment_size
64
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
170
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 169
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
49 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(241).cnf
db|aurora_8b10b_v5_2_example_design.(241).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
50
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
sample_depth
64
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
6
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
169 downto 169
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
5 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(242).cnf
db|aurora_8b10b_v5_2_example_design.(242).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
50
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(243).cnf
db|aurora_8b10b_v5_2_example_design.(243).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
150
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q99
-1
3
Q98
-1
3
Q97
-1
3
Q96
-1
3
Q95
-1
3
Q94
-1
3
Q93
-1
3
Q92
-1
3
Q91
-1
3
Q90
-1
3
Q9
-1
3
Q89
-1
3
Q88
-1
3
Q87
-1
3
Q86
-1
3
Q85
-1
3
Q84
-1
3
Q83
-1
3
Q82
-1
3
Q81
-1
3
Q80
-1
3
Q8
-1
3
Q79
-1
3
Q78
-1
3
Q77
-1
3
Q76
-1
3
Q75
-1
3
Q74
-1
3
Q73
-1
3
Q72
-1
3
Q71
-1
3
Q70
-1
3
Q7
-1
3
Q69
-1
3
Q68
-1
3
Q67
-1
3
Q66
-1
3
Q65
-1
3
Q64
-1
3
Q63
-1
3
Q62
-1
3
Q61
-1
3
Q60
-1
3
Q6
-1
3
Q59
-1
3
Q58
-1
3
Q57
-1
3
Q56
-1
3
Q55
-1
3
Q54
-1
3
Q53
-1
3
Q52
-1
3
Q51
-1
3
Q50
-1
3
Q5
-1
3
Q49
-1
3
Q48
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q32
-1
3
Q31
-1
3
Q30
-1
3
Q3
-1
3
Q29
-1
3
Q28
-1
3
Q27
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q22
-1
3
Q21
-1
3
Q20
-1
3
Q2
-1
3
Q19
-1
3
Q18
-1
3
Q17
-1
3
Q16
-1
3
Q15
-1
3
Q149
-1
3
Q148
-1
3
Q147
-1
3
Q146
-1
3
Q145
-1
3
Q144
-1
3
Q143
-1
3
Q142
-1
3
Q141
-1
3
Q140
-1
3
Q14
-1
3
Q139
-1
3
Q138
-1
3
Q137
-1
3
Q136
-1
3
Q135
-1
3
Q134
-1
3
Q133
-1
3
Q132
-1
3
Q131
-1
3
Q130
-1
3
Q13
-1
3
Q129
-1
3
Q128
-1
3
Q127
-1
3
Q126
-1
3
Q125
-1
3
Q124
-1
3
Q123
-1
3
Q122
-1
3
Q121
-1
3
Q120
-1
3
Q12
-1
3
Q119
-1
3
Q118
-1
3
Q117
-1
3
Q116
-1
3
Q115
-1
3
Q114
-1
3
Q113
-1
3
Q112
-1
3
Q111
-1
3
Q110
-1
3
Q11
-1
3
Q109
-1
3
Q108
-1
3
Q107
-1
3
Q106
-1
3
Q105
-1
3
Q104
-1
3
Q103
-1
3
Q102
-1
3
Q101
-1
3
Q100
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(244).cnf
db|aurora_8b10b_v5_2_example_design.(244).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
50
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
149 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(245).cnf
db|aurora_8b10b_v5_2_example_design.(245).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
50
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
50
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
6
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_ul14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_ul14
# storage
db|aurora_8b10b_v5_2_example_design.(246).cnf
db|aurora_8b10b_v5_2_example_design.(246).cnf
# case_insensitive
# source_file
db|altsyncram_ul14.tdf
7da5dbfc6495db14c203c53a457c2cd
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(247).cnf
db|aurora_8b10b_v5_2_example_design.(247).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
64
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
6
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
50
PARAMETER_SIGNED_DEC
USR
status_bits
13
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
6
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
4
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
49 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
12 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
5 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(248).cnf
db|aurora_8b10b_v5_2_example_design.(248).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
6
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
50
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_qdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_qdi
# storage
db|aurora_8b10b_v5_2_example_design.(249).cnf
db|aurora_8b10b_v5_2_example_design.(249).cnf
# case_insensitive
# source_file
db|cntr_qdi.tdf
c9c8bbf340ed19aec8319496e8d3da
7
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_pdc
# storage
db|aurora_8b10b_v5_2_example_design.(250).cnf
db|aurora_8b10b_v5_2_example_design.(250).cnf
# case_insensitive
# source_file
db|cmpr_pdc.tdf
2a699a9daa415c42a9f26a5559b622aa
7
# used_port {
datab3
-1
3
datab2
-1
3
datab1
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab5
-1
2
datab4
-1
2
datab0
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(251).cnf
db|aurora_8b10b_v5_2_example_design.(251).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
50
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA49
-1
3
DATA48
-1
3
DATA47
-1
3
DATA46
-1
3
DATA45
-1
3
DATA44
-1
3
DATA43
-1
3
DATA42
-1
3
DATA41
-1
3
DATA40
-1
3
DATA4
-1
3
DATA39
-1
3
DATA38
-1
3
DATA37
-1
3
DATA36
-1
3
DATA35
-1
3
DATA34
-1
3
DATA33
-1
3
DATA32
-1
3
DATA31
-1
3
DATA30
-1
3
DATA3
-1
3
DATA29
-1
3
DATA28
-1
3
DATA27
-1
3
DATA26
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(252).cnf
db|aurora_8b10b_v5_2_example_design.(252).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
50
PARAMETER_UNKNOWN
USR
sld_trigger_bits
50
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
64556
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
12778
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
1024
PARAMETER_UNKNOWN
USR
sld_segment_size
1024
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
174
PARAMETER_UNKNOWN
USR
sld_inversion_mask
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(253).cnf
db|aurora_8b10b_v5_2_example_design.(253).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
50
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
50
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
64556
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
12778
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
1024
PARAMETER_SIGNED_DEC
USR
sld_segment_size
1024
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
174
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 173
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
49 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(254).cnf
db|aurora_8b10b_v5_2_example_design.(254).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
50
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
10
PARAMETER_SIGNED_DEC
USR
sample_depth
1024
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
10
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
173 downto 173
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
9 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(255).cnf
db|aurora_8b10b_v5_2_example_design.(255).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
50
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
50
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_jo14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_jo14
# storage
db|aurora_8b10b_v5_2_example_design.(256).cnf
db|aurora_8b10b_v5_2_example_design.(256).cnf
# case_insensitive
# source_file
db|altsyncram_jo14.tdf
e41c8e91bbacb13d543df6d3db63b6e
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(257).cnf
db|aurora_8b10b_v5_2_example_design.(257).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
1024
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
10
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
50
PARAMETER_SIGNED_DEC
USR
status_bits
21
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
6
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
49 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
20 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
9 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
9 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
9 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(258).cnf
db|aurora_8b10b_v5_2_example_design.(258).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
50
PARAMETER_UNKNOWN
USR
sld_trigger_bits
50
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
55416
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
12778
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
175
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(259).cnf
db|aurora_8b10b_v5_2_example_design.(259).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
50
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
50
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
55416
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
12778
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
175
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 174
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
49 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(260).cnf
db|aurora_8b10b_v5_2_example_design.(260).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
50
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
sample_depth
2048
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
174 downto 174
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(261).cnf
db|aurora_8b10b_v5_2_example_design.(261).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
50
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
50
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_lo14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_lo14
# storage
db|aurora_8b10b_v5_2_example_design.(262).cnf
db|aurora_8b10b_v5_2_example_design.(262).cnf
# case_insensitive
# source_file
db|altsyncram_lo14.tdf
17fb5f50ce44b4fffad17f861c9a501b
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b49
-1
3
q_b48
-1
3
q_b47
-1
3
q_b46
-1
3
q_b45
-1
3
q_b44
-1
3
q_b43
-1
3
q_b42
-1
3
q_b41
-1
3
q_b40
-1
3
q_b4
-1
3
q_b39
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a49
-1
3
data_a48
-1
3
data_a47
-1
3
data_a46
-1
3
data_a45
-1
3
data_a44
-1
3
data_a43
-1
3
data_a42
-1
3
data_a41
-1
3
data_a40
-1
3
data_a4
-1
3
data_a39
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(263).cnf
db|aurora_8b10b_v5_2_example_design.(263).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
2048
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
50
PARAMETER_SIGNED_DEC
USR
status_bits
23
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
6
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
49 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
22 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(264).cnf
db|aurora_8b10b_v5_2_example_design.(264).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
50
PARAMETER_UNKNOWN
USR
sld_trigger_bits
1
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
47820
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
5251
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
28
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(265).cnf
db|aurora_8b10b_v5_2_example_design.(265).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
50
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
1
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
47820
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
5251
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
28
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 27
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
49 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(266).cnf
db|aurora_8b10b_v5_2_example_design.(266).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
1
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
sample_depth
2048
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
27 downto 27
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(267).cnf
db|aurora_8b10b_v5_2_example_design.(267).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
5
PARAMETER_UNKNOWN
USR
sld_trigger_bits
5
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
7433
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
48543
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
40
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(268).cnf
db|aurora_8b10b_v5_2_example_design.(268).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
5
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
5
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
7433
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
48543
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
40
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 39
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
4 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
4 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
4 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
4 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(269).cnf
db|aurora_8b10b_v5_2_example_design.(269).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
5
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
sample_depth
2048
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
39 downto 39
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
4 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(270).cnf
db|aurora_8b10b_v5_2_example_design.(270).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
5
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
4 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(271).cnf
db|aurora_8b10b_v5_2_example_design.(271).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
15
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q14
-1
3
Q13
-1
3
Q12
-1
3
Q11
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(272).cnf
db|aurora_8b10b_v5_2_example_design.(272).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
5
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
4 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
14 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(273).cnf
db|aurora_8b10b_v5_2_example_design.(273).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
5
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
5
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_ll14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_ll14
# storage
db|aurora_8b10b_v5_2_example_design.(274).cnf
db|aurora_8b10b_v5_2_example_design.(274).cnf
# case_insensitive
# source_file
db|altsyncram_ll14.tdf
c36c4c2fe5ebbd87931749b5f2b4f30
7
# used_port {
wren_a
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(275).cnf
db|aurora_8b10b_v5_2_example_design.(275).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
2048
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
5
PARAMETER_SIGNED_DEC
USR
status_bits
23
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
3
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
4 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
22 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(276).cnf
db|aurora_8b10b_v5_2_example_design.(276).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
3
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
5
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_pbi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_pbi
# storage
db|aurora_8b10b_v5_2_example_design.(277).cnf
db|aurora_8b10b_v5_2_example_design.(277).cnf
# case_insensitive
# source_file
db|cntr_pbi.tdf
7ebc3baf42314b228c6126d06e4a166c
7
# used_port {
sclr
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_mdc
# storage
db|aurora_8b10b_v5_2_example_design.(278).cnf
db|aurora_8b10b_v5_2_example_design.(278).cnf
# case_insensitive
# source_file
db|cmpr_mdc.tdf
1d1530b0c45545913cfb1f5c5332ccd9
7
# used_port {
datab1
-1
3
datab0
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab2
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(279).cnf
db|aurora_8b10b_v5_2_example_design.(279).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
5
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_LANE_INIT_SM
# storage
db|aurora_8b10b_v5_2_example_design.(8).cnf
db|aurora_8b10b_v5_2_example_design.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_lane_init_sm.vhd
2d204b729cdd7493954e469c2a1227b
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(rx_not_in_table)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_disp_err)
1 downto 0
PARAMETER_STRING
USR
 constraint(rx_char_is_comma)
1 downto 0
PARAMETER_STRING
USR
 constraint(gen_sp_data)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_spa_data)
0 to 1
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_CHANNEL_INIT_SM
# storage
db|aurora_8b10b_v5_2_example_design.(16).cnf
db|aurora_8b10b_v5_2_example_design.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_channel_init_sm.vhd
97a1e4989d7da3993b11f4355120c76d
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(got_a)
0 to 1
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_IDLE_AND_VER_GEN
# storage
db|aurora_8b10b_v5_2_example_design.(18).cnf
db|aurora_8b10b_v5_2_example_design.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_idle_and_ver_gen.vhd
acf7c4c31c919b62aa9b4826030b5
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(gen_k)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_r)
0 to 1
PARAMETER_STRING
USR
 constraint(gen_v)
0 to 1
PARAMETER_STRING
USR
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
aurora_8b10b_v5_2_TX_LL_CONTROL
# storage
db|aurora_8b10b_v5_2_example_design.(28).cnf
db|aurora_8b10b_v5_2_example_design.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_tx_ll_control.vhd
dfa4710da7ad2bdec605aec8d2c3d2f
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# include_file {
aurora_8b10b_v5_2|src|aurora_8b10b_v5_2_aurora_pkg.vhd
aaeeadcc8522c0f4758a99ae997a5b0
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(280).cnf
db|aurora_8b10b_v5_2_example_design.(280).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
37
PARAMETER_UNKNOWN
USR
sld_trigger_bits
37
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
23012
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
64278
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
136
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(281).cnf
db|aurora_8b10b_v5_2_example_design.(281).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
37
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
37
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
23012
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
64278
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
136
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 135
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
36 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
36 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(282).cnf
db|aurora_8b10b_v5_2_example_design.(282).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
37
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
sample_depth
2048
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
135 downto 135
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(283).cnf
db|aurora_8b10b_v5_2_example_design.(283).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
37
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(284).cnf
db|aurora_8b10b_v5_2_example_design.(284).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
111
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q99
-1
3
Q98
-1
3
Q97
-1
3
Q96
-1
3
Q95
-1
3
Q94
-1
3
Q93
-1
3
Q92
-1
3
Q91
-1
3
Q90
-1
3
Q9
-1
3
Q89
-1
3
Q88
-1
3
Q87
-1
3
Q86
-1
3
Q85
-1
3
Q84
-1
3
Q83
-1
3
Q82
-1
3
Q81
-1
3
Q80
-1
3
Q8
-1
3
Q79
-1
3
Q78
-1
3
Q77
-1
3
Q76
-1
3
Q75
-1
3
Q74
-1
3
Q73
-1
3
Q72
-1
3
Q71
-1
3
Q70
-1
3
Q7
-1
3
Q69
-1
3
Q68
-1
3
Q67
-1
3
Q66
-1
3
Q65
-1
3
Q64
-1
3
Q63
-1
3
Q62
-1
3
Q61
-1
3
Q60
-1
3
Q6
-1
3
Q59
-1
3
Q58
-1
3
Q57
-1
3
Q56
-1
3
Q55
-1
3
Q54
-1
3
Q53
-1
3
Q52
-1
3
Q51
-1
3
Q50
-1
3
Q5
-1
3
Q49
-1
3
Q48
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q32
-1
3
Q31
-1
3
Q30
-1
3
Q3
-1
3
Q29
-1
3
Q28
-1
3
Q27
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q22
-1
3
Q21
-1
3
Q20
-1
3
Q2
-1
3
Q19
-1
3
Q18
-1
3
Q17
-1
3
Q16
-1
3
Q15
-1
3
Q14
-1
3
Q13
-1
3
Q12
-1
3
Q110
-1
3
Q11
-1
3
Q109
-1
3
Q108
-1
3
Q107
-1
3
Q106
-1
3
Q105
-1
3
Q104
-1
3
Q103
-1
3
Q102
-1
3
Q101
-1
3
Q100
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(285).cnf
db|aurora_8b10b_v5_2_example_design.(285).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
37
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
110 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(286).cnf
db|aurora_8b10b_v5_2_example_design.(286).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
37
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
37
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_vo14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_vo14
# storage
db|aurora_8b10b_v5_2_example_design.(287).cnf
db|aurora_8b10b_v5_2_example_design.(287).cnf
# case_insensitive
# source_file
db|altsyncram_vo14.tdf
bfa125b6e958ecd2d5105b6152fa8
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(288).cnf
db|aurora_8b10b_v5_2_example_design.(288).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
2048
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
37
PARAMETER_SIGNED_DEC
USR
status_bits
23
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
6
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
36 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
22 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(289).cnf
db|aurora_8b10b_v5_2_example_design.(289).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
6
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
37
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_rdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_rdi
# storage
db|aurora_8b10b_v5_2_example_design.(290).cnf
db|aurora_8b10b_v5_2_example_design.(290).cnf
# case_insensitive
# source_file
db|cntr_rdi.tdf
54579954edae59a344f842a1c5fac9
7
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_pdc
# storage
db|aurora_8b10b_v5_2_example_design.(291).cnf
db|aurora_8b10b_v5_2_example_design.(291).cnf
# case_insensitive
# source_file
db|cmpr_pdc.tdf
2a699a9daa415c42a9f26a5559b622aa
7
# used_port {
datab4
-1
3
datab3
-1
3
datab1
-1
3
datab0
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab5
-1
2
datab2
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(292).cnf
db|aurora_8b10b_v5_2_example_design.(292).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
37
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA36
-1
3
DATA35
-1
3
DATA34
-1
3
DATA33
-1
3
DATA32
-1
3
DATA31
-1
3
DATA30
-1
3
DATA3
-1
3
DATA29
-1
3
DATA28
-1
3
DATA27
-1
3
DATA26
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(293).cnf
db|aurora_8b10b_v5_2_example_design.(293).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
37
PARAMETER_UNKNOWN
USR
sld_trigger_bits
1
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
10605
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
3080
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
28
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(294).cnf
db|aurora_8b10b_v5_2_example_design.(294).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
37
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
1
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
10605
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
3080
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
28
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 27
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
36 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(295).cnf
db|aurora_8b10b_v5_2_example_design.(295).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
39
PARAMETER_UNKNOWN
USR
sld_trigger_bits
1
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
19945
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
10007
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
28
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(296).cnf
db|aurora_8b10b_v5_2_example_design.(296).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
39
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
1
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
19945
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
10007
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
28
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 27
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
38 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
38 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(297).cnf
db|aurora_8b10b_v5_2_example_design.(297).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
39
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
39
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_6p14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altsyncram_6p14
# storage
db|aurora_8b10b_v5_2_example_design.(298).cnf
db|aurora_8b10b_v5_2_example_design.(298).cnf
# case_insensitive
# source_file
db|altsyncram_6p14.tdf
5c4fc0a4441dbbc35b11a143ca562c9
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(299).cnf
db|aurora_8b10b_v5_2_example_design.(299).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
2048
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
39
PARAMETER_SIGNED_DEC
USR
status_bits
23
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
6
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
38 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
22 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(300).cnf
db|aurora_8b10b_v5_2_example_design.(300).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
6
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
39
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_sdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
cntr_sdi
# storage
db|aurora_8b10b_v5_2_example_design.(301).cnf
db|aurora_8b10b_v5_2_example_design.(301).cnf
# case_insensitive
# source_file
db|cntr_sdi.tdf
cc5a66259b3c89fcdacc595ea3c3cea
7
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# macro_sequence

# end
# entity
cmpr_pdc
# storage
db|aurora_8b10b_v5_2_example_design.(302).cnf
db|aurora_8b10b_v5_2_example_design.(302).cnf
# case_insensitive
# source_file
db|cmpr_pdc.tdf
2a699a9daa415c42a9f26a5559b622aa
7
# used_port {
datab4
-1
3
datab3
-1
3
datab0
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
datab5
-1
2
datab2
-1
2
datab1
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(303).cnf
db|aurora_8b10b_v5_2_example_design.(303).cnf
# case_insensitive
# source_file
c:|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
39
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA38
-1
3
DATA37
-1
3
DATA36
-1
3
DATA35
-1
3
DATA34
-1
3
DATA33
-1
3
DATA32
-1
3
DATA31
-1
3
DATA30
-1
3
DATA3
-1
3
DATA29
-1
3
DATA28
-1
3
DATA27
-1
3
DATA26
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
altpll
# storage
db|aurora_8b10b_v5_2_example_design.(9).cnf
db|aurora_8b10b_v5_2_example_design.(9).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|altpll.tdf
86b75138429c7354c383e2cca01ca9f6
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
LPM_HINT
CBX_MODULE_PREFIX=PLL_LA
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
6400
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
USR
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
2
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_LOW_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
VCO_RANGE_DETECTOR_HIGH_BITS
UNUSED
PARAMETER_UNKNOWN
DEF
DPA_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
DPA_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
DPA_DIVIDER
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN
DEF
C9_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C6_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C7_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C8_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
C9_USE_CASC_IN
OFF
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK6_COUNTER
E0
PARAMETER_UNKNOWN
DEF
CLK7_COUNTER
E1
PARAMETER_UNKNOWN
DEF
CLK8_COUNTER
E2
PARAMETER_UNKNOWN
DEF
CLK9_COUNTER
E3
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R_BITS
9999
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C_BITS
9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
PLL_LA_altpll
PARAMETER_UNKNOWN
USR
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
10
PARAMETER_SIGNED_DEC
USR
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk0
-1
3
clk0
-1
3
inclk1
-1
1
}
# hierarchies {
PLL_LA:LA_PLL|altpll:altpll_component
}
# macro_sequence

# end
# entity
FDR
# storage
db|aurora_8b10b_v5_2_example_design.(17).cnf
db|aurora_8b10b_v5_2_example_design.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fdr.vhd
2598153bdbd1e1e6df27652e661588
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
INIT
'0'
PARAMETER_ENUM
DEF
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|FDR:lane_up_flop_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_last_flop_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_taps_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i|FDR:gen_cc_flop_0_i
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
FD
# storage
db|aurora_8b10b_v5_2_example_design.(19).cnf
db|aurora_8b10b_v5_2_example_design.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fd.vhd
9773d3f516cd37a8755fc433712d88
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
INIT
'0'
PARAMETER_ENUM
DEF
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|FD:reset_lanes_flop_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_0_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_1_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_a_flop_0_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_0_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_1_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_0_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_1_i
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
SRL16
# storage
db|aurora_8b10b_v5_2_example_design.(20).cnf
db|aurora_8b10b_v5_2_example_design.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
srl16.vhd
fc4d3887983cd8b5b76cb33532189
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPMSHIFTREG16
# storage
db|aurora_8b10b_v5_2_example_design.(22).cnf
db|aurora_8b10b_v5_2_example_design.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpmshiftreg16.vhd
5c972b592be57032b58d1e43c65b4b22
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(q)
15 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(304).cnf
db|aurora_8b10b_v5_2_example_design.(304).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
16
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
LEFT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component
}
# macro_sequence

# end
# entity
MUX16to1
# storage
db|aurora_8b10b_v5_2_example_design.(305).cnf
db|aurora_8b10b_v5_2_example_design.(305).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
mux16to1.vhd
9f9d89ab7118ae3995ce2248a5e09f64
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(sel)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_MUX
# storage
db|aurora_8b10b_v5_2_example_design.(306).cnf
db|aurora_8b10b_v5_2_example_design.(306).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_mux.tdf
d2c33760a4359bf0707ac9e7afb311f2
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
1
PARAMETER_SIGNED_DEC
USR
LPM_SIZE
16
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHS
4
PARAMETER_SIGNED_DEC
USR
LPM_PIPELINE
0
PARAMETER_SIGNED_DEC
USR
CBXI_PARAMETER
mux_76e
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
}
# used_port {
SEL3
-1
3
SEL2
-1
3
SEL1
-1
3
SEL0
-1
3
RESULT0
-1
3
DATA9_0
-1
3
DATA8_0
-1
3
DATA7_0
-1
3
DATA6_0
-1
3
DATA5_0
-1
3
DATA4_0
-1
3
DATA3_0
-1
3
DATA2_0
-1
3
DATA1_0
-1
3
DATA15_0
-1
3
DATA14_0
-1
3
DATA13_0
-1
3
DATA12_0
-1
3
DATA11_0
-1
3
DATA10_0
-1
3
DATA0_0
-1
3
}
# hierarchies {
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|lpm_mux:lpm_mux_component
aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1|lpm_mux:lpm_mux_component
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|aurora_8b10b_v5_2_example_design.(307).cnf
db|aurora_8b10b_v5_2_example_design.(307).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
39
PARAMETER_UNKNOWN
USR
sld_trigger_bits
1
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
19945
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
10007
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_segment_size
2048
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M9K
PARAMETER_UNKNOWN
USR
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
28
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_BITS
1
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_GAP_RECORD
0
PARAMETER_SIGNED_DEC
DEF
SLD_STORAGE_QUALIFIER_MODE
OFF
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION
0
PARAMETER_SIGNED_DEC
DEF
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_UNKNOWN
USR
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY
basic
PARAMETER_STRING
DEF
SLD_STORAGE_QUALIFIER_PIPELINE
0
PARAMETER_SIGNED_DEC
DEF
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|aurora_8b10b_v5_2_example_design.(308).cnf
db|aurora_8b10b_v5_2_example_design.(308).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_signaltap.vhd
a5a335bbf9ac9a5b6cb65b7c1abe6782
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
39
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
1
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
19945
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
10007
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
2048
PARAMETER_SIGNED_DEC
USR
sld_segment_size
2048
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
M9K
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
28
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_bits
1
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_gap_record
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_mode
OFF
PARAMETER_STRING
USR
sld_storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
sld_storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
sld_storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(sld_ram_block_type)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 27
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(sld_storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_data_in)
38 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(acq_storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
38 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|aurora_8b10b_v5_2_example_design.(309).cnf
db|aurora_8b10b_v5_2_example_design.(309).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
1
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
sample_depth
2048
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_width
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
storage_qualifier_enable_advanced_condition
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_inversion_mask_length
0
PARAMETER_SIGNED_DEC
USR
storage_qualifier_advanced_condition_entity
basic
PARAMETER_STRING
USR
storage_qualifier_pipeline
0
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
27 downto 27
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(storage_qualifier_advanced_condition_entity)
1 to 5
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(storage_qualifier_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(310).cnf
db|aurora_8b10b_v5_2_example_design.(310).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
4
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|aurora_8b10b_v5_2_example_design.(311).cnf
db|aurora_8b10b_v5_2_example_design.(311).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_ela_control.vhd
80d090106366afbfe9bdd77bf57f258
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(data_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(312).cnf
db|aurora_8b10b_v5_2_example_design.(312).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
3
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(313).cnf
db|aurora_8b10b_v5_2_example_design.(313).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
1
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
2 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_sbpmg
# storage
db|aurora_8b10b_v5_2_example_design.(314).cnf
db|aurora_8b10b_v5_2_example_design.(314).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_mbpmg.vhd
85f782e9b645f3fd4d670de5fdc5e3
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_ela_trigger_flow_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(315).cnf
db|aurora_8b10b_v5_2_example_design.(315).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_ela_trigger_flow_mgr.vhd
54b4e96651b97ec28a57c8b6d87fce
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(condition_met)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(316).cnf
db|aurora_8b10b_v5_2_example_design.(316).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
10
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
sld_buffer_manager
# storage
db|aurora_8b10b_v5_2_example_design.(317).cnf
db|aurora_8b10b_v5_2_example_design.(317).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
address_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
11
PARAMETER_SIGNED_DEC
USR
num_segments_bits
1
PARAMETER_SIGNED_DEC
USR
storage_qualifier_mode
OFF
PARAMETER_STRING
USR
 constraint(storage_qualifier_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(address)
10 downto 0
PARAMETER_STRING
USR
 constraint(post_count)
10 downto 0
PARAMETER_STRING
USR
 constraint(current_segment)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_offset)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_trigger_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(318).cnf
db|aurora_8b10b_v5_2_example_design.(318).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
11
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|aurora_8b10b_v5_2_example_design.(319).cnf
db|aurora_8b10b_v5_2_example_design.(319).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|altsyncram.tdf
8dfe23324554fd33374fa9f122ad8d4
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
39
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
39
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
11
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
M9K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
WIDTH_ECCSTATUS
3
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_6p14
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b38
-1
3
q_b37
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a38
-1
3
data_a37
-1
3
data_a36
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# macro_sequence

# end
# entity
altdpram
# storage
db|aurora_8b10b_v5_2_example_design.(320).cnf
db|aurora_8b10b_v5_2_example_design.(320).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|altdpram.tdf
2c2259fdcccd62fa8105010b956d34
7
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH_ECCSTATUS
3
PARAMETER_UNKNOWN
DEF
WIDTH
23
PARAMETER_SIGNED_DEC
USR
WIDTHAD
1
PARAMETER_SIGNED_DEC
USR
NUMWORDS
0
PARAMETER_SIGNED_DEC
USR
FILE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
DEF
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
BYTE_SIZE
0
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA
1
PARAMETER_SIGNED_DEC
USR
DISABLE_LE_RAM_LIMIT_CHECK
on
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
-1
3
wraddress0
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclocken
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
lpm_mux
# storage
db|aurora_8b10b_v5_2_example_design.(321).cnf
db|aurora_8b10b_v5_2_example_design.(321).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_mux.tdf
d2c33760a4359bf0707ac9e7afb311f2
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
23
PARAMETER_UNKNOWN
USR
LPM_SIZE
2
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_opc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
}
# used_port {
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data1_9
-1
3
data1_8
-1
3
data1_7
-1
3
data1_6
-1
3
data1_5
-1
3
data1_4
-1
3
data1_3
-1
3
data1_22
-1
3
data1_21
-1
3
data1_20
-1
3
data1_2
-1
3
data1_19
-1
3
data1_18
-1
3
data1_17
-1
3
data1_16
-1
3
data1_15
-1
3
data1_14
-1
3
data1_13
-1
3
data1_12
-1
3
data1_11
-1
3
data1_10
-1
3
data1_1
-1
3
data1_0
-1
3
data0_9
-1
3
data0_8
-1
3
data0_7
-1
3
data0_6
-1
3
data0_5
-1
3
data0_4
-1
3
data0_3
-1
3
data0_22
-1
3
data0_21
-1
3
data0_20
-1
3
data0_2
-1
3
data0_19
-1
3
data0_18
-1
3
data0_17
-1
3
data0_16
-1
3
data0_15
-1
3
data0_14
-1
3
data0_13
-1
3
data0_12
-1
3
data0_11
-1
3
data0_10
-1
3
data0_1
-1
3
data0_0
-1
3
}
# macro_sequence

# end
# entity
lpm_decode
# storage
db|aurora_8b10b_v5_2_example_design.(322).cnf
db|aurora_8b10b_v5_2_example_design.(322).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_decode.tdf
61bb7230fce64482977996ae7bdd7ec8
7
# user_parameter {
LPM_WIDTH
1
PARAMETER_UNKNOWN
USR
LPM_DECODES
2
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_asf
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
eq1
-1
3
eq0
-1
3
enable
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
sld_offload_buffer_mgr
# storage
db|aurora_8b10b_v5_2_example_design.(323).cnf
db|aurora_8b10b_v5_2_example_design.(323).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_buffer_manager.vhd
6f5e8d39533706155a84bac9118c3d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
buffer_depth
2048
PARAMETER_SIGNED_DEC
USR
segment_count
1
PARAMETER_SIGNED_DEC
USR
mem_address_bits
11
PARAMETER_SIGNED_DEC
USR
status_address_bits
1
PARAMETER_SIGNED_DEC
USR
data_bits
39
PARAMETER_SIGNED_DEC
USR
status_bits
23
PARAMETER_SIGNED_DEC
USR
data_bit_cntr_bits
6
PARAMETER_SIGNED_DEC
USR
status_bit_cntr_bits
5
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
 constraint(buffer_read_data_out)
38 downto 0
PARAMETER_STRING
USR
 constraint(status_read_data_out)
22 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(buffer_read_address)
10 downto 0
PARAMETER_STRING
USR
 constraint(status_read_address)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(324).cnf
db|aurora_8b10b_v5_2_example_design.(324).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
6
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
39
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_sdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(325).cnf
db|aurora_8b10b_v5_2_example_design.(325).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
11
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
2048
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_d6j
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
CLK_EN
-1
3
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(326).cnf
db|aurora_8b10b_v5_2_example_design.(326).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
39
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA38
-1
3
DATA37
-1
3
DATA36
-1
3
DATA35
-1
3
DATA34
-1
3
DATA33
-1
3
DATA32
-1
3
DATA31
-1
3
DATA30
-1
3
DATA3
-1
3
DATA29
-1
3
DATA28
-1
3
DATA27
-1
3
DATA26
-1
3
DATA25
-1
3
DATA24
-1
3
DATA23
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(327).cnf
db|aurora_8b10b_v5_2_example_design.(327).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
23
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
ENABLE
-1
2
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(328).cnf
db|aurora_8b10b_v5_2_example_design.(328).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
5
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
23
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_bdi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
LPM_COUNTER
# storage
db|aurora_8b10b_v5_2_example_design.(329).cnf
db|aurora_8b10b_v5_2_example_design.(329).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_counter.tdf
937133f7fa52965669ad68ccfded3
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
1
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
1
PARAMETER_SIGNED_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
OFF
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_vvi
PARAMETER_UNKNOWN
USR
}
# used_port {
SCLR
-1
3
Q0
-1
3
CLOCK
-1
3
CLK_EN
-1
3
}
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(330).cnf
db|aurora_8b10b_v5_2_example_design.(330).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
23
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
LOAD
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA22
-1
3
DATA21
-1
3
DATA20
-1
3
DATA2
-1
3
DATA19
-1
3
DATA18
-1
3
DATA17
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
ACLR
-1
3
SHIFTIN
-1
2
ENABLE
-1
2
}
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|aurora_8b10b_v5_2_example_design.(331).cnf
db|aurora_8b10b_v5_2_example_design.(331).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_rom_sr.vhd
c8a299171b404a8be9d59988f836b14
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
32
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
31 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|aurora_8b10b_v5_2_example_design.(332).cnf
db|aurora_8b10b_v5_2_example_design.(332).cnf
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|lpm_shiftreg.tdf
ba522854eb521cc3dd17577a11762e6
7
# user_parameter {
LPM_WIDTH
17
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix IV
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
LOAD
-1
3
ENABLE
-1
3
DATA9
-1
3
DATA8
-1
3
DATA7
-1
3
DATA6
-1
3
DATA5
-1
3
DATA4
-1
3
DATA3
-1
3
DATA2
-1
3
DATA16
-1
3
DATA15
-1
3
DATA14
-1
3
DATA13
-1
3
DATA12
-1
3
DATA11
-1
3
DATA10
-1
3
DATA1
-1
3
DATA0
-1
3
CLOCK
-1
3
}
# macro_sequence

# end
# entity
sld_hub
# storage
db|aurora_8b10b_v5_2_example_design.(333).cnf
db|aurora_8b10b_v5_2_example_design.(333).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_hub.vhd
7a79487a6e8170b43b1767a2ea68
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
4
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Stratix IV
PARAMETER_UNKNOWN
USR
n_nodes
1
PARAMETER_UNKNOWN
USR
n_sel_bits
1
PARAMETER_UNKNOWN
USR
n_node_ir_bits
8
PARAMETER_UNKNOWN
USR
node_info
00110000000000000110111000000000
PARAMETER_UNSIGNED_BIN
USR
compilation_mode
1
PARAMETER_UNKNOWN
USR
BROADCAST_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
FORCE_IR_CAPTURE_FEATURE
1
PARAMETER_SIGNED_DEC
DEF
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_shadow_jsm
# storage
db|aurora_8b10b_v5_2_example_design.(334).cnf
db|aurora_8b10b_v5_2_example_design.(334).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_hub.vhd
7a79487a6e8170b43b1767a2ea68
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
1
PARAMETER_SIGNED_DEC
USR
ip_minor_version
4
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
 constraint(jtag_state)
15 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|aurora_8b10b_v5_2_example_design.(335).cnf
db|aurora_8b10b_v5_2_example_design.(335).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|altera|10.1|quartus|libraries|megafunctions|sld_rom_sr.vhd
c8a299171b404a8be9d59988f836b14
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
64
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
63 downto 0
PARAMETER_STRING
USR
}
# lmf
|altera|10.1|quartus|lmf|maxplus2.lmf
a36c8ec425c8a2589af98b2d4daabc3
# macro_sequence

# end
# complete

