|aurora_8b10b_v5_2_example_design
DIS_USER_CLK <= DIS_USER_CLK~reg0.DB_MAX_OUTPUT_PORT_TYPE
DIS_TX_CLK <= comb.DB_MAX_OUTPUT_PORT_TYPE
DIS_RX_CLK <= aurora_8b10b_v5_2:aurora_module_i.rxclk
GXB_DOWN => aurora_8b10b_v5_2:aurora_module_i.GXB_DOWN
RESET => aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i.RESET
HARD_ERR <= HARD_ERR_Buffer.DB_MAX_OUTPUT_PORT_TYPE
SOFT_ERR <= SOFT_ERR_Buffer.DB_MAX_OUTPUT_PORT_TYPE
FRAME_ERR <= FRAME_ERR_Buffer.DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[7] <= ERR_COUNT_Buffer[7].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[6] <= ERR_COUNT_Buffer[6].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[5] <= ERR_COUNT_Buffer[5].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[4] <= ERR_COUNT_Buffer[4].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[3] <= ERR_COUNT_Buffer[3].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[2] <= ERR_COUNT_Buffer[2].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[1] <= ERR_COUNT_Buffer[1].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[0] <= ERR_COUNT_Buffer[0].DB_MAX_OUTPUT_PORT_TYPE
LANE_UP <= LANE_UP_Buffer.DB_MAX_OUTPUT_PORT_TYPE
CHANNEL_UP <= CHANNEL_UP_Buffer.DB_MAX_OUTPUT_PORT_TYPE
INIT_CLK => PLL_LA:LA_PLL.inclk0
INIT_CLK => aurora_8b10b_v5_2:aurora_module_i.INIT_CLK
INIT_CLK => aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i.INIT_CLK
GT_RESET_IN => aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i.GT_RESET_IN
GTXQ4 => aurora_8b10b_v5_2:aurora_module_i.GTXQ4
RXP => aurora_8b10b_v5_2:aurora_module_i.RXP
RXN => aurora_8b10b_v5_2:aurora_module_i.RXN
TXP <= aurora_8b10b_v5_2:aurora_module_i.TXP
TXN <= aurora_8b10b_v5_2:aurora_module_i.TXN


|aurora_8b10b_v5_2_example_design|PLL_LA:LA_PLL
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|aurora_8b10b_v5_2_example_design|PLL_LA:LA_PLL|altpll:altpll_component
inclk[0] => PLL_LA_altpll:auto_generated.inclk[0]
inclk[1] => PLL_LA_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
clk[5] <= clk[5].DB_MAX_OUTPUT_PORT_TYPE
clk[6] <= clk[6].DB_MAX_OUTPUT_PORT_TYPE
clk[7] <= clk[7].DB_MAX_OUTPUT_PORT_TYPE
clk[8] <= clk[8].DB_MAX_OUTPUT_PORT_TYPE
clk[9] <= clk[9].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>


|aurora_8b10b_v5_2_example_design|PLL_LA:LA_PLL|altpll:altpll_component|PLL_LA_altpll:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
clk[5] <= pll1.CLK5
clk[6] <= pll1.CLK6
clk[7] <= pll1.CLK7
clk[8] <= pll1.CLK8
clk[9] <= pll1.CLK9
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_CHECK:frame_check_i
RX_D[15] => RX_D_R.DATAA
RX_D[15] => RX_D_R.DATAB
RX_D[14] => RX_D_R.DATAA
RX_D[14] => RX_D_R.DATAB
RX_D[13] => RX_D_R.DATAA
RX_D[13] => RX_D_R.DATAB
RX_D[12] => RX_D_R.DATAA
RX_D[12] => RX_D_R.DATAB
RX_D[11] => RX_D_R.DATAA
RX_D[11] => RX_D_R.DATAB
RX_D[10] => RX_D_R.DATAA
RX_D[10] => RX_D_R.DATAB
RX_D[9] => RX_D_R.DATAA
RX_D[9] => RX_D_R.DATAB
RX_D[8] => RX_D_R.DATAA
RX_D[8] => RX_D_R.DATAB
RX_D[7] => RX_D_R.DATAB
RX_D[7] => RX_D_R.DATAB
RX_D[6] => RX_D_R.DATAB
RX_D[6] => RX_D_R.DATAB
RX_D[5] => RX_D_R.DATAB
RX_D[5] => RX_D_R.DATAB
RX_D[4] => RX_D_R.DATAB
RX_D[4] => RX_D_R.DATAB
RX_D[3] => RX_D_R.DATAB
RX_D[3] => RX_D_R.DATAB
RX_D[2] => RX_D_R.DATAB
RX_D[2] => RX_D_R.DATAB
RX_D[1] => RX_D_R.DATAB
RX_D[1] => RX_D_R.DATAB
RX_D[0] => RX_D_R.DATAB
RX_D[0] => RX_D_R.DATAB
RX_REM => RX_D_R.OUTPUTSELECT
RX_REM => RX_D_R.OUTPUTSELECT
RX_REM => RX_D_R.OUTPUTSELECT
RX_REM => RX_D_R.OUTPUTSELECT
RX_REM => RX_D_R.OUTPUTSELECT
RX_REM => RX_D_R.OUTPUTSELECT
RX_REM => RX_D_R.OUTPUTSELECT
RX_REM => RX_D_R.OUTPUTSELECT
RX_REM => pdu_cmp_data_r.OUTPUTSELECT
RX_REM => pdu_cmp_data_r.OUTPUTSELECT
RX_REM => pdu_cmp_data_r.OUTPUTSELECT
RX_REM => pdu_cmp_data_r.OUTPUTSELECT
RX_REM => pdu_cmp_data_r.OUTPUTSELECT
RX_REM => pdu_cmp_data_r.OUTPUTSELECT
RX_REM => pdu_cmp_data_r.OUTPUTSELECT
RX_REM => pdu_cmp_data_r.OUTPUTSELECT
RX_SOF_N => data_in_frame_c.IN0
RX_SOF_N => process_1.IN1
RX_EOF_N => process_1.IN1
RX_EOF_N => process_1.IN1
RX_EOF_N => process_2.IN0
RX_EOF_N => process_3.IN1
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => RX_D_R.OUTPUTSELECT
RX_SRC_RDY_N => data_in_frame_c.IN1
RX_SRC_RDY_N => data_valid_c.IN1
RX_SRC_RDY_N => process_1.IN1
RX_SRC_RDY_N => process_1.IN1
RX_SRC_RDY_N => process_2.IN1
USER_CLK => err_count_tmp[8].CLK
USER_CLK => err_count_tmp[7].CLK
USER_CLK => err_count_tmp[6].CLK
USER_CLK => err_count_tmp[5].CLK
USER_CLK => err_count_tmp[4].CLK
USER_CLK => err_count_tmp[3].CLK
USER_CLK => err_count_tmp[2].CLK
USER_CLK => err_count_tmp[1].CLK
USER_CLK => err_count_tmp[0].CLK
USER_CLK => data_err_detected_r.CLK
USER_CLK => data_lfsr_r[15].CLK
USER_CLK => data_lfsr_r[14].CLK
USER_CLK => data_lfsr_r[13].CLK
USER_CLK => data_lfsr_r[12].CLK
USER_CLK => data_lfsr_r[11].CLK
USER_CLK => data_lfsr_r[10].CLK
USER_CLK => data_lfsr_r[9].CLK
USER_CLK => data_lfsr_r[8].CLK
USER_CLK => data_lfsr_r[7].CLK
USER_CLK => data_lfsr_r[6].CLK
USER_CLK => data_lfsr_r[5].CLK
USER_CLK => data_lfsr_r[4].CLK
USER_CLK => data_lfsr_r[3].CLK
USER_CLK => data_lfsr_r[2].CLK
USER_CLK => data_lfsr_r[1].CLK
USER_CLK => data_lfsr_r[0].CLK
USER_CLK => pdu_cmp_data_r[15].CLK
USER_CLK => pdu_cmp_data_r[14].CLK
USER_CLK => pdu_cmp_data_r[13].CLK
USER_CLK => pdu_cmp_data_r[12].CLK
USER_CLK => pdu_cmp_data_r[11].CLK
USER_CLK => pdu_cmp_data_r[10].CLK
USER_CLK => pdu_cmp_data_r[9].CLK
USER_CLK => pdu_cmp_data_r[8].CLK
USER_CLK => pdu_cmp_data_r[7].CLK
USER_CLK => pdu_cmp_data_r[6].CLK
USER_CLK => pdu_cmp_data_r[5].CLK
USER_CLK => pdu_cmp_data_r[4].CLK
USER_CLK => pdu_cmp_data_r[3].CLK
USER_CLK => pdu_cmp_data_r[2].CLK
USER_CLK => pdu_cmp_data_r[1].CLK
USER_CLK => pdu_cmp_data_r[0].CLK
USER_CLK => RX_D_R[15].CLK
USER_CLK => RX_D_R[14].CLK
USER_CLK => RX_D_R[13].CLK
USER_CLK => RX_D_R[12].CLK
USER_CLK => RX_D_R[11].CLK
USER_CLK => RX_D_R[10].CLK
USER_CLK => RX_D_R[9].CLK
USER_CLK => RX_D_R[8].CLK
USER_CLK => RX_D_R[7].CLK
USER_CLK => RX_D_R[6].CLK
USER_CLK => RX_D_R[5].CLK
USER_CLK => RX_D_R[4].CLK
USER_CLK => RX_D_R[3].CLK
USER_CLK => RX_D_R[2].CLK
USER_CLK => RX_D_R[1].CLK
USER_CLK => RX_D_R[0].CLK
USER_CLK => data_in_frame_r.CLK
USER_CLK => data_valid_r.CLK
RESET => reset_c.IN0
CHANNEL_UP => reset_c.IN1
ERR_COUNT[7] <= err_count_tmp[8].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[6] <= err_count_tmp[7].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[5] <= err_count_tmp[6].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[4] <= err_count_tmp[5].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[3] <= err_count_tmp[4].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[2] <= err_count_tmp[3].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[1] <= err_count_tmp[2].DB_MAX_OUTPUT_PORT_TYPE
ERR_COUNT[0] <= err_count_tmp[1].DB_MAX_OUTPUT_PORT_TYPE


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_FRAME_GEN:frame_gen_i
TX_D[15] <= TX_D[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[14] <= TX_D[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[13] <= TX_D[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[12] <= TX_D[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[11] <= TX_D[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[10] <= TX_D[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[9] <= TX_D[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[8] <= TX_D[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[7] <= TX_D[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[6] <= TX_D[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[5] <= TX_D[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[4] <= TX_D[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[3] <= TX_D[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[2] <= TX_D[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[1] <= TX_D[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_D[0] <= TX_D[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_REM <= <VCC>
TX_SOF_N <= TX_SOF_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_EOF_N <= TX_EOF_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_SRC_RDY_N <= TX_SRC_RDY_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
TX_DST_RDY_N => TX_SOF_N.OUTPUTSELECT
TX_DST_RDY_N => TX_EOF_N.OUTPUTSELECT
TX_DST_RDY_N => TX_SRC_RDY_N.OUTPUTSELECT
TX_DST_RDY_N => process_3.IN1
TX_DST_RDY_N => idle_r.OUTPUTSELECT
TX_DST_RDY_N => single_cycle_frame_r.OUTPUTSELECT
TX_DST_RDY_N => sof_r.OUTPUTSELECT
TX_DST_RDY_N => data_cycle_r.OUTPUTSELECT
TX_DST_RDY_N => eof_r.OUTPUTSELECT
USER_CLK => TX_SRC_RDY_N~reg0.CLK
USER_CLK => TX_EOF_N~reg0.CLK
USER_CLK => TX_SOF_N~reg0.CLK
USER_CLK => eof_r.CLK
USER_CLK => data_cycle_r.CLK
USER_CLK => sof_r.CLK
USER_CLK => single_cycle_frame_r.CLK
USER_CLK => idle_r.CLK
USER_CLK => ifg_size_r[3].CLK
USER_CLK => ifg_size_r[2].CLK
USER_CLK => ifg_size_r[1].CLK
USER_CLK => ifg_size_r[0].CLK
USER_CLK => bytes_sent_r[7].CLK
USER_CLK => bytes_sent_r[6].CLK
USER_CLK => bytes_sent_r[5].CLK
USER_CLK => bytes_sent_r[4].CLK
USER_CLK => bytes_sent_r[3].CLK
USER_CLK => bytes_sent_r[2].CLK
USER_CLK => bytes_sent_r[1].CLK
USER_CLK => bytes_sent_r[0].CLK
USER_CLK => frame_size_r[7].CLK
USER_CLK => frame_size_r[6].CLK
USER_CLK => frame_size_r[5].CLK
USER_CLK => frame_size_r[4].CLK
USER_CLK => frame_size_r[3].CLK
USER_CLK => frame_size_r[2].CLK
USER_CLK => frame_size_r[1].CLK
USER_CLK => frame_size_r[0].CLK
USER_CLK => TX_D[15]~reg0.CLK
USER_CLK => TX_D[14]~reg0.CLK
USER_CLK => TX_D[13]~reg0.CLK
USER_CLK => TX_D[12]~reg0.CLK
USER_CLK => TX_D[11]~reg0.CLK
USER_CLK => TX_D[10]~reg0.CLK
USER_CLK => TX_D[9]~reg0.CLK
USER_CLK => TX_D[8]~reg0.CLK
USER_CLK => TX_D[7]~reg0.CLK
USER_CLK => TX_D[6]~reg0.CLK
USER_CLK => TX_D[5]~reg0.CLK
USER_CLK => TX_D[4]~reg0.CLK
USER_CLK => TX_D[3]~reg0.CLK
USER_CLK => TX_D[2]~reg0.CLK
USER_CLK => TX_D[1]~reg0.CLK
USER_CLK => TX_D[0]~reg0.CLK
USER_CLK => tx_data_buf_2[0].CLK
USER_CLK => tx_data_buf_2[1].CLK
USER_CLK => tx_data_buf_2[2].CLK
USER_CLK => tx_data_buf_2[3].CLK
USER_CLK => tx_data_buf_2[4].CLK
USER_CLK => tx_data_buf_2[5].CLK
USER_CLK => tx_data_buf_2[6].CLK
USER_CLK => tx_data_buf_2[7].CLK
USER_CLK => tx_data_buf_2[8].CLK
USER_CLK => tx_data_buf_2[9].CLK
USER_CLK => tx_data_buf_2[10].CLK
USER_CLK => tx_data_buf_2[11].CLK
USER_CLK => tx_data_buf_2[12].CLK
USER_CLK => tx_data_buf_2[13].CLK
USER_CLK => tx_data_buf_2[14].CLK
USER_CLK => tx_data_buf_2[15].CLK
RESET => reset_c.IN0
CHANNEL_UP => reset_c.IN1


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i
rxclk <= MGT_alt4gxb:MGT_0.rx_clkout[0]
txclk <= MGT_alt4gxb:MGT_0.tx_clkout[0]
GXB_DOWN => MGT_alt4gxb:MGT_0.pll_powerdown[0]
GXB_DOWN => MGT_alt4gxb:MGT_0.gxb_powerdown[0]
TX_D[15] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[15]
TX_D[14] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[14]
TX_D[13] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[13]
TX_D[12] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[12]
TX_D[11] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[11]
TX_D[10] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[10]
TX_D[9] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[9]
TX_D[8] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[8]
TX_D[7] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[7]
TX_D[6] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[6]
TX_D[5] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[5]
TX_D[4] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[4]
TX_D[3] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[3]
TX_D[2] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[2]
TX_D[1] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[1]
TX_D[0] => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_D[0]
TX_REM => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_REM
TX_SRC_RDY_N => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_SRC_RDY_N
TX_SOF_N => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_SOF_N
TX_EOF_N => aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_EOF_N
TX_DST_RDY_N <= aurora_8b10b_v5_2_TX_LL:tx_ll_i.TX_DST_RDY_N
RX_D[15] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[15]
RX_D[14] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[14]
RX_D[13] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[13]
RX_D[12] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[12]
RX_D[11] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[11]
RX_D[10] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[10]
RX_D[9] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[9]
RX_D[8] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[8]
RX_D[7] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[7]
RX_D[6] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[6]
RX_D[5] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[5]
RX_D[4] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[4]
RX_D[3] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[3]
RX_D[2] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[2]
RX_D[1] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[1]
RX_D[0] <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_D[0]
RX_REM <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_REM
RX_SRC_RDY_N <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_SRC_RDY_N
RX_SOF_N <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_SOF_N
RX_EOF_N <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.RX_EOF_N
RXP => MGT_alt4gxb:MGT_0.rx_datain[0]
RXN => ~NO_FANOUT~
TXP <= MGT_alt4gxb:MGT_0.tx_dataout[0]
TXN <= TXN.DB_MAX_OUTPUT_PORT_TYPE
GTXQ4 => MGT_alt4gxb:MGT_0.pll_inclk
HARD_ERR <= aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i.CHANNEL_HARD_ERR
SOFT_ERR <= aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i.CHANNEL_SOFT_ERR
FRAME_ERR <= aurora_8b10b_v5_2_RX_LL:rx_ll_i.FRAME_ERR
CHANNEL_UP <= aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i.CHANNEL_UP
LANE_UP <= aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i.LANE_UP
WARN_CC => aurora_8b10b_v5_2_TX_LL:tx_ll_i.WARN_CC
DO_CC => aurora_8b10b_v5_2_TX_LL:tx_ll_i.DO_CC
INIT_CLK => MGT_alt4gxb:MGT_0.cal_blk_clk
USER_CLK => aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_TX_LL:tx_ll_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_RX_LL:rx_ll_i.USER_CLK
SYNC_CLK => ~NO_FANOUT~
RESET => aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i.RESET_SYMGEN
RESET => aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i.RESET
POWER_DOWN => aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i.POWER_DOWN
LOOPBACK[0] => ~NO_FANOUT~
LOOPBACK[1] => ~NO_FANOUT~
LOOPBACK[2] => ~NO_FANOUT~
GT_RESET => ~NO_FANOUT~
TX_OUT_CLK <= comb.DB_MAX_OUTPUT_PORT_TYPE
TX_LOCK <= MGT_alt4gxb:MGT_0.pll_locked[0]


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i
RX_DATA[0] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[8]
RX_DATA[1] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[9]
RX_DATA[2] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[10]
RX_DATA[3] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[11]
RX_DATA[4] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[12]
RX_DATA[5] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[13]
RX_DATA[6] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[14]
RX_DATA[7] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[15]
RX_DATA[8] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[0]
RX_DATA[9] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[1]
RX_DATA[10] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[2]
RX_DATA[11] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[3]
RX_DATA[12] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[4]
RX_DATA[13] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[5]
RX_DATA[14] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[6]
RX_DATA[15] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_DATA[7]
RX_NOT_IN_TABLE[0] => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_NOT_IN_TABLE[0]
RX_NOT_IN_TABLE[0] => aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.RX_NOT_IN_TABLE[1]
RX_NOT_IN_TABLE[1] => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_NOT_IN_TABLE[1]
RX_NOT_IN_TABLE[1] => aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.RX_NOT_IN_TABLE[0]
RX_DISP_ERR[0] => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_DISP_ERR[0]
RX_DISP_ERR[0] => aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.RX_DISP_ERR[1]
RX_DISP_ERR[1] => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_DISP_ERR[1]
RX_DISP_ERR[1] => aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.RX_DISP_ERR[0]
RX_CHAR_IS_K[0] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_CHAR_IS_K[1]
RX_CHAR_IS_K[1] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_CHAR_IS_K[0]
RX_CHAR_IS_COMMA[0] => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_CHAR_IS_COMMA[0]
RX_CHAR_IS_COMMA[0] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_CHAR_IS_COMMA[1]
RX_CHAR_IS_COMMA[1] => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_CHAR_IS_COMMA[1]
RX_CHAR_IS_COMMA[1] => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_CHAR_IS_COMMA[0]
RX_STATUS[0] => aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i.RX_STATUS[0]
RX_STATUS[1] => aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i.RX_STATUS[1]
RX_STATUS[2] => aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i.RX_STATUS[2]
RX_STATUS[3] => aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i.RX_STATUS[3]
RX_STATUS[4] => aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i.RX_STATUS[4]
RX_STATUS[5] => aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i.RX_STATUS[5]
RX_BUF_ERR => aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.RX_BUF_ERR
TX_BUF_ERR => aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.TX_BUF_ERR
RX_REALIGN => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_REALIGN
RX_REALIGN => aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.RX_REALIGN
RX_POLARITY <= aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_POLARITY
RX_RESET <= aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RX_RESET
TX_CHAR_IS_K[0] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_CHAR_IS_K[1]
TX_CHAR_IS_K[1] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_CHAR_IS_K[0]
TX_DATA[0] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[8]
TX_DATA[1] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[9]
TX_DATA[2] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[10]
TX_DATA[3] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[11]
TX_DATA[4] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[12]
TX_DATA[5] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[13]
TX_DATA[6] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[14]
TX_DATA[7] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[15]
TX_DATA[8] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[0]
TX_DATA[9] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[1]
TX_DATA[10] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[2]
TX_DATA[11] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[3]
TX_DATA[12] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[4]
TX_DATA[13] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[5]
TX_DATA[14] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[6]
TX_DATA[15] <= aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_DATA[7]
TX_RESET <= aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.TX_RESET
ENA_COMMA_ALIGN <= aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.ENA_COMMA_ALIGN
GEN_SCP => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_SCP
GEN_ECP => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_ECP
GEN_PAD => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_PAD
TX_PE_DATA[15] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[15]
TX_PE_DATA[14] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[14]
TX_PE_DATA[13] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[13]
TX_PE_DATA[12] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[12]
TX_PE_DATA[11] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[11]
TX_PE_DATA[10] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[10]
TX_PE_DATA[9] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[9]
TX_PE_DATA[8] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[8]
TX_PE_DATA[7] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[7]
TX_PE_DATA[6] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[6]
TX_PE_DATA[5] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[5]
TX_PE_DATA[4] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[4]
TX_PE_DATA[3] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[3]
TX_PE_DATA[2] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[2]
TX_PE_DATA[1] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[1]
TX_PE_DATA[0] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA[0]
TX_PE_DATA_V => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.TX_PE_DATA_V
GEN_CC => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_CC
RX_PAD <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PAD
RX_PE_DATA[15] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[15]
RX_PE_DATA[14] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[14]
RX_PE_DATA[13] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[13]
RX_PE_DATA[12] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[12]
RX_PE_DATA[11] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[11]
RX_PE_DATA[10] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[10]
RX_PE_DATA[9] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[9]
RX_PE_DATA[8] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[8]
RX_PE_DATA[7] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[7]
RX_PE_DATA[6] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[6]
RX_PE_DATA[5] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[5]
RX_PE_DATA[4] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[4]
RX_PE_DATA[3] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[3]
RX_PE_DATA[2] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[2]
RX_PE_DATA[1] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[1]
RX_PE_DATA[0] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA[0]
RX_PE_DATA_V <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_PE_DATA_V
RX_SCP <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_SCP
RX_ECP <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RX_ECP
GEN_A => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_A
GEN_K[1] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_K[1]
GEN_K[0] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_K[0]
GEN_R[1] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_R[1]
GEN_R[0] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_R[0]
GEN_V[1] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_V[1]
GEN_V[0] => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.GEN_V[0]
LANE_UP <= aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.LANE_UP
SOFT_ERR <= aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.SOFT_ERR
HARD_ERR <= aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.HARD_ERR
CHANNEL_BOND_LOAD <= aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i.CHANNEL_BOND_LOAD
GOT_A[1] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.GOT_A[1]
GOT_A[0] <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.GOT_A[0]
GOT_V <= aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.GOT_V
USER_CLK => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_ERR_DETECT:err_detect_i.USER_CLK
RESET_SYMGEN => aurora_8b10b_v5_2_SYM_GEN:sym_gen_i.RESET
RESET => aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i.RESET
RESET => aurora_8b10b_v5_2_SYM_DEC:sym_dec_i.RESET


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i
RX_NOT_IN_TABLE[0] => Equal1.IN1
RX_NOT_IN_TABLE[1] => Equal1.IN0
RX_DISP_ERR[0] => Equal0.IN1
RX_DISP_ERR[1] => Equal0.IN0
RX_CHAR_IS_COMMA[0] => RX_CHAR_IS_COMMA_R[0].DATAIN
RX_CHAR_IS_COMMA[1] => RX_CHAR_IS_COMMA_R[1].DATAIN
RX_REALIGN => next_begin_c.IN1
RX_REALIGN => next_polarity_c.IN1
RX_REALIGN => next_realign_c.IN1
RX_RESET <= rst_r.DB_MAX_OUTPUT_PORT_TYPE
TX_RESET <= rst_r.DB_MAX_OUTPUT_PORT_TYPE
RX_POLARITY <= rx_polarity_r.DB_MAX_OUTPUT_PORT_TYPE
ENA_COMMA_ALIGN <= align_r.DB_MAX_OUTPUT_PORT_TYPE
GEN_K <= GEN_K_Buffer.DB_MAX_OUTPUT_PORT_TYPE
GEN_SP_DATA[1] <= send_sp_c.DB_MAX_OUTPUT_PORT_TYPE
GEN_SP_DATA[0] <= GEN_SP_DATA_Buffer.DB_MAX_OUTPUT_PORT_TYPE
GEN_SPA_DATA[1] <= ack_r.DB_MAX_OUTPUT_PORT_TYPE
GEN_SPA_DATA[0] <= GEN_SPA_DATA_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_SP => process_10.IN1
RX_SPA => process_9.IN1
RX_NEG => process_14.IN1
RX_NEG => next_ack_c.IN1
DO_WORD_ALIGN <= DO_WORD_ALIGN_Buffer.DB_MAX_OUTPUT_PORT_TYPE
ENABLE_ERR_DETECT <= ENABLE_ERR_DETECT_Buffer.DB_MAX_OUTPUT_PORT_TYPE
HARD_ERR_RESET => process_0.IN0
LANE_UP <= FDR:lane_up_flop_i.Q
USER_CLK => FDR:lane_up_flop_i.C
USER_CLK => rx_polarity_r.CLK
USER_CLK => do_watchdog_count_r.CLK
USER_CLK => prev_count_128d_done_r.CLK
USER_CLK => counter5_r[15].CLK
USER_CLK => counter5_r[14].CLK
USER_CLK => counter5_r[13].CLK
USER_CLK => counter5_r[12].CLK
USER_CLK => counter5_r[11].CLK
USER_CLK => counter5_r[10].CLK
USER_CLK => counter5_r[9].CLK
USER_CLK => counter5_r[8].CLK
USER_CLK => counter5_r[7].CLK
USER_CLK => counter5_r[6].CLK
USER_CLK => counter5_r[5].CLK
USER_CLK => counter5_r[4].CLK
USER_CLK => counter5_r[3].CLK
USER_CLK => counter5_r[2].CLK
USER_CLK => counter5_r[1].CLK
USER_CLK => counter5_r[0].CLK
USER_CLK => counter4_r[15].CLK
USER_CLK => counter4_r[14].CLK
USER_CLK => counter4_r[13].CLK
USER_CLK => counter4_r[12].CLK
USER_CLK => counter4_r[11].CLK
USER_CLK => counter4_r[10].CLK
USER_CLK => counter4_r[9].CLK
USER_CLK => counter4_r[8].CLK
USER_CLK => counter4_r[7].CLK
USER_CLK => counter4_r[6].CLK
USER_CLK => counter4_r[5].CLK
USER_CLK => counter4_r[4].CLK
USER_CLK => counter4_r[3].CLK
USER_CLK => counter4_r[2].CLK
USER_CLK => counter4_r[1].CLK
USER_CLK => counter4_r[0].CLK
USER_CLK => counter3_r[3].CLK
USER_CLK => counter3_r[2].CLK
USER_CLK => counter3_r[1].CLK
USER_CLK => counter3_r[0].CLK
USER_CLK => counter2_r[15].CLK
USER_CLK => counter2_r[14].CLK
USER_CLK => counter2_r[13].CLK
USER_CLK => counter2_r[12].CLK
USER_CLK => counter2_r[11].CLK
USER_CLK => counter2_r[10].CLK
USER_CLK => counter2_r[9].CLK
USER_CLK => counter2_r[8].CLK
USER_CLK => counter2_r[7].CLK
USER_CLK => counter2_r[6].CLK
USER_CLK => counter2_r[5].CLK
USER_CLK => counter2_r[4].CLK
USER_CLK => counter2_r[3].CLK
USER_CLK => counter2_r[2].CLK
USER_CLK => counter2_r[1].CLK
USER_CLK => counter2_r[0].CLK
USER_CLK => comma_over_two_cycles_r.CLK
USER_CLK => prev_char_was_comma_r.CLK
USER_CLK => RX_CHAR_IS_COMMA_R[0].CLK
USER_CLK => RX_CHAR_IS_COMMA_R[1].CLK
USER_CLK => reset_count_r.CLK
USER_CLK => counter1_r[7].CLK
USER_CLK => counter1_r[6].CLK
USER_CLK => counter1_r[5].CLK
USER_CLK => counter1_r[4].CLK
USER_CLK => counter1_r[3].CLK
USER_CLK => counter1_r[2].CLK
USER_CLK => counter1_r[1].CLK
USER_CLK => counter1_r[0].CLK
USER_CLK => odd_word_r.CLK
USER_CLK => ENABLE_ERR_DETECT_Buffer.CLK
USER_CLK => ready_r.CLK
USER_CLK => ack_r.CLK
USER_CLK => polarity_r.CLK
USER_CLK => realign_r.CLK
USER_CLK => align_r.CLK
USER_CLK => rst_r.CLK
USER_CLK => begin_r.CLK
RESET => process_0.IN1
RESET => reset_count_r.IN1
RESET => FDR:lane_up_flop_i.R


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_LANE_INIT_SM:lane_init_sm_i|FDR:lane_up_flop_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q.DATAA
R => Q.OUTPUTSELECT


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_CHBOND_COUNT_DEC:chbond_count_dec_i
RX_STATUS[0] => Equal0.IN5
RX_STATUS[1] => Equal0.IN4
RX_STATUS[2] => Equal0.IN3
RX_STATUS[3] => Equal0.IN1
RX_STATUS[4] => Equal0.IN0
RX_STATUS[5] => Equal0.IN2
CHANNEL_BOND_LOAD <= CHANNEL_BOND_LOAD_Buffer.DB_MAX_OUTPUT_PORT_TYPE
USER_CLK => CHANNEL_BOND_LOAD_Buffer.CLK


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_GEN:sym_gen_i
GEN_SCP => gen_scp_r.DATAIN
GEN_ECP => gen_ecp_r.DATAIN
GEN_PAD => gen_pad_r.DATAIN
TX_PE_DATA[15] => tx_pe_data_r[15].DATAIN
TX_PE_DATA[14] => tx_pe_data_r[14].DATAIN
TX_PE_DATA[13] => tx_pe_data_r[13].DATAIN
TX_PE_DATA[12] => tx_pe_data_r[12].DATAIN
TX_PE_DATA[11] => tx_pe_data_r[11].DATAIN
TX_PE_DATA[10] => tx_pe_data_r[10].DATAIN
TX_PE_DATA[9] => tx_pe_data_r[9].DATAIN
TX_PE_DATA[8] => tx_pe_data_r[8].DATAIN
TX_PE_DATA[7] => tx_pe_data_r[7].DATAIN
TX_PE_DATA[6] => tx_pe_data_r[6].DATAIN
TX_PE_DATA[5] => tx_pe_data_r[5].DATAIN
TX_PE_DATA[4] => tx_pe_data_r[4].DATAIN
TX_PE_DATA[3] => tx_pe_data_r[3].DATAIN
TX_PE_DATA[2] => tx_pe_data_r[2].DATAIN
TX_PE_DATA[1] => tx_pe_data_r[1].DATAIN
TX_PE_DATA[0] => tx_pe_data_r[0].DATAIN
TX_PE_DATA_V => tx_pe_data_v_r.DATAIN
GEN_CC => gen_cc_r.DATAIN
GEN_A => gen_a_r.DATAIN
GEN_K[1] => gen_k_r[1].DATAIN
GEN_K[0] => gen_k_r[0].DATAIN
GEN_R[1] => gen_r_r[1].DATAIN
GEN_R[0] => gen_r_r[0].DATAIN
GEN_V[1] => gen_v_r[1].DATAIN
GEN_V[0] => gen_v_r[0].DATAIN
GEN_K_FSM => gen_k_fsm_r.DATAIN
GEN_SP_DATA[1] => gen_sp_data_r[1].DATAIN
GEN_SP_DATA[0] => gen_sp_data_r[0].DATAIN
GEN_SPA_DATA[1] => gen_spa_data_r[1].DATAIN
GEN_SPA_DATA[0] => gen_spa_data_r[0].DATAIN
TX_CHAR_IS_K[0] <= TX_CHAR_IS_K_Buffer[0].DB_MAX_OUTPUT_PORT_TYPE
TX_CHAR_IS_K[1] <= TX_CHAR_IS_K_Buffer[1].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[0] <= TX_DATA_Buffer[0].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[1] <= TX_DATA_Buffer[1].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[2] <= TX_DATA_Buffer[2].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[3] <= TX_DATA_Buffer[3].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[4] <= TX_DATA_Buffer[4].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[5] <= TX_DATA_Buffer[5].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[6] <= TX_DATA_Buffer[6].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[7] <= TX_DATA_Buffer[7].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[8] <= TX_DATA_Buffer[8].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[9] <= TX_DATA_Buffer[9].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[10] <= TX_DATA_Buffer[10].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[11] <= TX_DATA_Buffer[11].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[12] <= TX_DATA_Buffer[12].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[13] <= TX_DATA_Buffer[13].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[14] <= TX_DATA_Buffer[14].DB_MAX_OUTPUT_PORT_TYPE
TX_DATA[15] <= TX_DATA_Buffer[15].DB_MAX_OUTPUT_PORT_TYPE
USER_CLK => TX_CHAR_IS_K_Buffer[0].CLK
USER_CLK => TX_DATA_Buffer[0].CLK
USER_CLK => TX_DATA_Buffer[1].CLK
USER_CLK => TX_DATA_Buffer[2].CLK
USER_CLK => TX_DATA_Buffer[3].CLK
USER_CLK => TX_DATA_Buffer[4].CLK
USER_CLK => TX_DATA_Buffer[5].CLK
USER_CLK => TX_DATA_Buffer[6].CLK
USER_CLK => TX_DATA_Buffer[7].CLK
USER_CLK => TX_CHAR_IS_K_Buffer[1].CLK
USER_CLK => TX_DATA_Buffer[8].CLK
USER_CLK => TX_DATA_Buffer[9].CLK
USER_CLK => TX_DATA_Buffer[10].CLK
USER_CLK => TX_DATA_Buffer[11].CLK
USER_CLK => TX_DATA_Buffer[12].CLK
USER_CLK => TX_DATA_Buffer[13].CLK
USER_CLK => TX_DATA_Buffer[14].CLK
USER_CLK => TX_DATA_Buffer[15].CLK
USER_CLK => gen_spa_data_r[1].CLK
USER_CLK => gen_spa_data_r[0].CLK
USER_CLK => gen_sp_data_r[1].CLK
USER_CLK => gen_sp_data_r[0].CLK
USER_CLK => gen_k_fsm_r.CLK
USER_CLK => gen_v_r[1].CLK
USER_CLK => gen_v_r[0].CLK
USER_CLK => gen_r_r[1].CLK
USER_CLK => gen_r_r[0].CLK
USER_CLK => gen_k_r[1].CLK
USER_CLK => gen_k_r[0].CLK
USER_CLK => gen_a_r.CLK
USER_CLK => gen_cc_r.CLK
USER_CLK => tx_pe_data_v_r.CLK
USER_CLK => tx_pe_data_r[15].CLK
USER_CLK => tx_pe_data_r[14].CLK
USER_CLK => tx_pe_data_r[13].CLK
USER_CLK => tx_pe_data_r[12].CLK
USER_CLK => tx_pe_data_r[11].CLK
USER_CLK => tx_pe_data_r[10].CLK
USER_CLK => tx_pe_data_r[9].CLK
USER_CLK => tx_pe_data_r[8].CLK
USER_CLK => tx_pe_data_r[7].CLK
USER_CLK => tx_pe_data_r[6].CLK
USER_CLK => tx_pe_data_r[5].CLK
USER_CLK => tx_pe_data_r[4].CLK
USER_CLK => tx_pe_data_r[3].CLK
USER_CLK => tx_pe_data_r[2].CLK
USER_CLK => tx_pe_data_r[1].CLK
USER_CLK => tx_pe_data_r[0].CLK
USER_CLK => gen_pad_r.CLK
USER_CLK => gen_ecp_r.CLK
USER_CLK => gen_scp_r.CLK
RESET => TX_CHAR_IS_K_Buffer.OUTPUTSELECT
RESET => TX_CHAR_IS_K_Buffer.OUTPUTSELECT


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_SYM_DEC:sym_dec_i
RX_PAD <= RX_PAD_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[15] <= RX_PE_DATA_Buffer[15].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[14] <= RX_PE_DATA_Buffer[14].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[13] <= RX_PE_DATA_Buffer[13].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[12] <= RX_PE_DATA_Buffer[12].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[11] <= RX_PE_DATA_Buffer[11].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[10] <= RX_PE_DATA_Buffer[10].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[9] <= RX_PE_DATA_Buffer[9].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[8] <= RX_PE_DATA_Buffer[8].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[7] <= RX_PE_DATA_Buffer[7].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[6] <= RX_PE_DATA_Buffer[6].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[5] <= RX_PE_DATA_Buffer[5].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[4] <= RX_PE_DATA_Buffer[4].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[3] <= RX_PE_DATA_Buffer[3].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[2] <= RX_PE_DATA_Buffer[2].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[1] <= RX_PE_DATA_Buffer[1].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA[0] <= RX_PE_DATA_Buffer[0].DB_MAX_OUTPUT_PORT_TYPE
RX_PE_DATA_V <= RX_PE_DATA_V_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_SCP <= RX_SCP_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_ECP <= RX_ECP_Buffer.DB_MAX_OUTPUT_PORT_TYPE
DO_WORD_ALIGN => process_0.IN1
RX_SP <= RX_SP_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_SPA <= RX_SPA_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_NEG <= RX_NEG_Buffer.DB_MAX_OUTPUT_PORT_TYPE
GOT_A[1] <= GOT_A_Buffer[1].DB_MAX_OUTPUT_PORT_TYPE
GOT_A[0] <= GOT_A_Buffer[0].DB_MAX_OUTPUT_PORT_TYPE
GOT_V <= GOT_V_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_DATA[0] => word_aligned_data_r.DATAA
RX_DATA[0] => word_aligned_data_r.DATAB
RX_DATA[1] => word_aligned_data_r.DATAA
RX_DATA[1] => word_aligned_data_r.DATAB
RX_DATA[2] => word_aligned_data_r.DATAA
RX_DATA[2] => word_aligned_data_r.DATAB
RX_DATA[3] => word_aligned_data_r.DATAA
RX_DATA[3] => word_aligned_data_r.DATAB
RX_DATA[4] => word_aligned_data_r.DATAA
RX_DATA[4] => word_aligned_data_r.DATAB
RX_DATA[5] => word_aligned_data_r.DATAA
RX_DATA[5] => word_aligned_data_r.DATAB
RX_DATA[6] => word_aligned_data_r.DATAA
RX_DATA[6] => word_aligned_data_r.DATAB
RX_DATA[7] => word_aligned_data_r.DATAA
RX_DATA[7] => word_aligned_data_r.DATAB
RX_DATA[8] => word_aligned_data_r.DATAB
RX_DATA[8] => word_aligned_data_r.DATAA
RX_DATA[9] => word_aligned_data_r.DATAB
RX_DATA[9] => word_aligned_data_r.DATAA
RX_DATA[10] => word_aligned_data_r.DATAB
RX_DATA[10] => word_aligned_data_r.DATAA
RX_DATA[11] => word_aligned_data_r.DATAB
RX_DATA[11] => word_aligned_data_r.DATAA
RX_DATA[12] => word_aligned_data_r.DATAB
RX_DATA[12] => word_aligned_data_r.DATAA
RX_DATA[13] => word_aligned_data_r.DATAB
RX_DATA[13] => word_aligned_data_r.DATAA
RX_DATA[14] => word_aligned_data_r.DATAB
RX_DATA[14] => word_aligned_data_r.DATAA
RX_DATA[15] => word_aligned_data_r.DATAB
RX_DATA[15] => word_aligned_data_r.DATAA
RX_CHAR_IS_K[0] => Mux0.IN3
RX_CHAR_IS_K[0] => word_aligned_control_bits_r.DATAA
RX_CHAR_IS_K[0] => word_aligned_control_bits_r.DATAB
RX_CHAR_IS_K[1] => Mux0.IN2
RX_CHAR_IS_K[1] => word_aligned_control_bits_r.DATAB
RX_CHAR_IS_K[1] => word_aligned_control_bits_r.DATAA
RX_CHAR_IS_COMMA[0] => Mux0.IN5
RX_CHAR_IS_COMMA[1] => Mux0.IN4
USER_CLK => first_v_received_r.CLK
USER_CLK => GOT_V_Buffer.CLK
USER_CLK => rx_v_d_r[3].CLK
USER_CLK => rx_v_d_r[2].CLK
USER_CLK => rx_v_d_r[1].CLK
USER_CLK => rx_v_d_r[0].CLK
USER_CLK => prev_beat_v_r.CLK
USER_CLK => prev_beat_v_d_r[3].CLK
USER_CLK => prev_beat_v_d_r[2].CLK
USER_CLK => prev_beat_v_d_r[1].CLK
USER_CLK => prev_beat_v_d_r[0].CLK
USER_CLK => GOT_A_Buffer[1].CLK
USER_CLK => GOT_A_Buffer[0].CLK
USER_CLK => got_a_d_r[3].CLK
USER_CLK => got_a_d_r[2].CLK
USER_CLK => got_a_d_r[1].CLK
USER_CLK => got_a_d_r[0].CLK
USER_CLK => RX_NEG_Buffer.CLK
USER_CLK => rx_spa_neg_d_r[1].CLK
USER_CLK => rx_spa_neg_d_r[0].CLK
USER_CLK => rx_sp_neg_d_r[1].CLK
USER_CLK => rx_sp_neg_d_r[0].CLK
USER_CLK => RX_SPA_Buffer.CLK
USER_CLK => rx_spa_d_r[3].CLK
USER_CLK => rx_spa_d_r[2].CLK
USER_CLK => rx_spa_d_r[1].CLK
USER_CLK => rx_spa_d_r[0].CLK
USER_CLK => RX_SP_Buffer.CLK
USER_CLK => rx_sp_d_r[3].CLK
USER_CLK => rx_sp_d_r[2].CLK
USER_CLK => rx_sp_d_r[1].CLK
USER_CLK => rx_sp_d_r[0].CLK
USER_CLK => prev_beat_spa_r.CLK
USER_CLK => prev_beat_spa_d_r[3].CLK
USER_CLK => prev_beat_spa_d_r[2].CLK
USER_CLK => prev_beat_spa_d_r[1].CLK
USER_CLK => prev_beat_spa_d_r[0].CLK
USER_CLK => prev_beat_sp_r.CLK
USER_CLK => prev_beat_sp_d_r[3].CLK
USER_CLK => prev_beat_sp_d_r[2].CLK
USER_CLK => prev_beat_sp_d_r[1].CLK
USER_CLK => prev_beat_sp_d_r[0].CLK
USER_CLK => RX_ECP_Buffer.CLK
USER_CLK => rx_ecp_d_r[3].CLK
USER_CLK => rx_ecp_d_r[2].CLK
USER_CLK => rx_ecp_d_r[1].CLK
USER_CLK => rx_ecp_d_r[0].CLK
USER_CLK => RX_SCP_Buffer.CLK
USER_CLK => rx_scp_d_r[3].CLK
USER_CLK => rx_scp_d_r[2].CLK
USER_CLK => rx_scp_d_r[1].CLK
USER_CLK => rx_scp_d_r[0].CLK
USER_CLK => RX_PE_DATA_V_Buffer.CLK
USER_CLK => RX_PAD_Buffer.CLK
USER_CLK => rx_pad_d_r[1].CLK
USER_CLK => rx_pad_d_r[0].CLK
USER_CLK => rx_pe_control_r[1].CLK
USER_CLK => rx_pe_control_r[0].CLK
USER_CLK => RX_PE_DATA_Buffer[15].CLK
USER_CLK => RX_PE_DATA_Buffer[14].CLK
USER_CLK => RX_PE_DATA_Buffer[13].CLK
USER_CLK => RX_PE_DATA_Buffer[12].CLK
USER_CLK => RX_PE_DATA_Buffer[11].CLK
USER_CLK => RX_PE_DATA_Buffer[10].CLK
USER_CLK => RX_PE_DATA_Buffer[9].CLK
USER_CLK => RX_PE_DATA_Buffer[8].CLK
USER_CLK => RX_PE_DATA_Buffer[7].CLK
USER_CLK => RX_PE_DATA_Buffer[6].CLK
USER_CLK => RX_PE_DATA_Buffer[5].CLK
USER_CLK => RX_PE_DATA_Buffer[4].CLK
USER_CLK => RX_PE_DATA_Buffer[3].CLK
USER_CLK => RX_PE_DATA_Buffer[2].CLK
USER_CLK => RX_PE_DATA_Buffer[1].CLK
USER_CLK => RX_PE_DATA_Buffer[0].CLK
USER_CLK => rx_pe_data_r[15].CLK
USER_CLK => rx_pe_data_r[14].CLK
USER_CLK => rx_pe_data_r[13].CLK
USER_CLK => rx_pe_data_r[12].CLK
USER_CLK => rx_pe_data_r[11].CLK
USER_CLK => rx_pe_data_r[10].CLK
USER_CLK => rx_pe_data_r[9].CLK
USER_CLK => rx_pe_data_r[8].CLK
USER_CLK => rx_pe_data_r[7].CLK
USER_CLK => rx_pe_data_r[6].CLK
USER_CLK => rx_pe_data_r[5].CLK
USER_CLK => rx_pe_data_r[4].CLK
USER_CLK => rx_pe_data_r[3].CLK
USER_CLK => rx_pe_data_r[2].CLK
USER_CLK => rx_pe_data_r[1].CLK
USER_CLK => rx_pe_data_r[0].CLK
USER_CLK => word_aligned_control_bits_r[1].CLK
USER_CLK => word_aligned_control_bits_r[0].CLK
USER_CLK => word_aligned_data_r[15].CLK
USER_CLK => word_aligned_data_r[14].CLK
USER_CLK => word_aligned_data_r[13].CLK
USER_CLK => word_aligned_data_r[12].CLK
USER_CLK => word_aligned_data_r[11].CLK
USER_CLK => word_aligned_data_r[10].CLK
USER_CLK => word_aligned_data_r[9].CLK
USER_CLK => word_aligned_data_r[8].CLK
USER_CLK => word_aligned_data_r[7].CLK
USER_CLK => word_aligned_data_r[6].CLK
USER_CLK => word_aligned_data_r[5].CLK
USER_CLK => word_aligned_data_r[4].CLK
USER_CLK => word_aligned_data_r[3].CLK
USER_CLK => word_aligned_data_r[2].CLK
USER_CLK => word_aligned_data_r[1].CLK
USER_CLK => word_aligned_data_r[0].CLK
USER_CLK => left_aligned_r.CLK
RESET => first_v_received_r.OUTPUTSELECT


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_AURORA_LANE:aurora_lane_0_i|aurora_8b10b_v5_2_ERR_DETECT:err_detect_i
ENABLE_ERR_DETECT => soft_err_r.OUTPUTSELECT
ENABLE_ERR_DETECT => soft_err_r.OUTPUTSELECT
ENABLE_ERR_DETECT => hard_err_flop_r.OUTPUTSELECT
ENABLE_ERR_DETECT => HARD_ERR_Buffer.OUTPUTSELECT
ENABLE_ERR_DETECT => bucket_full_r.OUTPUTSELECT
ENABLE_ERR_DETECT => count_r.OUTPUTSELECT
ENABLE_ERR_DETECT => count_r.OUTPUTSELECT
ENABLE_ERR_DETECT => good_count_r.OUTPUTSELECT
ENABLE_ERR_DETECT => good_count_r.OUTPUTSELECT
HARD_ERR_RESET <= hard_err_flop_r.DB_MAX_OUTPUT_PORT_TYPE
SOFT_ERR <= SOFT_ERR_Buffer.DB_MAX_OUTPUT_PORT_TYPE
HARD_ERR <= HARD_ERR_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_BUF_ERR => hard_err_flop_r.IN0
RX_DISP_ERR[0] => soft_err_r.IN0
RX_DISP_ERR[1] => soft_err_r.IN0
RX_NOT_IN_TABLE[0] => soft_err_r.IN1
RX_NOT_IN_TABLE[1] => soft_err_r.IN1
TX_BUF_ERR => hard_err_flop_r.IN1
RX_REALIGN => hard_err_flop_r.IN1
USER_CLK => bucket_full_r.CLK
USER_CLK => count_r[1].CLK
USER_CLK => count_r[0].CLK
USER_CLK => good_count_r[1].CLK
USER_CLK => good_count_r[0].CLK
USER_CLK => HARD_ERR_Buffer.CLK
USER_CLK => hard_err_flop_r.CLK
USER_CLK => SOFT_ERR_Buffer.CLK
USER_CLK => soft_err_flop_r.CLK
USER_CLK => soft_err_r[1].CLK
USER_CLK => soft_err_r[0].CLK


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|MGT_alt4gxb:MGT_0
cal_blk_clk => cal_blk0.CLK
gxb_powerdown[0] => cent_unit0.QUADRESET
pll_inclk => rx_cdr_pll0.CLK
pll_inclk => tx_pll0.CLK
pll_locked[0] <= tx_pll0.LOCKED
pll_powerdown[0] => cent_unit0.TX_PLL_RESET
reconfig_clk => cent_unit0.DPRIOCLK
reconfig_clk => cent_unit0.FIXEDCLK
reconfig_fromgxb[0] <= cent_unit0.DPRIOOUT
reconfig_fromgxb[1] <= receive_pma0.ANALOGTESTBUS2
reconfig_fromgxb[2] <= receive_pma0.ANALOGTESTBUS3
reconfig_fromgxb[3] <= receive_pma0.ANALOGTESTBUS4
reconfig_fromgxb[4] <= receive_pma0.ANALOGTESTBUS5
reconfig_fromgxb[5] <= <GND>
reconfig_fromgxb[6] <= <GND>
reconfig_fromgxb[7] <= <GND>
reconfig_fromgxb[8] <= <GND>
reconfig_fromgxb[9] <= <GND>
reconfig_fromgxb[10] <= <GND>
reconfig_fromgxb[11] <= <GND>
reconfig_fromgxb[12] <= <GND>
reconfig_fromgxb[13] <= <GND>
reconfig_fromgxb[14] <= <GND>
reconfig_fromgxb[15] <= <GND>
reconfig_fromgxb[16] <= <GND>
reconfig_togxb[0] => cent_unit0.DPRIOIN
reconfig_togxb[1] => cent_unit0.DPRIODISABLE
reconfig_togxb[2] => cent_unit0.DPRIOLOAD
reconfig_togxb[3] => receive_pcs0.CDRCTRL_LOCK_TO_REF_CLK
rx_clkout[0] <= receive_pcs0.CLK
rx_ctrldetect[0] <= receive_pcs0.CTRLDETECT
rx_ctrldetect[1] <= receive_pcs0.CTRLDETECT1
rx_datain[0] => receive_pma0.DATAIN
rx_dataout[0] <= receive_pcs0.DATAOUT
rx_dataout[1] <= receive_pcs0.DATAOUT1
rx_dataout[2] <= receive_pcs0.DATAOUT2
rx_dataout[3] <= receive_pcs0.DATAOUT3
rx_dataout[4] <= receive_pcs0.DATAOUT4
rx_dataout[5] <= receive_pcs0.DATAOUT5
rx_dataout[6] <= receive_pcs0.DATAOUT6
rx_dataout[7] <= receive_pcs0.DATAOUT7
rx_dataout[8] <= receive_pcs0.DATAOUT8
rx_dataout[9] <= receive_pcs0.DATAOUT9
rx_dataout[10] <= receive_pcs0.DATAOUT10
rx_dataout[11] <= receive_pcs0.DATAOUT11
rx_dataout[12] <= receive_pcs0.DATAOUT12
rx_dataout[13] <= receive_pcs0.DATAOUT13
rx_dataout[14] <= receive_pcs0.DATAOUT14
rx_dataout[15] <= receive_pcs0.DATAOUT15
rx_digitalreset[0] => cent_unit0.RXDIGITALRESET
rx_disperr[0] <= receive_pcs0.DISPERR
rx_disperr[1] <= receive_pcs0.DISPERR1
rx_enapatternalign[0] => receive_pcs0.ENAPATTERNALIGN
rx_errdetect[0] <= receive_pcs0.ERRDETECT
rx_errdetect[1] <= receive_pcs0.ERRDETECT1
rx_invpolarity[0] => receive_pcs0.INVPOL
rx_patterndetect[0] <= receive_pcs0.PATTERNDETECT
rx_patterndetect[1] <= receive_pcs0.PATTERNDETECT1
rx_phase_comp_fifo_error[0] <= wire_w_lg_w_rx_phfifooverflowout_range288w289w.DB_MAX_OUTPUT_PORT_TYPE
rx_syncstatus[0] <= receive_pcs0.SYNCSTATUS
rx_syncstatus[1] <= receive_pcs0.SYNCSTATUS1
tx_clkout[0] <= transmit_pcs0.CLK
tx_ctrlenable[0] => transmit_pcs0.CTRLENABLE
tx_ctrlenable[1] => transmit_pcs0.CTRLENABLE1
tx_datain[0] => transmit_pcs0.DATAIN
tx_datain[1] => transmit_pcs0.DATAIN1
tx_datain[2] => transmit_pcs0.DATAIN2
tx_datain[3] => transmit_pcs0.DATAIN3
tx_datain[4] => transmit_pcs0.DATAIN4
tx_datain[5] => transmit_pcs0.DATAIN5
tx_datain[6] => transmit_pcs0.DATAIN6
tx_datain[7] => transmit_pcs0.DATAIN7
tx_datain[8] => transmit_pcs0.DATAIN8
tx_datain[9] => transmit_pcs0.DATAIN9
tx_datain[10] => transmit_pcs0.DATAIN10
tx_datain[11] => transmit_pcs0.DATAIN11
tx_datain[12] => transmit_pcs0.DATAIN12
tx_datain[13] => transmit_pcs0.DATAIN13
tx_datain[14] => transmit_pcs0.DATAIN14
tx_datain[15] => transmit_pcs0.DATAIN15
tx_dataout[0] <= transmit_pma0.DATAOUT
tx_digitalreset[0] => cent_unit0.TXDIGITALRESET
tx_phase_comp_fifo_error[0] <= wire_w_lg_w_tx_phfifooverflowout_range181w182w.DB_MAX_OUTPUT_PORT_TYPE


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i
CH_BOND_DONE => aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.CH_BOND_DONE
EN_CHAN_SYNC <= aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.EN_CHAN_SYNC
LANE_UP => aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i.LANE_UP
SOFT_ERR => aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i.SOFT_ERR
HARD_ERR => aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i.HARD_ERR
CHANNEL_BOND_LOAD => aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.CHANNEL_BOND_LOAD
GOT_A[1] => aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.GOT_A[1]
GOT_A[0] => aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.GOT_A[0]
GOT_V => aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.GOT_V
GEN_A <= aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.GEN_A
GEN_K[1] <= aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.GEN_K[1]
GEN_K[0] <= aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.GEN_K[0]
GEN_R[1] <= aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.GEN_R[1]
GEN_R[0] <= aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.GEN_R[0]
GEN_V[1] <= aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.GEN_V[1]
GEN_V[0] <= aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.GEN_V[0]
RESET_LANES <= aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.RESET_LANES
USER_CLK => aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i.USER_CLK
RESET => aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.RESET
RESET => aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i.RESET
POWER_DOWN => aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i.POWER_DOWN
CHANNEL_UP <= aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.CHANNEL_UP
START_RX <= aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i.START_RX
CHANNEL_SOFT_ERR <= aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i.CHANNEL_SOFT_ERR
CHANNEL_HARD_ERR <= aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i.CHANNEL_HARD_ERR


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i
CH_BOND_DONE => ~NO_FANOUT~
EN_CHAN_SYNC <= <GND>
CHANNEL_BOND_LOAD => ~NO_FANOUT~
GOT_A[1] => ~NO_FANOUT~
GOT_A[0] => ~NO_FANOUT~
GOT_V => all_lanes_v_r.DATAIN
RESET_LANES <= FD:reset_lanes_flop_i.Q
USER_CLK => FD:reset_lanes_flop_i.C
USER_CLK => txver_count_r[7].CLK
USER_CLK => txver_count_r[6].CLK
USER_CLK => txver_count_r[5].CLK
USER_CLK => txver_count_r[4].CLK
USER_CLK => txver_count_r[3].CLK
USER_CLK => txver_count_r[2].CLK
USER_CLK => txver_count_r[1].CLK
USER_CLK => txver_count_r[0].CLK
USER_CLK => rxver_count_r[2].CLK
USER_CLK => rxver_count_r[1].CLK
USER_CLK => rxver_count_r[0].CLK
USER_CLK => bad_v_r.CLK
USER_CLK => v_count_r[31].CLK
USER_CLK => v_count_r[30].CLK
USER_CLK => v_count_r[29].CLK
USER_CLK => v_count_r[28].CLK
USER_CLK => v_count_r[27].CLK
USER_CLK => v_count_r[26].CLK
USER_CLK => v_count_r[25].CLK
USER_CLK => v_count_r[24].CLK
USER_CLK => v_count_r[23].CLK
USER_CLK => v_count_r[22].CLK
USER_CLK => v_count_r[21].CLK
USER_CLK => v_count_r[20].CLK
USER_CLK => v_count_r[19].CLK
USER_CLK => v_count_r[18].CLK
USER_CLK => v_count_r[17].CLK
USER_CLK => v_count_r[16].CLK
USER_CLK => v_count_r[15].CLK
USER_CLK => v_count_r[14].CLK
USER_CLK => v_count_r[13].CLK
USER_CLK => v_count_r[12].CLK
USER_CLK => v_count_r[11].CLK
USER_CLK => v_count_r[10].CLK
USER_CLK => v_count_r[9].CLK
USER_CLK => v_count_r[8].CLK
USER_CLK => v_count_r[7].CLK
USER_CLK => v_count_r[6].CLK
USER_CLK => v_count_r[5].CLK
USER_CLK => v_count_r[4].CLK
USER_CLK => v_count_r[3].CLK
USER_CLK => v_count_r[2].CLK
USER_CLK => v_count_r[1].CLK
USER_CLK => v_count_r[0].CLK
USER_CLK => got_first_v_r.CLK
USER_CLK => all_lanes_v_r.CLK
USER_CLK => verify_watchdog_r[15].CLK
USER_CLK => verify_watchdog_r[14].CLK
USER_CLK => verify_watchdog_r[13].CLK
USER_CLK => verify_watchdog_r[12].CLK
USER_CLK => verify_watchdog_r[11].CLK
USER_CLK => verify_watchdog_r[10].CLK
USER_CLK => verify_watchdog_r[9].CLK
USER_CLK => verify_watchdog_r[8].CLK
USER_CLK => verify_watchdog_r[7].CLK
USER_CLK => verify_watchdog_r[6].CLK
USER_CLK => verify_watchdog_r[5].CLK
USER_CLK => verify_watchdog_r[4].CLK
USER_CLK => verify_watchdog_r[3].CLK
USER_CLK => verify_watchdog_r[2].CLK
USER_CLK => verify_watchdog_r[1].CLK
USER_CLK => verify_watchdog_r[0].CLK
USER_CLK => free_count_r[7].CLK
USER_CLK => free_count_r[6].CLK
USER_CLK => free_count_r[5].CLK
USER_CLK => free_count_r[4].CLK
USER_CLK => free_count_r[3].CLK
USER_CLK => free_count_r[2].CLK
USER_CLK => free_count_r[1].CLK
USER_CLK => free_count_r[0].CLK
USER_CLK => START_RX_Buffer.CLK
USER_CLK => CHANNEL_UP_Buffer.CLK
USER_CLK => ready_r.CLK
USER_CLK => verify_r.CLK
USER_CLK => wait_for_lane_up_r.CLK
RESET => process_0.IN0
RESET => START_RX_Buffer.OUTPUTSELECT
RESET => reset_lanes_c.IN1
CHANNEL_UP <= CHANNEL_UP_Buffer.DB_MAX_OUTPUT_PORT_TYPE
START_RX <= START_RX_Buffer.DB_MAX_OUTPUT_PORT_TYPE
DID_VER => process_10.IN1
GEN_VER <= verify_r.DB_MAX_OUTPUT_PORT_TYPE
RESET_CHANNEL => process_0.IN1
RESET_CHANNEL => reset_lanes_c.IN1


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_INIT_SM:channel_init_sm_i|FD:reset_lanes_flop_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q~reg0.DATAIN


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i
GEN_VER => gen_ver_edge_c.IN1
GEN_VER => recycle_gen_ver_c.IN1
GEN_VER => gen_v_flop_c[0].IN1
GEN_VER => gen_v_flop_c[1].IN1
GEN_VER => prev_cycle_gen_ver_r.DATAIN
DID_VER <= gen_ver_word_2_r.DB_MAX_OUTPUT_PORT_TYPE
GEN_A <= FD:gen_a_flop_0_i.Q
GEN_K[1] <= FD:gen_k_flop_1_i.Q
GEN_K[0] <= FD:gen_k_flop_0_i.Q
GEN_R[1] <= FD:gen_r_flop_1_i.Q
GEN_R[0] <= FD:gen_r_flop_0_i.Q
GEN_V[1] <= FD:gen_v_flop_1_i.Q
GEN_V[0] <= FD:gen_v_flop_0_i.Q
RESET => downcounter_r.OUTPUTSELECT
RESET => downcounter_r.OUTPUTSELECT
RESET => downcounter_r.OUTPUTSELECT
RESET => downcounter_r.OUTPUTSELECT
RESET => FDR:lfsr_last_flop_i.R
RESET => FDR:lfsr_taps_i.R
USER_CLK => FDR:lfsr_last_flop_i.C
USER_CLK => gen_ver_word_2_r.CLK
USER_CLK => prev_cycle_gen_ver_r.CLK
USER_CLK => downcounter_r[3].CLK
USER_CLK => downcounter_r[2].CLK
USER_CLK => downcounter_r[1].CLK
USER_CLK => downcounter_r[0].CLK
USER_CLK => lfsr_shift_register_r[3].CLK
USER_CLK => lfsr_shift_register_r[2].CLK
USER_CLK => lfsr_shift_register_r[1].CLK
USER_CLK => lfsr_shift_register_r[0].CLK
USER_CLK => FDR:lfsr_taps_i.C
USER_CLK => SRL16:ver_counter_0_i.CLK
USER_CLK => SRL16:ver_counter_1_i.CLK
USER_CLK => FD:gen_v_flop_0_i.C
USER_CLK => FD:gen_v_flop_1_i.C
USER_CLK => FD:gen_a_flop_0_i.C
USER_CLK => FD:gen_k_flop_0_i.C
USER_CLK => FD:gen_k_flop_1_i.C
USER_CLK => FD:gen_r_flop_0_i.C
USER_CLK => FD:gen_r_flop_1_i.C


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_last_flop_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q.DATAA
R => Q.OUTPUTSELECT


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FDR:lfsr_taps_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q.DATAA
R => Q.OUTPUTSELECT


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i
A0 => MUX16to1:MUX_16to1.sel[0]
A1 => MUX16to1:MUX_16to1.sel[1]
A2 => MUX16to1:MUX_16to1.sel[2]
A3 => MUX16to1:MUX_16to1.sel[3]
CLK => LPMSHIFTREG16:lpm_shiftreg16.clock
D => LPMSHIFTREG16:lpm_shiftreg16.shiftin
Q <= MUX16to1:MUX_16to1.result


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16
clock => lpm_shiftreg:lpm_shiftreg_component.clock
shiftin => lpm_shiftreg:lpm_shiftreg_component.shiftin
q[0] <= lpm_shiftreg:lpm_shiftreg_component.q[0]
q[1] <= lpm_shiftreg:lpm_shiftreg_component.q[1]
q[2] <= lpm_shiftreg:lpm_shiftreg_component.q[2]
q[3] <= lpm_shiftreg:lpm_shiftreg_component.q[3]
q[4] <= lpm_shiftreg:lpm_shiftreg_component.q[4]
q[5] <= lpm_shiftreg:lpm_shiftreg_component.q[5]
q[6] <= lpm_shiftreg:lpm_shiftreg_component.q[6]
q[7] <= lpm_shiftreg:lpm_shiftreg_component.q[7]
q[8] <= lpm_shiftreg:lpm_shiftreg_component.q[8]
q[9] <= lpm_shiftreg:lpm_shiftreg_component.q[9]
q[10] <= lpm_shiftreg:lpm_shiftreg_component.q[10]
q[11] <= lpm_shiftreg:lpm_shiftreg_component.q[11]
q[12] <= lpm_shiftreg:lpm_shiftreg_component.q[12]
q[13] <= lpm_shiftreg:lpm_shiftreg_component.q[13]
q[14] <= lpm_shiftreg:lpm_shiftreg_component.q[14]
q[15] <= lpm_shiftreg:lpm_shiftreg_component.q[15]


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component
data[0] => _.IN1
data[1] => _.IN1
data[2] => _.IN1
data[3] => _.IN1
data[4] => _.IN1
data[5] => _.IN1
data[6] => _.IN1
data[7] => _.IN1
data[8] => _.IN1
data[9] => _.IN1
data[10] => _.IN1
data[11] => _.IN1
data[12] => _.IN1
data[13] => _.IN1
data[14] => _.IN1
data[15] => _.IN1
clock => dffs[15].CLK
clock => dffs[14].CLK
clock => dffs[13].CLK
clock => dffs[12].CLK
clock => dffs[11].CLK
clock => dffs[10].CLK
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[15].ENA
enable => dffs[14].ENA
enable => dffs[13].ENA
enable => dffs[12].ENA
enable => dffs[11].ENA
enable => dffs[10].ENA
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
shiftin => _.IN1
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
sclr => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffs[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffs[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffs[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= dffs[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= dffs[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= dffs[15].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout.DB_MAX_OUTPUT_PORT_TYPE


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1
data0 => LPM_MUX:lpm_mux_component.DATA[0][0]
data1 => LPM_MUX:lpm_mux_component.DATA[1][0]
data10 => LPM_MUX:lpm_mux_component.DATA[10][0]
data11 => LPM_MUX:lpm_mux_component.DATA[11][0]
data12 => LPM_MUX:lpm_mux_component.DATA[12][0]
data13 => LPM_MUX:lpm_mux_component.DATA[13][0]
data14 => LPM_MUX:lpm_mux_component.DATA[14][0]
data15 => LPM_MUX:lpm_mux_component.DATA[15][0]
data2 => LPM_MUX:lpm_mux_component.DATA[2][0]
data3 => LPM_MUX:lpm_mux_component.DATA[3][0]
data4 => LPM_MUX:lpm_mux_component.DATA[4][0]
data5 => LPM_MUX:lpm_mux_component.DATA[5][0]
data6 => LPM_MUX:lpm_mux_component.DATA[6][0]
data7 => LPM_MUX:lpm_mux_component.DATA[7][0]
data8 => LPM_MUX:lpm_mux_component.DATA[8][0]
data9 => LPM_MUX:lpm_mux_component.DATA[9][0]
sel[0] => LPM_MUX:lpm_mux_component.SEL[0]
sel[1] => LPM_MUX:lpm_mux_component.SEL[1]
sel[2] => LPM_MUX:lpm_mux_component.SEL[2]
sel[3] => LPM_MUX:lpm_mux_component.SEL[3]
result <= LPM_MUX:lpm_mux_component.RESULT[0]


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component
data[0][0] => mux_76e:auto_generated.data[0]
data[1][0] => mux_76e:auto_generated.data[1]
data[2][0] => mux_76e:auto_generated.data[2]
data[3][0] => mux_76e:auto_generated.data[3]
data[4][0] => mux_76e:auto_generated.data[4]
data[5][0] => mux_76e:auto_generated.data[5]
data[6][0] => mux_76e:auto_generated.data[6]
data[7][0] => mux_76e:auto_generated.data[7]
data[8][0] => mux_76e:auto_generated.data[8]
data[9][0] => mux_76e:auto_generated.data[9]
data[10][0] => mux_76e:auto_generated.data[10]
data[11][0] => mux_76e:auto_generated.data[11]
data[12][0] => mux_76e:auto_generated.data[12]
data[13][0] => mux_76e:auto_generated.data[13]
data[14][0] => mux_76e:auto_generated.data[14]
data[15][0] => mux_76e:auto_generated.data[15]
sel[0] => mux_76e:auto_generated.sel[0]
sel[1] => mux_76e:auto_generated.sel[1]
sel[2] => mux_76e:auto_generated.sel[2]
sel[3] => mux_76e:auto_generated.sel[3]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_76e:auto_generated.result[0]


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_0_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component|mux_76e:auto_generated
data[0] => l1_w0_n0_mux_dataout.IN1
data[1] => l1_w0_n0_mux_dataout.IN1
data[2] => l1_w0_n1_mux_dataout.IN1
data[3] => l1_w0_n1_mux_dataout.IN1
data[4] => l1_w0_n2_mux_dataout.IN1
data[5] => l1_w0_n2_mux_dataout.IN1
data[6] => l1_w0_n3_mux_dataout.IN1
data[7] => l1_w0_n3_mux_dataout.IN1
data[8] => l1_w0_n4_mux_dataout.IN1
data[9] => l1_w0_n4_mux_dataout.IN1
data[10] => l1_w0_n5_mux_dataout.IN1
data[11] => l1_w0_n5_mux_dataout.IN1
data[12] => l1_w0_n6_mux_dataout.IN1
data[13] => l1_w0_n6_mux_dataout.IN1
data[14] => l1_w0_n7_mux_dataout.IN1
data[15] => l1_w0_n7_mux_dataout.IN1
result[0] <= l4_w0_n0_mux_dataout.DB_MAX_OUTPUT_PORT_TYPE
sel[0] => l1_w0_n0_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n1_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n2_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n3_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n4_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n5_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n6_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n7_mux_dataout.IN0
sel[0] => _.IN0
sel[1] => l2_w0_n0_mux_dataout.IN0
sel[1] => _.IN0
sel[1] => l2_w0_n1_mux_dataout.IN0
sel[1] => _.IN0
sel[1] => l2_w0_n2_mux_dataout.IN0
sel[1] => _.IN0
sel[1] => l2_w0_n3_mux_dataout.IN0
sel[1] => _.IN0
sel[2] => l3_w0_n0_mux_dataout.IN0
sel[2] => _.IN0
sel[2] => l3_w0_n1_mux_dataout.IN0
sel[2] => _.IN0
sel[3] => l4_w0_n0_mux_dataout.IN0
sel[3] => _.IN0


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i
A0 => MUX16to1:MUX_16to1.sel[0]
A1 => MUX16to1:MUX_16to1.sel[1]
A2 => MUX16to1:MUX_16to1.sel[2]
A3 => MUX16to1:MUX_16to1.sel[3]
CLK => LPMSHIFTREG16:lpm_shiftreg16.clock
D => LPMSHIFTREG16:lpm_shiftreg16.shiftin
Q <= MUX16to1:MUX_16to1.result


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16
clock => lpm_shiftreg:lpm_shiftreg_component.clock
shiftin => lpm_shiftreg:lpm_shiftreg_component.shiftin
q[0] <= lpm_shiftreg:lpm_shiftreg_component.q[0]
q[1] <= lpm_shiftreg:lpm_shiftreg_component.q[1]
q[2] <= lpm_shiftreg:lpm_shiftreg_component.q[2]
q[3] <= lpm_shiftreg:lpm_shiftreg_component.q[3]
q[4] <= lpm_shiftreg:lpm_shiftreg_component.q[4]
q[5] <= lpm_shiftreg:lpm_shiftreg_component.q[5]
q[6] <= lpm_shiftreg:lpm_shiftreg_component.q[6]
q[7] <= lpm_shiftreg:lpm_shiftreg_component.q[7]
q[8] <= lpm_shiftreg:lpm_shiftreg_component.q[8]
q[9] <= lpm_shiftreg:lpm_shiftreg_component.q[9]
q[10] <= lpm_shiftreg:lpm_shiftreg_component.q[10]
q[11] <= lpm_shiftreg:lpm_shiftreg_component.q[11]
q[12] <= lpm_shiftreg:lpm_shiftreg_component.q[12]
q[13] <= lpm_shiftreg:lpm_shiftreg_component.q[13]
q[14] <= lpm_shiftreg:lpm_shiftreg_component.q[14]
q[15] <= lpm_shiftreg:lpm_shiftreg_component.q[15]


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|LPMSHIFTREG16:lpm_shiftreg16|lpm_shiftreg:lpm_shiftreg_component
data[0] => _.IN1
data[1] => _.IN1
data[2] => _.IN1
data[3] => _.IN1
data[4] => _.IN1
data[5] => _.IN1
data[6] => _.IN1
data[7] => _.IN1
data[8] => _.IN1
data[9] => _.IN1
data[10] => _.IN1
data[11] => _.IN1
data[12] => _.IN1
data[13] => _.IN1
data[14] => _.IN1
data[15] => _.IN1
clock => dffs[15].CLK
clock => dffs[14].CLK
clock => dffs[13].CLK
clock => dffs[12].CLK
clock => dffs[11].CLK
clock => dffs[10].CLK
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[15].ENA
enable => dffs[14].ENA
enable => dffs[13].ENA
enable => dffs[12].ENA
enable => dffs[11].ENA
enable => dffs[10].ENA
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
shiftin => _.IN1
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
load => _.IN0
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
sclr => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
sset => _.IN0
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffs[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffs[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffs[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= dffs[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= dffs[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= dffs[15].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout.DB_MAX_OUTPUT_PORT_TYPE


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1
data0 => LPM_MUX:lpm_mux_component.DATA[0][0]
data1 => LPM_MUX:lpm_mux_component.DATA[1][0]
data10 => LPM_MUX:lpm_mux_component.DATA[10][0]
data11 => LPM_MUX:lpm_mux_component.DATA[11][0]
data12 => LPM_MUX:lpm_mux_component.DATA[12][0]
data13 => LPM_MUX:lpm_mux_component.DATA[13][0]
data14 => LPM_MUX:lpm_mux_component.DATA[14][0]
data15 => LPM_MUX:lpm_mux_component.DATA[15][0]
data2 => LPM_MUX:lpm_mux_component.DATA[2][0]
data3 => LPM_MUX:lpm_mux_component.DATA[3][0]
data4 => LPM_MUX:lpm_mux_component.DATA[4][0]
data5 => LPM_MUX:lpm_mux_component.DATA[5][0]
data6 => LPM_MUX:lpm_mux_component.DATA[6][0]
data7 => LPM_MUX:lpm_mux_component.DATA[7][0]
data8 => LPM_MUX:lpm_mux_component.DATA[8][0]
data9 => LPM_MUX:lpm_mux_component.DATA[9][0]
sel[0] => LPM_MUX:lpm_mux_component.SEL[0]
sel[1] => LPM_MUX:lpm_mux_component.SEL[1]
sel[2] => LPM_MUX:lpm_mux_component.SEL[2]
sel[3] => LPM_MUX:lpm_mux_component.SEL[3]
result <= LPM_MUX:lpm_mux_component.RESULT[0]


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component
data[0][0] => mux_76e:auto_generated.data[0]
data[1][0] => mux_76e:auto_generated.data[1]
data[2][0] => mux_76e:auto_generated.data[2]
data[3][0] => mux_76e:auto_generated.data[3]
data[4][0] => mux_76e:auto_generated.data[4]
data[5][0] => mux_76e:auto_generated.data[5]
data[6][0] => mux_76e:auto_generated.data[6]
data[7][0] => mux_76e:auto_generated.data[7]
data[8][0] => mux_76e:auto_generated.data[8]
data[9][0] => mux_76e:auto_generated.data[9]
data[10][0] => mux_76e:auto_generated.data[10]
data[11][0] => mux_76e:auto_generated.data[11]
data[12][0] => mux_76e:auto_generated.data[12]
data[13][0] => mux_76e:auto_generated.data[13]
data[14][0] => mux_76e:auto_generated.data[14]
data[15][0] => mux_76e:auto_generated.data[15]
sel[0] => mux_76e:auto_generated.sel[0]
sel[1] => mux_76e:auto_generated.sel[1]
sel[2] => mux_76e:auto_generated.sel[2]
sel[3] => mux_76e:auto_generated.sel[3]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_76e:auto_generated.result[0]


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|SRL16:ver_counter_1_i|MUX16to1:MUX_16to1|LPM_MUX:lpm_mux_component|mux_76e:auto_generated
data[0] => l1_w0_n0_mux_dataout.IN1
data[1] => l1_w0_n0_mux_dataout.IN1
data[2] => l1_w0_n1_mux_dataout.IN1
data[3] => l1_w0_n1_mux_dataout.IN1
data[4] => l1_w0_n2_mux_dataout.IN1
data[5] => l1_w0_n2_mux_dataout.IN1
data[6] => l1_w0_n3_mux_dataout.IN1
data[7] => l1_w0_n3_mux_dataout.IN1
data[8] => l1_w0_n4_mux_dataout.IN1
data[9] => l1_w0_n4_mux_dataout.IN1
data[10] => l1_w0_n5_mux_dataout.IN1
data[11] => l1_w0_n5_mux_dataout.IN1
data[12] => l1_w0_n6_mux_dataout.IN1
data[13] => l1_w0_n6_mux_dataout.IN1
data[14] => l1_w0_n7_mux_dataout.IN1
data[15] => l1_w0_n7_mux_dataout.IN1
result[0] <= l4_w0_n0_mux_dataout.DB_MAX_OUTPUT_PORT_TYPE
sel[0] => l1_w0_n0_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n1_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n2_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n3_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n4_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n5_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n6_mux_dataout.IN0
sel[0] => _.IN0
sel[0] => l1_w0_n7_mux_dataout.IN0
sel[0] => _.IN0
sel[1] => l2_w0_n0_mux_dataout.IN0
sel[1] => _.IN0
sel[1] => l2_w0_n1_mux_dataout.IN0
sel[1] => _.IN0
sel[1] => l2_w0_n2_mux_dataout.IN0
sel[1] => _.IN0
sel[1] => l2_w0_n3_mux_dataout.IN0
sel[1] => _.IN0
sel[2] => l3_w0_n0_mux_dataout.IN0
sel[2] => _.IN0
sel[2] => l3_w0_n1_mux_dataout.IN0
sel[2] => _.IN0
sel[3] => l4_w0_n0_mux_dataout.IN0
sel[3] => _.IN0


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_0_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q~reg0.DATAIN


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_v_flop_1_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q~reg0.DATAIN


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_a_flop_0_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q~reg0.DATAIN


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_0_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q~reg0.DATAIN


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_k_flop_1_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q~reg0.DATAIN


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_0_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q~reg0.DATAIN


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_IDLE_AND_VER_GEN:idle_and_ver_gen_i|FD:gen_r_flop_1_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q~reg0.DATAIN


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_GLOBAL_LOGIC:global_logic_i|aurora_8b10b_v5_2_CHANNEL_ERR_DETECT:channel_err_detect_i
SOFT_ERR => soft_err_r.DATAIN
HARD_ERR => hard_err_r.DATAIN
LANE_UP => lane_up_r.DATAIN
USER_CLK => RESET_CHANNEL_Buffer.CLK
USER_CLK => lane_up_r.CLK
USER_CLK => CHANNEL_HARD_ERR_Buffer.CLK
USER_CLK => CHANNEL_SOFT_ERR_Buffer.CLK
USER_CLK => hard_err_r.CLK
USER_CLK => soft_err_r.CLK
POWER_DOWN => RESET_CHANNEL_Buffer.IN1
CHANNEL_SOFT_ERR <= CHANNEL_SOFT_ERR_Buffer.DB_MAX_OUTPUT_PORT_TYPE
CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RESET_CHANNEL <= RESET_CHANNEL_Buffer.DB_MAX_OUTPUT_PORT_TYPE


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i
TX_D[15] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[15]
TX_D[14] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[14]
TX_D[13] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[13]
TX_D[12] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[12]
TX_D[11] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[11]
TX_D[10] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[10]
TX_D[9] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[9]
TX_D[8] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[8]
TX_D[7] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[7]
TX_D[6] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[6]
TX_D[5] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[5]
TX_D[4] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[4]
TX_D[3] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[3]
TX_D[2] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[2]
TX_D[1] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[1]
TX_D[0] => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_D[0]
TX_REM => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_REM
TX_REM => aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.TX_REM
TX_SRC_RDY_N => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_SRC_RDY_N
TX_SRC_RDY_N => aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.TX_SRC_RDY_N
TX_SOF_N => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_SOF_N
TX_SOF_N => aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.TX_SOF_N
TX_EOF_N => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_EOF_N
TX_EOF_N => aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.TX_EOF_N
TX_DST_RDY_N <= aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.TX_DST_RDY_N
WARN_CC => aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.WARN_CC
DO_CC => aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.DO_CC
CHANNEL_UP => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.CHANNEL_UP
CHANNEL_UP => aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.CHANNEL_UP
GEN_SCP <= aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.GEN_SCP
GEN_ECP <= aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.GEN_ECP
TX_PE_DATA_V <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA_V
GEN_PAD <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.GEN_PAD
TX_PE_DATA[15] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[15]
TX_PE_DATA[14] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[14]
TX_PE_DATA[13] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[13]
TX_PE_DATA[12] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[12]
TX_PE_DATA[11] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[11]
TX_PE_DATA[10] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[10]
TX_PE_DATA[9] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[9]
TX_PE_DATA[8] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[8]
TX_PE_DATA[7] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[7]
TX_PE_DATA[6] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[6]
TX_PE_DATA[5] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[5]
TX_PE_DATA[4] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[4]
TX_PE_DATA[3] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[3]
TX_PE_DATA[2] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[2]
TX_PE_DATA[1] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[1]
TX_PE_DATA[0] <= aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.TX_PE_DATA[0]
GEN_CC <= aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.GEN_CC
USER_CLK => aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i.USER_CLK
USER_CLK => aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i.USER_CLK


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_DATAPATH:tx_ll_datapath_i
TX_D[15] => storage_r[15].DATAIN
TX_D[14] => storage_r[14].DATAIN
TX_D[13] => storage_r[13].DATAIN
TX_D[12] => storage_r[12].DATAIN
TX_D[11] => storage_r[11].DATAIN
TX_D[10] => storage_r[10].DATAIN
TX_D[9] => storage_r[9].DATAIN
TX_D[8] => storage_r[8].DATAIN
TX_D[7] => storage_r[7].DATAIN
TX_D[6] => storage_r[6].DATAIN
TX_D[5] => storage_r[5].DATAIN
TX_D[4] => storage_r[4].DATAIN
TX_D[3] => storage_r[3].DATAIN
TX_D[2] => storage_r[2].DATAIN
TX_D[1] => storage_r[1].DATAIN
TX_D[0] => storage_r[0].DATAIN
TX_REM => gen_pad_c.DATAA
TX_SRC_RDY_N => ll_valid_c.IN0
TX_SOF_N => process_0.IN0
TX_SOF_N => in_frame_c.IN1
TX_EOF_N => process_0.IN1
TX_EOF_N => gen_pad_c.OUTPUTSELECT
TX_EOF_N => in_frame_r.OUTPUTSELECT
TX_PE_DATA_V <= TX_PE_DATA_V_Buffer.DB_MAX_OUTPUT_PORT_TYPE
GEN_PAD <= GEN_PAD_Buffer.DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[15] <= TX_PE_DATA_Buffer[15].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[14] <= TX_PE_DATA_Buffer[14].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[13] <= TX_PE_DATA_Buffer[13].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[12] <= TX_PE_DATA_Buffer[12].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[11] <= TX_PE_DATA_Buffer[11].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[10] <= TX_PE_DATA_Buffer[10].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[9] <= TX_PE_DATA_Buffer[9].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[8] <= TX_PE_DATA_Buffer[8].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[7] <= TX_PE_DATA_Buffer[7].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[6] <= TX_PE_DATA_Buffer[6].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[5] <= TX_PE_DATA_Buffer[5].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[4] <= TX_PE_DATA_Buffer[4].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[3] <= TX_PE_DATA_Buffer[3].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[2] <= TX_PE_DATA_Buffer[2].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[1] <= TX_PE_DATA_Buffer[1].DB_MAX_OUTPUT_PORT_TYPE
TX_PE_DATA[0] <= TX_PE_DATA_Buffer[0].DB_MAX_OUTPUT_PORT_TYPE
HALT_C => TX_PE_DATA_V_Buffer.IN1
HALT_C => GEN_PAD_Buffer.IN1
HALT_C => storage_r[15].ENA
HALT_C => tx_pe_data_r[15].ENA
HALT_C => storage_v_r.ENA
HALT_C => tx_pe_data_v_r.ENA
HALT_C => storage_pad_r.ENA
HALT_C => gen_pad_r.ENA
HALT_C => tx_pe_data_r[14].ENA
HALT_C => tx_pe_data_r[13].ENA
HALT_C => tx_pe_data_r[12].ENA
HALT_C => tx_pe_data_r[11].ENA
HALT_C => tx_pe_data_r[10].ENA
HALT_C => tx_pe_data_r[9].ENA
HALT_C => tx_pe_data_r[8].ENA
HALT_C => tx_pe_data_r[7].ENA
HALT_C => tx_pe_data_r[6].ENA
HALT_C => tx_pe_data_r[5].ENA
HALT_C => tx_pe_data_r[4].ENA
HALT_C => tx_pe_data_r[3].ENA
HALT_C => tx_pe_data_r[2].ENA
HALT_C => tx_pe_data_r[1].ENA
HALT_C => tx_pe_data_r[0].ENA
HALT_C => storage_r[14].ENA
HALT_C => storage_r[13].ENA
HALT_C => storage_r[12].ENA
HALT_C => storage_r[11].ENA
HALT_C => storage_r[10].ENA
HALT_C => storage_r[9].ENA
HALT_C => storage_r[8].ENA
HALT_C => storage_r[7].ENA
HALT_C => storage_r[6].ENA
HALT_C => storage_r[5].ENA
HALT_C => storage_r[4].ENA
HALT_C => storage_r[3].ENA
HALT_C => storage_r[2].ENA
HALT_C => storage_r[1].ENA
HALT_C => storage_r[0].ENA
TX_DST_RDY_N => ll_valid_c.IN1
CHANNEL_UP => in_frame_r.OUTPUTSELECT
USER_CLK => GEN_PAD_Buffer.CLK
USER_CLK => TX_PE_DATA_V_Buffer.CLK
USER_CLK => TX_PE_DATA_Buffer[15].CLK
USER_CLK => TX_PE_DATA_Buffer[14].CLK
USER_CLK => TX_PE_DATA_Buffer[13].CLK
USER_CLK => TX_PE_DATA_Buffer[12].CLK
USER_CLK => TX_PE_DATA_Buffer[11].CLK
USER_CLK => TX_PE_DATA_Buffer[10].CLK
USER_CLK => TX_PE_DATA_Buffer[9].CLK
USER_CLK => TX_PE_DATA_Buffer[8].CLK
USER_CLK => TX_PE_DATA_Buffer[7].CLK
USER_CLK => TX_PE_DATA_Buffer[6].CLK
USER_CLK => TX_PE_DATA_Buffer[5].CLK
USER_CLK => TX_PE_DATA_Buffer[4].CLK
USER_CLK => TX_PE_DATA_Buffer[3].CLK
USER_CLK => TX_PE_DATA_Buffer[2].CLK
USER_CLK => TX_PE_DATA_Buffer[1].CLK
USER_CLK => TX_PE_DATA_Buffer[0].CLK
USER_CLK => gen_pad_r.CLK
USER_CLK => storage_pad_r.CLK
USER_CLK => tx_pe_data_v_r.CLK
USER_CLK => storage_v_r.CLK
USER_CLK => tx_pe_data_r[15].CLK
USER_CLK => tx_pe_data_r[14].CLK
USER_CLK => tx_pe_data_r[13].CLK
USER_CLK => tx_pe_data_r[12].CLK
USER_CLK => tx_pe_data_r[11].CLK
USER_CLK => tx_pe_data_r[10].CLK
USER_CLK => tx_pe_data_r[9].CLK
USER_CLK => tx_pe_data_r[8].CLK
USER_CLK => tx_pe_data_r[7].CLK
USER_CLK => tx_pe_data_r[6].CLK
USER_CLK => tx_pe_data_r[5].CLK
USER_CLK => tx_pe_data_r[4].CLK
USER_CLK => tx_pe_data_r[3].CLK
USER_CLK => tx_pe_data_r[2].CLK
USER_CLK => tx_pe_data_r[1].CLK
USER_CLK => tx_pe_data_r[0].CLK
USER_CLK => storage_r[15].CLK
USER_CLK => storage_r[14].CLK
USER_CLK => storage_r[13].CLK
USER_CLK => storage_r[12].CLK
USER_CLK => storage_r[11].CLK
USER_CLK => storage_r[10].CLK
USER_CLK => storage_r[9].CLK
USER_CLK => storage_r[8].CLK
USER_CLK => storage_r[7].CLK
USER_CLK => storage_r[6].CLK
USER_CLK => storage_r[5].CLK
USER_CLK => storage_r[4].CLK
USER_CLK => storage_r[3].CLK
USER_CLK => storage_r[2].CLK
USER_CLK => storage_r[1].CLK
USER_CLK => storage_r[0].CLK
USER_CLK => in_frame_r.CLK


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i
TX_SRC_RDY_N => do_sof_c.IN1
TX_SOF_N => do_sof_c.IN1
TX_EOF_N => do_eof_c.IN1
TX_REM => ~NO_FANOUT~
TX_DST_RDY_N <= TX_DST_RDY_N_Buffer.DB_MAX_OUTPUT_PORT_TYPE
WARN_CC => ~NO_FANOUT~
DO_CC => tx_dst_rdy_n_c.IN1
DO_CC => do_cc_r.DATAIN
CHANNEL_UP => GEN_SCP_Buffer.OUTPUTSELECT
CHANNEL_UP => GEN_ECP_Buffer.OUTPUTSELECT
CHANNEL_UP => TX_DST_RDY_N_Buffer.OUTPUTSELECT
CHANNEL_UP => FDR:gen_cc_flop_0_i.R
CHANNEL_UP => idle_r.OUTPUTSELECT
CHANNEL_UP => sof_r.OUTPUTSELECT
CHANNEL_UP => sof_data_eof_1_r.OUTPUTSELECT
CHANNEL_UP => sof_data_eof_2_r.OUTPUTSELECT
CHANNEL_UP => sof_data_eof_3_r.OUTPUTSELECT
CHANNEL_UP => data_r.OUTPUTSELECT
CHANNEL_UP => data_eof_1_r.OUTPUTSELECT
CHANNEL_UP => data_eof_2_r.OUTPUTSELECT
CHANNEL_UP => data_eof_3_r.OUTPUTSELECT
HALT_C <= do_cc_r.DB_MAX_OUTPUT_PORT_TYPE
GEN_SCP <= GEN_SCP_Buffer.DB_MAX_OUTPUT_PORT_TYPE
GEN_ECP <= GEN_ECP_Buffer.DB_MAX_OUTPUT_PORT_TYPE
GEN_CC <= FDR:gen_cc_flop_0_i.Q
USER_CLK => FDR:gen_cc_flop_0_i.C
USER_CLK => TX_DST_RDY_N_Buffer.CLK
USER_CLK => GEN_ECP_Buffer.CLK
USER_CLK => GEN_SCP_Buffer.CLK
USER_CLK => data_eof_3_r.CLK
USER_CLK => data_eof_2_r.CLK
USER_CLK => data_eof_1_r.CLK
USER_CLK => data_r.CLK
USER_CLK => sof_data_eof_3_r.CLK
USER_CLK => sof_data_eof_2_r.CLK
USER_CLK => sof_data_eof_1_r.CLK
USER_CLK => sof_r.CLK
USER_CLK => idle_r.CLK
USER_CLK => do_cc_r.CLK


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_TX_LL:tx_ll_i|aurora_8b10b_v5_2_TX_LL_CONTROL:tx_ll_control_i|FDR:gen_cc_flop_0_i
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => Q~reg0.CLK
D => Q.DATAA
R => Q.OUTPUTSELECT


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_RX_LL:rx_ll_i
RX_D[15] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[15]
RX_D[14] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[14]
RX_D[13] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[13]
RX_D[12] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[12]
RX_D[11] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[11]
RX_D[10] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[10]
RX_D[9] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[9]
RX_D[8] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[8]
RX_D[7] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[7]
RX_D[6] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[6]
RX_D[5] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[5]
RX_D[4] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[4]
RX_D[3] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[3]
RX_D[2] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[2]
RX_D[1] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[1]
RX_D[0] <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_D[0]
RX_REM <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_REM
RX_SRC_RDY_N <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_SRC_RDY_N
RX_SOF_N <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_SOF_N
RX_EOF_N <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RX_EOF_N
START_RX => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.RESET
RX_PAD => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_PAD
RX_PE_DATA[15] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[15]
RX_PE_DATA[14] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[14]
RX_PE_DATA[13] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[13]
RX_PE_DATA[12] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[12]
RX_PE_DATA[11] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[11]
RX_PE_DATA[10] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[10]
RX_PE_DATA[9] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[9]
RX_PE_DATA[8] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[8]
RX_PE_DATA[7] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[7]
RX_PE_DATA[6] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[6]
RX_PE_DATA[5] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[5]
RX_PE_DATA[4] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[4]
RX_PE_DATA[3] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[3]
RX_PE_DATA[2] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[2]
RX_PE_DATA[1] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[1]
RX_PE_DATA[0] => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA[0]
RX_PE_DATA_V => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_DATA_V
RX_SCP => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_SCP
RX_ECP => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.PDU_ECP
FRAME_ERR <= aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.FRAME_ERR
USER_CLK => aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i.USER_CLK


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2:aurora_module_i|aurora_8b10b_v5_2_RX_LL:rx_ll_i|aurora_8b10b_v5_2_RX_LL_PDU_DATAPATH:rx_ll_pdu_datapath_i
PDU_DATA[15] => storage_r[15].DATAIN
PDU_DATA[14] => storage_r[14].DATAIN
PDU_DATA[13] => storage_r[13].DATAIN
PDU_DATA[12] => storage_r[12].DATAIN
PDU_DATA[11] => storage_r[11].DATAIN
PDU_DATA[10] => storage_r[10].DATAIN
PDU_DATA[9] => storage_r[9].DATAIN
PDU_DATA[8] => storage_r[8].DATAIN
PDU_DATA[7] => storage_r[7].DATAIN
PDU_DATA[6] => storage_r[6].DATAIN
PDU_DATA[5] => storage_r[5].DATAIN
PDU_DATA[4] => storage_r[4].DATAIN
PDU_DATA[3] => storage_r[3].DATAIN
PDU_DATA[2] => storage_r[2].DATAIN
PDU_DATA[1] => storage_r[1].DATAIN
PDU_DATA[0] => storage_r[0].DATAIN
PDU_DATA_V => storage_ce_c.IN1
PDU_PAD => pad_in_storage_r.DATAIN
PDU_SCP => in_frame_r.OUTPUTSELECT
PDU_SCP => sof_in_storage_r.OUTPUTSELECT
PDU_SCP => FRAME_ERR_Buffer.IN1
PDU_ECP => src_rdy_n_c.IN1
PDU_ECP => in_frame_r.OUTPUTSELECT
PDU_ECP => FRAME_ERR_Buffer.IN1
PDU_ECP => FRAME_ERR_Buffer.IN1
PDU_ECP => RX_EOF_N_Buffer.DATAIN
RX_D[15] <= RX_D_Buffer[15].DB_MAX_OUTPUT_PORT_TYPE
RX_D[14] <= RX_D_Buffer[14].DB_MAX_OUTPUT_PORT_TYPE
RX_D[13] <= RX_D_Buffer[13].DB_MAX_OUTPUT_PORT_TYPE
RX_D[12] <= RX_D_Buffer[12].DB_MAX_OUTPUT_PORT_TYPE
RX_D[11] <= RX_D_Buffer[11].DB_MAX_OUTPUT_PORT_TYPE
RX_D[10] <= RX_D_Buffer[10].DB_MAX_OUTPUT_PORT_TYPE
RX_D[9] <= RX_D_Buffer[9].DB_MAX_OUTPUT_PORT_TYPE
RX_D[8] <= RX_D_Buffer[8].DB_MAX_OUTPUT_PORT_TYPE
RX_D[7] <= RX_D_Buffer[7].DB_MAX_OUTPUT_PORT_TYPE
RX_D[6] <= RX_D_Buffer[6].DB_MAX_OUTPUT_PORT_TYPE
RX_D[5] <= RX_D_Buffer[5].DB_MAX_OUTPUT_PORT_TYPE
RX_D[4] <= RX_D_Buffer[4].DB_MAX_OUTPUT_PORT_TYPE
RX_D[3] <= RX_D_Buffer[3].DB_MAX_OUTPUT_PORT_TYPE
RX_D[2] <= RX_D_Buffer[2].DB_MAX_OUTPUT_PORT_TYPE
RX_D[1] <= RX_D_Buffer[1].DB_MAX_OUTPUT_PORT_TYPE
RX_D[0] <= RX_D_Buffer[0].DB_MAX_OUTPUT_PORT_TYPE
RX_REM <= RX_REM_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_SOF_N <= RX_SOF_N_Buffer.DB_MAX_OUTPUT_PORT_TYPE
RX_EOF_N <= RX_EOF_N_Buffer.DB_MAX_OUTPUT_PORT_TYPE
FRAME_ERR <= FRAME_ERR_Buffer.DB_MAX_OUTPUT_PORT_TYPE
USER_CLK => FRAME_ERR_Buffer.CLK
USER_CLK => RX_REM_Buffer.CLK
USER_CLK => pad_in_storage_r.CLK
USER_CLK => RX_EOF_N_Buffer.CLK
USER_CLK => RX_SOF_N_Buffer.CLK
USER_CLK => sof_in_storage_r.CLK
USER_CLK => in_frame_r.CLK
USER_CLK => RX_SRC_RDY_N_Buffer.CLK
USER_CLK => RX_D_Buffer[15].CLK
USER_CLK => RX_D_Buffer[14].CLK
USER_CLK => RX_D_Buffer[13].CLK
USER_CLK => RX_D_Buffer[12].CLK
USER_CLK => RX_D_Buffer[11].CLK
USER_CLK => RX_D_Buffer[10].CLK
USER_CLK => RX_D_Buffer[9].CLK
USER_CLK => RX_D_Buffer[8].CLK
USER_CLK => RX_D_Buffer[7].CLK
USER_CLK => RX_D_Buffer[6].CLK
USER_CLK => RX_D_Buffer[5].CLK
USER_CLK => RX_D_Buffer[4].CLK
USER_CLK => RX_D_Buffer[3].CLK
USER_CLK => RX_D_Buffer[2].CLK
USER_CLK => RX_D_Buffer[1].CLK
USER_CLK => RX_D_Buffer[0].CLK
USER_CLK => storage_v_r.CLK
USER_CLK => storage_r[15].CLK
USER_CLK => storage_r[14].CLK
USER_CLK => storage_r[13].CLK
USER_CLK => storage_r[12].CLK
USER_CLK => storage_r[11].CLK
USER_CLK => storage_r[10].CLK
USER_CLK => storage_r[9].CLK
USER_CLK => storage_r[8].CLK
USER_CLK => storage_r[7].CLK
USER_CLK => storage_r[6].CLK
USER_CLK => storage_r[5].CLK
USER_CLK => storage_r[4].CLK
USER_CLK => storage_r[3].CLK
USER_CLK => storage_r[2].CLK
USER_CLK => storage_r[1].CLK
USER_CLK => storage_r[0].CLK
RESET => storage_v_r.OUTPUTSELECT
RESET => RX_SRC_RDY_N_Buffer.OUTPUTSELECT
RESET => in_frame_r.OUTPUTSELECT


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_STANDARD_CC_MODULE:standard_cc_module_i
WARN_CC <= WARN_CC~reg0.DB_MAX_OUTPUT_PORT_TYPE
DO_CC <= DO_CC~reg0.DB_MAX_OUTPUT_PORT_TYPE
PLL_NOT_LOCKED => ~NO_FANOUT~
USER_CLK => DO_CC~reg0.CLK
USER_CLK => cc_count_r[5].CLK
USER_CLK => cc_count_r[4].CLK
USER_CLK => cc_count_r[3].CLK
USER_CLK => cc_count_r[2].CLK
USER_CLK => cc_count_r[1].CLK
USER_CLK => cc_count_r[0].CLK
USER_CLK => reset_r.CLK
USER_CLK => WARN_CC~reg0.CLK
USER_CLK => prepare_count_r[9].CLK
USER_CLK => prepare_count_r[8].CLK
USER_CLK => prepare_count_r[7].CLK
USER_CLK => prepare_count_r[6].CLK
USER_CLK => prepare_count_r[5].CLK
USER_CLK => prepare_count_r[4].CLK
USER_CLK => prepare_count_r[3].CLK
USER_CLK => prepare_count_r[2].CLK
USER_CLK => prepare_count_r[1].CLK
USER_CLK => prepare_count_r[0].CLK
USER_CLK => count_24d_flop_r.CLK
USER_CLK => count_24d_srl_r[22].CLK
USER_CLK => count_24d_srl_r[21].CLK
USER_CLK => count_24d_srl_r[20].CLK
USER_CLK => count_24d_srl_r[19].CLK
USER_CLK => count_24d_srl_r[18].CLK
USER_CLK => count_24d_srl_r[17].CLK
USER_CLK => count_24d_srl_r[16].CLK
USER_CLK => count_24d_srl_r[15].CLK
USER_CLK => count_24d_srl_r[14].CLK
USER_CLK => count_24d_srl_r[13].CLK
USER_CLK => count_24d_srl_r[12].CLK
USER_CLK => count_24d_srl_r[11].CLK
USER_CLK => count_24d_srl_r[10].CLK
USER_CLK => count_24d_srl_r[9].CLK
USER_CLK => count_24d_srl_r[8].CLK
USER_CLK => count_24d_srl_r[7].CLK
USER_CLK => count_24d_srl_r[6].CLK
USER_CLK => count_24d_srl_r[5].CLK
USER_CLK => count_24d_srl_r[4].CLK
USER_CLK => count_24d_srl_r[3].CLK
USER_CLK => count_24d_srl_r[2].CLK
USER_CLK => count_24d_srl_r[1].CLK
USER_CLK => count_24d_srl_r[0].CLK
USER_CLK => count_16d_flop_r.CLK
USER_CLK => count_16d_srl_r[14].CLK
USER_CLK => count_16d_srl_r[13].CLK
USER_CLK => count_16d_srl_r[12].CLK
USER_CLK => count_16d_srl_r[11].CLK
USER_CLK => count_16d_srl_r[10].CLK
USER_CLK => count_16d_srl_r[9].CLK
USER_CLK => count_16d_srl_r[8].CLK
USER_CLK => count_16d_srl_r[7].CLK
USER_CLK => count_16d_srl_r[6].CLK
USER_CLK => count_16d_srl_r[5].CLK
USER_CLK => count_16d_srl_r[4].CLK
USER_CLK => count_16d_srl_r[3].CLK
USER_CLK => count_16d_srl_r[2].CLK
USER_CLK => count_16d_srl_r[1].CLK
USER_CLK => count_16d_srl_r[0].CLK
USER_CLK => count_13d_flop_r.CLK
USER_CLK => count_13d_srl_r[11].CLK
USER_CLK => count_13d_srl_r[10].CLK
USER_CLK => count_13d_srl_r[9].CLK
USER_CLK => count_13d_srl_r[8].CLK
USER_CLK => count_13d_srl_r[7].CLK
USER_CLK => count_13d_srl_r[6].CLK
USER_CLK => count_13d_srl_r[5].CLK
USER_CLK => count_13d_srl_r[4].CLK
USER_CLK => count_13d_srl_r[3].CLK
USER_CLK => count_13d_srl_r[2].CLK
USER_CLK => count_13d_srl_r[1].CLK
USER_CLK => count_13d_srl_r[0].CLK
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_srl_r.OUTPUTSELECT
RESET => count_13d_flop_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_srl_r.OUTPUTSELECT
RESET => count_16d_flop_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_srl_r.OUTPUTSELECT
RESET => count_24d_flop_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => prepare_count_r.OUTPUTSELECT
RESET => WARN_CC.OUTPUTSELECT
RESET => cc_count_r.OUTPUTSELECT
RESET => cc_count_r.OUTPUTSELECT
RESET => cc_count_r.OUTPUTSELECT
RESET => cc_count_r.OUTPUTSELECT
RESET => cc_count_r.OUTPUTSELECT
RESET => cc_count_r.OUTPUTSELECT
RESET => DO_CC.OUTPUTSELECT
RESET => reset_r.DATAIN
RESET => process_2.IN1
RESET => process_4.IN1
RESET => cc_count_r.IN1
RESET => start_cc_c.IN1


|aurora_8b10b_v5_2_example_design|aurora_8b10b_v5_2_RESET_LOGIC:reset_logic_i
RESET => reset_debounce_r[0].DATAIN
USER_CLK => reset_debounce_r4.CLK
USER_CLK => reset_debounce_r3.CLK
USER_CLK => reset_debounce_r2.CLK
USER_CLK => reset_debounce_r[3].CLK
USER_CLK => reset_debounce_r[2].CLK
USER_CLK => reset_debounce_r[1].CLK
USER_CLK => reset_debounce_r[0].CLK
INIT_CLK => debounce_gt_rst_r[3].CLK
INIT_CLK => debounce_gt_rst_r[2].CLK
INIT_CLK => debounce_gt_rst_r[1].CLK
INIT_CLK => debounce_gt_rst_r[0].CLK
GT_RESET_IN => debounce_gt_rst_r[0].DATAIN
TX_LOCK_IN => reset_debounce_r3.IN1
PLL_NOT_LOCKED => SYSTEM_RESET.IN1
SYSTEM_RESET <= SYSTEM_RESET.DB_MAX_OUTPUT_PORT_TYPE
GT_RESET_OUT <= gt_rst_r.DB_MAX_OUTPUT_PORT_TYPE


