Altium

Design Rule Verification Report

Date: 3/27/2019
Time: 6:12:28 PM
Elapsed Time: 00:00:00
Filename: C:\Users\Public\Documents\Altium\lmhamptestboard.PcbDoc
Warnings: 0
Rule Violations: 60

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=10mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 6
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=10mil) (Max=20mil) (Preferred=10mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=7mil) (All) 0
Hole Size Constraint (Min=13mil) (Max=265mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=6mil) (IsPad),(All) 23
Silk to Silk (Clearance=0mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (All) 31
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (Disabled)(All) 0
Total 60

Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net GND Between Pad 10^0-3(949.512mil,917.362mil) on L2 And Pad 10^0-3(949.512mil,917.362mil) on L1
Un-Routed Net Constraint: Net GND Between Track (920.512mil,789mil)(949.512mil,760mil) on L2 And Pad 10^0-3(949.512mil,917.362mil) on L2
Un-Routed Net Constraint: Net GND Between Pad 10^-1-3(222.638mil,1174.512mil) on L2 And Pad 10^-1-3(222.638mil,1174.512mil) on L1
Un-Routed Net Constraint: Net GND Between Pad 10^1-3(823.268mil,1174.512mil) on L1 And Pad 10^1-3(823.268mil,1174.512mil) on L2
Un-Routed Net Constraint: Net GND Between Pad 10^-2-3(105mil,904.724mil) on L2 And Pad 10^-2-3(105mil,904.724mil) on L1
Un-Routed Net Constraint: Net GND Between Pad RFIN-3(587.362mil,100.488mil) on L1 And Pad RFIN-3(587.362mil,100.488mil) on L2
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Silk To Solder Mask (Clearance=6mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^0-2(949.512mil,712.638mil) on L1 And Track (852.07mil,656.536mil)(1038.858mil,656.536mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.907mil < 6mil) Between Pad 10^0-2(949.512mil,712.638mil) on L1 And Track (852.07mil,656.536mil)(852.07mil,767.756mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.907mil]
Silk To Solder Mask Clearance Constraint: (5.907mil < 6mil) Between Pad 10^0-3(949.512mil,917.362mil) on L1 And Track (852.07mil,862.244mil)(852.07mil,973.464mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.907mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^0-3(949.512mil,917.362mil) on L1 And Track (852.07mil,973.464mil)(1038.858mil,973.464mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.907mil < 6mil) Between Pad 10^-1-2(427.362mil,1174.512mil) on L1 And Track (372.244mil,1077.07mil)(483.464mil,1077.07mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.907mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^-1-2(427.362mil,1174.512mil) on L1 And Track (483.464mil,1077.07mil)(483.464mil,1263.858mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (Collision < 6mil) Between Pad 10^1-2(618.544mil,1174.512mil) on L2 And Text "C2" (722mil,1032mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^1-2(618.544mil,1174.512mil) on L2 And Track (562.442mil,1077.07mil)(562.442mil,1263.858mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.907mil < 6mil) Between Pad 10^1-2(618.544mil,1174.512mil) on L2 And Track (562.442mil,1077.07mil)(673.662mil,1077.07mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [5.907mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^-1-3(222.638mil,1174.512mil) on L1 And Track (166.536mil,1077.07mil)(166.536mil,1263.858mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.907mil < 6mil) Between Pad 10^-1-3(222.638mil,1174.512mil) on L1 And Track (166.536mil,1077.07mil)(277.756mil,1077.07mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.907mil]
Silk To Solder Mask Clearance Constraint: (5.907mil < 6mil) Between Pad 10^1-3(823.268mil,1174.512mil) on L2 And Track (768.15mil,1077.07mil)(879.37mil,1077.07mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [5.907mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^1-3(823.268mil,1174.512mil) on L2 And Track (879.37mil,1077.07mil)(879.37mil,1263.858mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^-2-2(105mil,700mil) on L2 And Track (15.654mil,643.898mil)(202.44mil,643.898mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^-2-2(105mil,700mil) on L2 And Track (202.44mil,643.898mil)(202.44mil,755.118mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^-2-3(105mil,904.724mil) on L2 And Track (15.654mil,960.828mil)(202.44mil,960.826mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad 10^-2-3(105mil,904.724mil) on L2 And Track (202.44mil,849.606mil)(202.44mil,960.826mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (3.503mil < 6mil) Between Pad D3-1(800mil,984.686mil) on L1 And Text "D3" (794.094mil,1005mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.503mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad RFIN-2(382.638mil,100.488mil) on L1 And Track (326.536mil,11.142mil)(326.536mil,197.93mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (5.907mil < 6mil) Between Pad RFIN-2(382.638mil,100.488mil) on L1 And Track (326.536mil,197.93mil)(437.756mil,197.93mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.907mil]
Silk To Solder Mask Clearance Constraint: (5.907mil < 6mil) Between Pad RFIN-3(587.362mil,100.488mil) on L1 And Track (532.244mil,197.93mil)(643.464mil,197.93mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.907mil]
Silk To Solder Mask Clearance Constraint: (5.905mil < 6mil) Between Pad RFIN-3(587.362mil,100.488mil) on L1 And Track (643.464mil,11.142mil)(643.464mil,197.93mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.905mil]
Silk To Solder Mask Clearance Constraint: (Collision < 6mil) Between Pad U1-4(495mil,615mil) on L2 And Text "R7" (517mil,552mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
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Board Clearance Constraint (Gap=0mil) (All)
Board Outline Clearance(Outline Edge): (10mil < 15mil) Between Board Edge And Pad 10^0-1(1000mil,815mil) on L1
Board Outline Clearance(Outline Edge): (11.906mil < 15mil) Between Board Edge And Pad 10^0-2(949.512mil,712.638mil) on L1
Board Outline Clearance(Outline Edge): (11.906mil < 15mil) Between Board Edge And Pad 10^0-2(949.512mil,712.638mil) on L2
Board Outline Clearance(Outline Edge): (11.906mil < 15mil) Between Board Edge And Pad 10^0-3(949.512mil,917.362mil) on L1
Board Outline Clearance(Outline Edge): (11.906mil < 15mil) Between Board Edge And Pad 10^0-3(949.512mil,917.362mil) on L2
Board Outline Clearance(Outline Edge): (5mil < 15mil) Between Board Edge And Pad 10^-1-1(325mil,1225mil) on L1
Board Outline Clearance(Outline Edge): (5mil < 15mil) Between Board Edge And Pad 10^1-1(720.906mil,1225mil) on L2
Board Outline Clearance(Outline Edge): (6.906mil < 15mil) Between Board Edge And Pad 10^-1-2(427.362mil,1174.512mil) on L1
Board Outline Clearance(Outline Edge): (6.906mil < 15mil) Between Board Edge And Pad 10^-1-2(427.362mil,1174.512mil) on L2
Board Outline Clearance(Outline Edge): (6.906mil < 15mil) Between Board Edge And Pad 10^1-2(618.544mil,1174.512mil) on L1
Board Outline Clearance(Outline Edge): (6.906mil < 15mil) Between Board Edge And Pad 10^1-2(618.544mil,1174.512mil) on L2
Board Outline Clearance(Outline Edge): (6.906mil < 15mil) Between Board Edge And Pad 10^-1-3(222.638mil,1174.512mil) on L1
Board Outline Clearance(Outline Edge): (6.906mil < 15mil) Between Board Edge And Pad 10^-1-3(222.638mil,1174.512mil) on L2
Board Outline Clearance(Outline Edge): (6.906mil < 15mil) Between Board Edge And Pad 10^1-3(823.268mil,1174.512mil) on L1
Board Outline Clearance(Outline Edge): (6.906mil < 15mil) Between Board Edge And Pad 10^1-3(823.268mil,1174.512mil) on L2
Board Outline Clearance(Outline Edge): (14.512mil < 15mil) Between Board Edge And Pad 10^-2-1(54.512mil,802.362mil) on L2
Board Outline Clearance(Outline Edge): (10.001mil < 15mil) Between Board Edge And Pad RFIN-1(485mil,50mil) on L1
Board Outline Clearance(Outline Edge): (11.906mil < 15mil) Between Board Edge And Pad RFIN-2(382.638mil,100.488mil) on L1
Board Outline Clearance(Outline Edge): (11.906mil < 15mil) Between Board Edge And Pad RFIN-2(382.638mil,100.488mil) on L2
Board Outline Clearance(Outline Edge): (11.906mil < 15mil) Between Board Edge And Pad RFIN-3(587.362mil,100.488mil) on L1
Board Outline Clearance(Outline Edge): (11.906mil < 15mil) Between Board Edge And Pad RFIN-3(587.362mil,100.488mil) on L2
Board Outline Clearance(Outline Edge): (12.702mil < 15mil) Between Board Edge And Track (15.654mil,643.898mil)(202.44mil,643.898mil) on Bottom Overlay
Board Outline Clearance(Outline Edge): (12.702mil < 15mil) Between Board Edge And Track (15.654mil,960.828mil)(202.44mil,960.826mil) on Bottom Overlay
Board Outline Clearance(Outline Edge): (3.19mil < 15mil) Between Board Edge And Track (166.536mil,1077.07mil)(166.536mil,1263.858mil) on Top Overlay
Board Outline Clearance(Outline Edge): (8.19mil < 15mil) Between Board Edge And Track (326.536mil,11.142mil)(326.536mil,197.93mil) on Top Overlay
Board Outline Clearance(Outline Edge): (3.19mil < 15mil) Between Board Edge And Track (483.464mil,1077.07mil)(483.464mil,1263.858mil) on Top Overlay
Board Outline Clearance(Outline Edge): (3.19mil < 15mil) Between Board Edge And Track (562.442mil,1077.07mil)(562.442mil,1263.858mil) on Bottom Overlay
Board Outline Clearance(Outline Edge): (8.19mil < 15mil) Between Board Edge And Track (643.464mil,11.142mil)(643.464mil,197.93mil) on Top Overlay
Board Outline Clearance(Outline Edge): (8.19mil < 15mil) Between Board Edge And Track (852.07mil,656.536mil)(1038.858mil,656.536mil) on Top Overlay
Board Outline Clearance(Outline Edge): (8.19mil < 15mil) Between Board Edge And Track (852.07mil,973.464mil)(1038.858mil,973.464mil) on Top Overlay
Board Outline Clearance(Outline Edge): (3.19mil < 15mil) Between Board Edge And Track (879.37mil,1077.07mil)(879.37mil,1263.858mil) on Bottom Overlay
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