Design Rule Verification Report

Date:		10/1/2018
Time:		10:20:00 PM
Elapsed Time:		00:00:00
Filename:		C:\Users\marvin_the_paranoid\Desktop\Project\PCB\PP_18_010-JTAG2LVDS\PCB1.PcbDoc

Warnings:		0
Rule Violations:		121

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=10mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)	15
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=1mil) (Max=100mil) (All)	2
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All)	11
Silk To Solder Mask (Clearance=10mil) (IsPad),(All)	74
Silk to Silk (Clearance=10mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Board Clearance Constraint (Gap=0mil) (All)	5
Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))	14
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	121

Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)
Width Constraint: Track (1725mil,1590mil)(1820mil,1685mil) on Top Layer Actual Width = 14mil, Target Width = 10mil
Width Constraint: Track (1741.181mil,1950.63mil)(1850.63mil,1841.181mil) on Bottom Layer Actual Width = 17mil, Target Width = 10mil
Width Constraint: Track (1820mil,1685mil)(1865mil,1685mil) on Top Layer Actual Width = 14mil, Target Width = 10mil
Width Constraint: Track (1845.63mil,1328.819mil)(1845.63mil,1360.63mil) on Top Layer Actual Width = 14mil, Target Width = 10mil
Width Constraint: Track (1845.63mil,1360.63mil)(1885.355mil,1400.355mil) on Top Layer Actual Width = 14mil, Target Width = 10mil
Width Constraint: Track (1845.63mil,1431.181mil)(1845.63mil,1545.275mil) on Bottom Layer Actual Width = 16mil, Target Width = 10mil
Width Constraint: Track (1845.63mil,1545.275mil)(1890mil,1589.645mil) on Bottom Layer Actual Width = 16mil, Target Width = 10mil
Width Constraint: Track (1850.63mil,1814.37mil)(1850.63mil,1841.181mil) on Bottom Layer Actual Width = 17mil, Target Width = 10mil
Width Constraint: Track (1850.63mil,1814.37mil)(1890mil,1775mil) on Bottom Layer Actual Width = 17mil, Target Width = 10mil
Width Constraint: Track (1865mil,1685mil)(1890mil,1710mil) on Top Layer Actual Width = 14mil, Target Width = 10mil
Width Constraint: Track (1885.355mil,1400.355mil)(1885.355mil,1585mil) on Top Layer Actual Width = 14mil, Target Width = 10mil
Width Constraint: Track (1890mil,1589.645mil)(1890mil,1590mil) on Bottom Layer Actual Width = 17mil, Target Width = 10mil
Width Constraint: Track (1890mil,1590mil)(1890mil,1775mil) on Bottom Layer Actual Width = 17mil, Target Width = 10mil
Width Constraint: Track (1890mil,1710mil)(1890mil,1738.819mil) on Top Layer Actual Width = 14mil, Target Width = 10mil
Width Constraint: Track (1890mil,1738.819mil)(1890mil,1935mil) on Top Layer Actual Width = 14mil, Target Width = 10mil

Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Hole Size Constraint: (127.953mil > 100mil) Pad J?-M1(2610mil,1750mil) on Multi-Layer Actual Hole Size = 127.953mil
Hole Size Constraint: (127.953mil > 100mil) Pad J?-M2(2160mil,1750mil) on Multi-Layer Actual Hole Size = 127.953mil

Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (3.811mil < 10mil) Between Pad B1-1(1845.63mil,1328.819mil) on Top Layer And Pad B1-2(1885mil,1328.819mil) on Top Layer [Top Solder] Mask Sliver [3.811mil]
Minimum Solder Mask Sliver Constraint: (3.811mil < 10mil) Between Pad B1-2(1885mil,1328.819mil) on Top Layer And Pad B1-3(1924.37mil,1328.819mil) on Top Layer [Top Solder] Mask Sliver [3.811mil]
Minimum Solder Mask Sliver Constraint: (4.165mil < 10mil) Between Pad B1-2(1885mil,1328.819mil) on Top Layer And Via (1885mil,1270mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [4.165mil]
Minimum Solder Mask Sliver Constraint: (3.811mil < 10mil) Between Pad B2-1(1850.63mil,1841.181mil) on Bottom Layer And Pad B2-2(1890mil,1841.181mil) on Bottom Layer [Bottom Solder] Mask Sliver [3.811mil]
Minimum Solder Mask Sliver Constraint: (3.811mil < 10mil) Between Pad B2-2(1890mil,1841.181mil) on Bottom Layer And Pad B2-3(1929.37mil,1841.181mil) on Bottom Layer [Bottom Solder] Mask Sliver [3.811mil]
Minimum Solder Mask Sliver Constraint: (3.811mil < 10mil) Between Pad B3-1(1845.63mil,1431.181mil) on Bottom Layer And Pad B3-2(1885mil,1431.181mil) on Bottom Layer [Bottom Solder] Mask Sliver [3.811mil]
Minimum Solder Mask Sliver Constraint: (3.811mil < 10mil) Between Pad B3-2(1885mil,1431.181mil) on Bottom Layer And Pad B3-3(1924.37mil,1431.181mil) on Bottom Layer [Bottom Solder] Mask Sliver [3.811mil]
Minimum Solder Mask Sliver Constraint: (3.811mil < 10mil) Between Pad B4-1(1850.63mil,1738.819mil) on Top Layer And Pad B4-2(1890mil,1738.819mil) on Top Layer [Top Solder] Mask Sliver [3.811mil]
Minimum Solder Mask Sliver Constraint: (3.811mil < 10mil) Between Pad B4-2(1890mil,1738.819mil) on Top Layer And Pad B4-3(1929.37mil,1738.819mil) on Top Layer [Top Solder] Mask Sliver [3.811mil]
Minimum Solder Mask Sliver Constraint: (3.181mil < 10mil) Between Pad J2-4(1605mil,1595mil) on Multi-Layer And Pad J5-3(1605mil,1655mil) on Multi-Layer [Top Solder] Mask Sliver [3.181mil] / [Bottom Solder] Mask Sliver [3.181mil]
Minimum Solder Mask Sliver Constraint: (3.181mil < 10mil) Between Pad J2-5(1505mil,1595mil) on Multi-Layer And Pad J5-2(1505mil,1655mil) on Multi-Layer [Top Solder] Mask Sliver [3.181mil] / [Bottom Solder] Mask Sliver [3.181mil]

Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (6.859mil < 10mil) Between Arc (1725mil,1590mil) on Top Overlay And Pad TP?-1(1725mil,1590mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.859mil]
Silk To Solder Mask Clearance Constraint: (6.859mil < 10mil) Between Arc (1741.181mil,1965mil) on Top Overlay And Pad TP?-1(1741.181mil,1965mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.859mil]
Silk To Solder Mask Clearance Constraint: (6.859mil < 10mil) Between Arc (1905.355mil,1590mil) on Top Overlay And Pad TP1-1(1905.355mil,1590mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.859mil]
Silk To Solder Mask Clearance Constraint: (6.859mil < 10mil) Between Arc (1920mil,1965mil) on Top Overlay And Pad TP2-1(1920mil,1965mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.859mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B1-1(1845.63mil,1328.819mil) on Top Layer And Track (1825.945mil,1350.472mil)(1825.945mil,1409.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B1-1(1845.63mil,1328.819mil) on Top Layer And Track (1825.945mil,1350.472mil)(1944.055mil,1350.472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B1-2(1885mil,1328.819mil) on Top Layer And Track (1825.945mil,1350.472mil)(1944.055mil,1350.472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B1-3(1924.37mil,1328.819mil) on Top Layer And Track (1825.945mil,1350.472mil)(1944.055mil,1350.472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B1-3(1924.37mil,1328.819mil) on Top Layer And Track (1944.055mil,1350.472mil)(1944.055mil,1409.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B1-4(1924.37mil,1431.181mil) on Top Layer And Track (1825.945mil,1409.528mil)(1944.055mil,1409.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B1-4(1924.37mil,1431.181mil) on Top Layer And Track (1944.055mil,1350.472mil)(1944.055mil,1409.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B1-5(1845.63mil,1431.181mil) on Top Layer And Track (1825.945mil,1350.472mil)(1825.945mil,1409.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B1-5(1845.63mil,1431.181mil) on Top Layer And Track (1825.945mil,1409.528mil)(1944.055mil,1409.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B2-1(1850.63mil,1841.181mil) on Bottom Layer And Track (1830.945mil,1760.472mil)(1830.945mil,1819.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B2-1(1850.63mil,1841.181mil) on Bottom Layer And Track (1830.945mil,1819.528mil)(1949.055mil,1819.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B2-2(1890mil,1841.181mil) on Bottom Layer And Track (1830.945mil,1819.528mil)(1949.055mil,1819.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B2-3(1929.37mil,1841.181mil) on Bottom Layer And Track (1830.945mil,1819.528mil)(1949.055mil,1819.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B2-3(1929.37mil,1841.181mil) on Bottom Layer And Track (1949.055mil,1760.472mil)(1949.055mil,1819.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B2-4(1929.37mil,1738.819mil) on Bottom Layer And Track (1830.945mil,1760.472mil)(1949.055mil,1760.472mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B2-4(1929.37mil,1738.819mil) on Bottom Layer And Track (1949.055mil,1760.472mil)(1949.055mil,1819.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B2-5(1850.63mil,1738.819mil) on Bottom Layer And Track (1830.945mil,1760.472mil)(1830.945mil,1819.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B2-5(1850.63mil,1738.819mil) on Bottom Layer And Track (1830.945mil,1760.472mil)(1949.055mil,1760.472mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B3-1(1845.63mil,1431.181mil) on Bottom Layer And Track (1825.945mil,1350.472mil)(1825.945mil,1409.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B3-1(1845.63mil,1431.181mil) on Bottom Layer And Track (1825.945mil,1409.528mil)(1944.055mil,1409.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B3-2(1885mil,1431.181mil) on Bottom Layer And Track (1825.945mil,1409.528mil)(1944.055mil,1409.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B3-3(1924.37mil,1431.181mil) on Bottom Layer And Track (1825.945mil,1409.528mil)(1944.055mil,1409.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B3-3(1924.37mil,1431.181mil) on Bottom Layer And Track (1944.055mil,1350.472mil)(1944.055mil,1409.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B3-4(1924.37mil,1328.819mil) on Bottom Layer And Track (1825.945mil,1350.472mil)(1944.055mil,1350.472mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B3-4(1924.37mil,1328.819mil) on Bottom Layer And Track (1944.055mil,1350.472mil)(1944.055mil,1409.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B3-5(1845.63mil,1328.819mil) on Bottom Layer And Track (1825.945mil,1350.472mil)(1825.945mil,1409.528mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B3-5(1845.63mil,1328.819mil) on Bottom Layer And Track (1825.945mil,1350.472mil)(1944.055mil,1350.472mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B4-1(1850.63mil,1738.819mil) on Top Layer And Track (1830.945mil,1760.472mil)(1830.945mil,1819.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B4-1(1850.63mil,1738.819mil) on Top Layer And Track (1830.945mil,1760.472mil)(1949.055mil,1760.472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B4-2(1890mil,1738.819mil) on Top Layer And Track (1830.945mil,1760.472mil)(1949.055mil,1760.472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B4-3(1929.37mil,1738.819mil) on Top Layer And Track (1830.945mil,1760.472mil)(1949.055mil,1760.472mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B4-3(1929.37mil,1738.819mil) on Top Layer And Track (1949.055mil,1760.472mil)(1949.055mil,1819.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B4-4(1929.37mil,1841.181mil) on Top Layer And Track (1830.945mil,1819.528mil)(1949.055mil,1819.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B4-4(1929.37mil,1841.181mil) on Top Layer And Track (1949.055mil,1760.472mil)(1949.055mil,1819.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (1.968mil < 10mil) Between Pad B4-5(1850.63mil,1841.181mil) on Top Layer And Track (1830.945mil,1760.472mil)(1830.945mil,1819.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.968mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad B4-5(1850.63mil,1841.181mil) on Top Layer And Track (1830.945mil,1819.528mil)(1949.055mil,1819.528mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (8.717mil < 10mil) Between Pad J?-M3(2692.087mil,1870.079mil) on Multi-Layer And Track (2751.732mil,2017.716mil)(2751.732mil,1305.118mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.717mil]
Silk To Solder Mask Clearance Constraint: (6.819mil < 10mil) Between Pad J?-M4(2077.913mil,1870.079mil) on Multi-Layer And Track (2019.449mil,2017.716mil)(2019.449mil,1305.118mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.819mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J2-2(1505mil,1495mil) on Multi-Layer And Track (1487.087mil,1477.087mil)(1487.087mil,1612.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J2-2(1505mil,1495mil) on Multi-Layer And Track (1487.087mil,1477.087mil)(1622.913mil,1477.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J2-3(1605mil,1495mil) on Multi-Layer And Track (1487.087mil,1477.087mil)(1622.913mil,1477.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (9.613mil < 10mil) Between Pad J2-3(1605mil,1495mil) on Multi-Layer And Track (1622.913mil,1477.087mil)(1622.913mil,1612.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.613mil]
Silk To Solder Mask Clearance Constraint: (4.065mil < 10mil) Between Pad J2-4(1605mil,1595mil) on Multi-Layer And Track (1487.087mil,1612.913mil)(1622.913mil,1612.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.065mil]
Silk To Solder Mask Clearance Constraint: (9.569mil < 10mil) Between Pad J2-4(1605mil,1595mil) on Multi-Layer And Track (1622.913mil,1477.087mil)(1622.913mil,1612.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.569mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J2-5(1505mil,1595mil) on Multi-Layer And Track (1487.087mil,1477.087mil)(1487.087mil,1612.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (5.04mil < 10mil) Between Pad J2-5(1505mil,1595mil) on Multi-Layer And Track (1487.087mil,1612.913mil)(1622.913mil,1612.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.04mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J3-2(1505mil,1825mil) on Multi-Layer And Track (1487.087mil,1807.087mil)(1487.087mil,1942.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J3-2(1505mil,1825mil) on Multi-Layer And Track (1487.087mil,1807.087mil)(1622.913mil,1807.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J3-3(1605mil,1825mil) on Multi-Layer And Track (1487.087mil,1807.087mil)(1622.913mil,1807.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (9.613mil < 10mil) Between Pad J3-3(1605mil,1825mil) on Multi-Layer And Track (1622.913mil,1807.087mil)(1622.913mil,1942.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.613mil]
Silk To Solder Mask Clearance Constraint: (4.065mil < 10mil) Between Pad J3-4(1605mil,1925mil) on Multi-Layer And Track (1487.087mil,1942.913mil)(1622.913mil,1942.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.065mil]
Silk To Solder Mask Clearance Constraint: (9.569mil < 10mil) Between Pad J3-4(1605mil,1925mil) on Multi-Layer And Track (1622.913mil,1807.087mil)(1622.913mil,1942.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.569mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J3-5(1505mil,1925mil) on Multi-Layer And Track (1487.087mil,1807.087mil)(1487.087mil,1942.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (5.04mil < 10mil) Between Pad J3-5(1505mil,1925mil) on Multi-Layer And Track (1487.087mil,1942.913mil)(1622.913mil,1942.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.04mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J4-2(1500mil,1320mil) on Multi-Layer And Track (1482.087mil,1302.087mil)(1482.087mil,1437.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J4-2(1500mil,1320mil) on Multi-Layer And Track (1482.087mil,1302.087mil)(1617.913mil,1302.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J4-3(1600mil,1320mil) on Multi-Layer And Track (1482.087mil,1302.087mil)(1617.913mil,1302.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (9.613mil < 10mil) Between Pad J4-3(1600mil,1320mil) on Multi-Layer And Track (1617.913mil,1302.087mil)(1617.913mil,1437.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.613mil]
Silk To Solder Mask Clearance Constraint: (4.065mil < 10mil) Between Pad J4-4(1600mil,1420mil) on Multi-Layer And Track (1482.087mil,1437.913mil)(1617.913mil,1437.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.065mil]
Silk To Solder Mask Clearance Constraint: (9.569mil < 10mil) Between Pad J4-4(1600mil,1420mil) on Multi-Layer And Track (1617.913mil,1302.087mil)(1617.913mil,1437.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.569mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J4-5(1500mil,1420mil) on Multi-Layer And Track (1482.087mil,1302.087mil)(1482.087mil,1437.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (5.04mil < 10mil) Between Pad J4-5(1500mil,1420mil) on Multi-Layer And Track (1482.087mil,1437.913mil)(1617.913mil,1437.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.04mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J5-2(1505mil,1655mil) on Multi-Layer And Track (1487.087mil,1637.087mil)(1487.087mil,1772.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J5-2(1505mil,1655mil) on Multi-Layer And Track (1487.087mil,1637.087mil)(1622.913mil,1637.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J5-3(1605mil,1655mil) on Multi-Layer And Track (1487.087mil,1637.087mil)(1622.913mil,1637.087mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (9.613mil < 10mil) Between Pad J5-3(1605mil,1655mil) on Multi-Layer And Track (1622.913mil,1637.087mil)(1622.913mil,1772.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.613mil]
Silk To Solder Mask Clearance Constraint: (4.065mil < 10mil) Between Pad J5-4(1605mil,1755mil) on Multi-Layer And Track (1487.087mil,1772.913mil)(1622.913mil,1772.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.065mil]
Silk To Solder Mask Clearance Constraint: (9.569mil < 10mil) Between Pad J5-4(1605mil,1755mil) on Multi-Layer And Track (1622.913mil,1637.087mil)(1622.913mil,1772.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.569mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J5-5(1505mil,1755mil) on Multi-Layer And Track (1487.087mil,1637.087mil)(1487.087mil,1772.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (5.04mil < 10mil) Between Pad J5-5(1505mil,1755mil) on Multi-Layer And Track (1487.087mil,1772.913mil)(1622.913mil,1772.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.04mil]

Board Clearance Constraint (Gap=0mil) (All)
Board Outline Clearance(Outline Edge): (8.308mil < 15mil) Between Arc (1741.181mil,1965mil) on Top Overlay And Board Edge
Board Outline Clearance(Outline Edge): (8.308mil < 15mil) Between Arc (1920mil,1965mil) on Top Overlay And Board Edge
Board Outline Clearance(Outline Edge): (10.001mil < 15mil) Between Area Fill (2155mil,1250mil) (2610mil,1355mil) on Bottom Overlay And Board Edge
Board Outline Clearance(Outline Edge): (8.478mil < 15mil) Between Board Edge And Text "+" (1804.528mil,2015mil) on Top Overlay
Board Outline Clearance(Outline Edge): (5mil < 15mil) Between Board Edge And Via (1885mil,1270mil) from Top Layer to Bottom Layer

Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component B1-SN65LVDS1DBVR(LVTTL-LVDS) (1885mil,1380mil) on Top Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component B2-SN65LVDS1DBVR(LVTTL-LVDS) (1890mil,1790mil) on Bottom Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component B3-SN65LVDS1DBVR(LVTTL-LVDS) (1885mil,1380mil) on Bottom Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component B4-SN65LVDT2DBVR(LVDS-LVTTL) (1890mil,1790mil) on Top Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component J?-0855085001 (2610mil,1750mil) on Top Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component J2-MMCX (1555mil,1545mil) on Top Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component J3-MMCX (1555mil,1875mil) on Top Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component J4-MMCX (1550mil,1370mil) on Top Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Component J5-MMCX (1555mil,1705mil) on Top Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between DIP Component U1-JTAG 14PIN (1275mil,1625mil) on Top Layer And Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1'))
Room Definition: Between Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1')) And Small Component TP?-TP 0.5mm (1725mil,1590mil) on Top Layer
Room Definition: Between Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1')) And Small Component TP?-TP 0.5mm (1741.181mil,1965mil) on Top Layer
Room Definition: Between Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1')) And Small Component TP1-TP 0.5mm (1905.355mil,1590mil) on Top Layer
Room Definition: Between Room Sheet1 (Bounding Region = (7045mil, 1060mil, 10420mil, 2525mil) (InComponentClass('Sheet1')) And Small Component TP2-TP 2.0mm (1920mil,1965mil) on Top Layer