LARC_USB_revBv02 Project Status
Project File: LARC_USB_revBv02.ise Current State: Synthesized
Module Name: TOP
  • Errors:
No Errors
Target Device: xc4vfx60-10ff1152
  • Warnings:
726 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
LARC_USB_revBv02 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 11,762 50,560 23%  
Number of 4 input LUTs 38,066 50,560 75%  
Logic Distribution     
Number of occupied Slices 25,278 25,280 99%  
    Number of Slices containing only related logic 23,988 25,278 94%  
    Number of Slices containing unrelated logic 1,290 25,278 5%  
Total Number of 4 input LUTs 40,366 50,560 79%  
Number used as logic 38,066      
Number used as a route-thru 2,272      
Number used as Shift registers 28      
Number of bonded IOBs
Number of bonded 436 576 75%  
Number of BUFG/BUFGCTRLs 13 32 40%  
    Number used as BUFGs 13      
    Number used as BUFGCTRLs 0      
Number of RPM macros 2      
Total equivalent gate count for design 440,700      
Additional JTAG gate count for IOBs 20,928      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue May 4 17:04:06 20100726 Warnings5 Infos
Translation ReportOut of DateTue May 4 17:01:56 2010000
Map ReportCurrentTue May 4 17:04:24 2010078 Warnings3 Infos
Place and Route ReportOut of DateTue May 4 17:04:01 201008 Warnings1 Info
Static Timing Report     
Bitgen ReportOut of DateTue May 4 17:01:52 2010018 Warnings0

Date Generated: 09/24/2010 - 10:06:58