LARC_USB_revBv02 Project Status | |||
Project File: | LARC_USB_revBv02.ise | Current State: | Synthesized |
Module Name: | TOP |
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No Errors |
Target Device: | xc4vfx60-10ff1152 |
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726 Warnings |
Product Version: | ISE 10.1.03 - Foundation Simulator |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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LARC_USB_revBv02 Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 11,762 | 50,560 | 23% | ||
Number of 4 input LUTs | 38,066 | 50,560 | 75% | ||
Logic Distribution | |||||
Number of occupied Slices | 25,278 | 25,280 | 99% | ||
Number of Slices containing only related logic | 23,988 | 25,278 | 94% | ||
Number of Slices containing unrelated logic | 1,290 | 25,278 | 5% | ||
Total Number of 4 input LUTs | 40,366 | 50,560 | 79% | ||
Number used as logic | 38,066 | ||||
Number used as a route-thru | 2,272 | ||||
Number used as Shift registers | 28 | ||||
Number of bonded IOBs | |||||
Number of bonded | 436 | 576 | 75% | ||
Number of BUFG/BUFGCTRLs | 13 | 32 | 40% | ||
Number used as BUFGs | 13 | ||||
Number used as BUFGCTRLs | 0 | ||||
Number of RPM macros | 2 | ||||
Total equivalent gate count for design | 440,700 | ||||
Additional JTAG gate count for IOBs | 20,928 |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue May 4 17:04:06 2010 | 0 | 726 Warnings | 5 Infos | |
Translation Report | Out of Date | Tue May 4 17:01:56 2010 | 0 | 0 | 0 | |
Map Report | Current | Tue May 4 17:04:24 2010 | 0 | 78 Warnings | 3 Infos | |
Place and Route Report | Out of Date | Tue May 4 17:04:01 2010 | 0 | 8 Warnings | 1 Info | |
Static Timing Report | ||||||
Bitgen Report | Out of Date | Tue May 4 17:01:52 2010 | 0 | 18 Warnings | 0 |