Belle II KLM Scint Firmware  1
klm_scrod.ucf
1 #General SCROD clocking
2 #NET BOARD_CLOCKP LOC=T3; #SPARE CLOCKP: U23
3 #NET BOARD_CLOCKN LOC=T1; #SPARE CLOCKN: U24
4 
5 ################################################################
6 #Clock Constraints
7 ################################################################
8 
9 # NET clk PERIOD = 7.861 ns;
10 NET "ttdclkp" TNM_NET = "TTD_CLK";
11 TIMESPEC TS_TTD_CLK = PERIOD "TTD_CLK" 7.861 ns HIGH 50%;
12 # TIMESPEC TS_TTD_CLK = PERIOD "TTD_CLK" 15.723 ns HIGH 50%;
13 #NET "klm_intfc_i/sys_clk2x_ib" TNM_NET = SYS_CLK2X;
14 
15 NET "target_tb*<*><*>" TNM_NET = "TNM_TTB";
16 TIMESPEC TS_TTB = PERIOD "TNM_TTB" 100000 ns HIGH 12 ns;
17 
18 
19 #Internal - may be duplicated but software generated names are nonsense
20 #NET "klm_intfc_i/sys_clk_ib" TNM_NET = "SYS_CLK";
21 #NET "klm_intfc_i/sys_clk_ib" TNM = "SYS_CLK_GRP";
22 #TIMESPEC TS_SYS_CLK = PERIOD "SYS_CLK" 7.861 ns HIGH 50%;
23 #TIMESPEC TS_SYS_CLK2X = PERIOD "SYS_CLK2X" TS_SYS_CLK / 2 HIGH 50%;
24 
25 
26 ################################################################
27 #Muli-Cycle Path Constraints
28 #https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
29 ################################################################
30 # NET "klm_intfc_i/tdc_ce[*]" TNM_NET = FFS "TDC_2X_GRP";
31 # TIMESPEC TS_TDC_2X = FROM "TDC_2X_GRP" TO "TDC_2X_GRP" TS_TTD_CLK * 2;
32 #
33 # NET "KLMReadoutCtrl_i/WaveformProcessing_i/bus?/clear_fifos_r_0_?" TNM="WaveFifoClear"; # does not match any design objects.
34 # NET "KLMReadoutCtrl_i/WaveformProcessing_i/bus?/WaveAndPedStaging_i[*].U5_i/*fifos_empty<*>" TNM="FifosEmpty"; # does not match any design objects.
35 # TIMESPEC TS_FIFO_empty = FROM "WaveFifoClear" TO "FifosEmpty" TS_TTD_CLK*5;
36 #
37 # NET "KLMReadoutCtrl_i/WaveformProcessing_i/bus?/WaveAndPedStaging_i[*].U5_i/reset" TNM="FifosReset"; # does not match any design objects.
38 # TIMESPEC TS_FIFO_reset = FROM "WaveFifoClear" TO "FifosReset" TS_TTD_CLK*5;
39 #
40 # NET "KLMReadoutCtrl_i/WaveformProcessing_i/wave_config_*" TNM = "WaveConfig"; # does not match any design objects.
41 # NET "KLMReadoutCtrl_i/WaveformProcessing_i/bus?/*" TNM = "SingleBusProcessing";
42 # TIMESPEC TS_WaveConfig = FROM "WaveConfig" TO "SingleBusProcessing" TS_TTD_CLK*5;
43 # needs work. This constraint ignored paths like KLMReadoutCtrl_i/WaveformProcessing_i/busA/U1/ShftWin_i/U0/samplesel_any_i to SAMPLESEL_ANY<0>
44 # KURTIS SAYS TRY MULTICYCLE CONSTRAINT FOR SLOW CONTROL
45 
46 # INST "KLMReadoutCtrl_i/WaveformProcessing_i/busA/fifos_empty*" TNM=FFS "FifosEmpty";
47 # INST "*/*/*/fifos_empty*" TNM=FFS "FifosEmpty"; # FYI: THIS SYNTAX WORKS.
48 # TIMESPEC TS_FifosEmpty = TO "FifosEmpty" 1000 ns DATAPATHONLY; # FYI: THIS SYNTAX WORKS.
49 
50 # INST "*/*/*/fifos_empty*" TNM=FFS "FifosEmpty"; # FYI: THIS SYNTAX WORKS.
51 # INST "*/*/*/clear_fifos*" TNM=FFS "ClearFifos"; # FYI: THIS SYNTAX WORKS.
52 # TIMESPEC TS_FifosEmpty = FROM "ClearFifofs" TO "FifosEmpty" 1000 ns DATAPATHONLY; # FYI: THIS SYNTAX WORKS.
53 
54 # INST "*/*/sca_cnt_ena*" TNM=FFS "ScalerCountEnable";
55 # INST "*/*/i_scalers_arr*" TNM=FFS "ScalersArray";
56 # TIMESPEC TS_ScalerCounting = FROM "ScalerCountEnable" TO "ScalersArray" 80 ns DATAPATHONLY;
57 
58 # INST "KLMReadoutCtrl_i/WaveformProcessing_i/bus?/clear_fifos_r*" TNM=FFS "ClearFifos";
59 # TIMESPEC TS_ClearFifos = FROM "ClearFifos" TO "FifosEmpty" 50 ns DATAPATHONLY;
60 
61 # INST "KLMReadoutCtrl_i/WaveformProcessing_i/bus?/WaveAndPedStaging_i[*].U5_i/reset_1" TNM "FifosResetAll";
62 # TIMESPEC TS_FifosResetAll = TO "FifosResetAll" 10 ns DATAPATHONLY;
63 
64 # INST "KLMReadoutCtrl_i/WaveformProcessing_i/busB/WaveAndPedStaging_i[14].U5_i/reset" TNM=FFS "FifosReset_B14";
65 # TIMESPEC TS_FifosEmpty = TO "FifosReset_B14" 10 ns DATAPATHONLY;
66 
67 # make run_reset group containing all flip-flop's driven by b2tt_runreset
68 #NET KLMReadoutCtrl_i/WaveformProcessing_i/b2tt_runreset TNM_NET = FFS run_reset_grp;
69 #TIMESPEC TS_RRG = FROM FFS(b2tt_ins/*) TO run_reset_grp TS_TTD_CLK*5;
70 #TIMESPEC TS_IRG = FROM run_reset_grp TO run_reset_grp TS_TTD_CLK*3;
71 
72 # NET "i_trgon/" TNM = "slow_ctrl_trig_sel";
73 # NET "klm_intfc_i/inttb<*><*>" TNM = "trig_mux_out";
74 # NET "klm_intfc_i/inttb<*>" TNM = "trig_mux_out1";
75 # # NET "klm_intfc_i/inttb*/" TNM = "trig_mux_out2"; # does not match any design objects.
76 # TIMESPEC TS_TRG_SEL = FROM "slow_ctrl_trig_sel" TO "trig_mux_out" TIG;
77 # TIMESPEC TS_TRG_SEL1 = FROM "slow_ctrl_trig_sel" TO "trig_mux_out1" TIG;
78 # TIMESPEC TS_TRG_SEL2 = FROM "slow_ctrl_trig_sel" TO "trig_mux_out2" TIG;
79 
80 
81 ###########################################################
82 # Steer the Xilinx Synthesis Tool
83 ###########################################################
84 # Tool was laying out this module in a way that created gross timing violations.
85 # Emphasize the time spec to help steer XST.
86 # https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst_v6s6.pdf
87 #TIMESPEC TS_b2tt_crap = FROM FFS(b2tt_ins/map_decode/map_is/map_iscan/cnt_cycle*) TO FFS(b2tt_ins/map_decode/map_is/map_iscan/sta_lenmax*) TS_TTD_CLK;
88 
89 ###########################################################
90 # Timing ignore constraints
91 ###########################################################
92 #NET "mgttxfault*[*]" TIG;
93 #NET "mgtmod0*[*]" TIG;
94 #NET "mgtlos*[*]" TIG;
95 #NET "mgttxdis*[*]" TIG;
96 #NET "mgtmod2*[*]" TIG;
97 #NET "mgtmod1*[*]" TIG;
98 #NET "ex_trig*" TIG;
99 
100 #Diagnostics on LEDs (2.5 V and 3.3 V )- on the USB daughtercard which sits on MB RevB
101 #Connected LEDS' location on the USB DC is actually the MONx location
102 #LEDS 0-9 are on top row of the USB DC
103 #LEDS 10-12 are on bottom row of the USB DC
104 #Rest of the LEDS are not connected to anywhere.
105 #NET LEDS<0> LOC=E1;# | IOSTANDARD=LVCMOS33; #MON0
106 #NET LEDS<1> LOC=E2;# | IOSTANDARD=LVCMOS33; #MON1
107 #NET LEDS<2> LOC=D1 | OUT_TERM=UNTUNED_50;# | IOSTANDARD=LVCMOS33; #MON2
108 #NET LEDS<3> LOC=C1;# | IOSTANDARD=LVCMOS33; #MON3
109 #NET LEDS<4> LOC=C2;# | IOSTANDARD=LVCMOS33; #MON4
110 #NET LEDS<5> LOC=B1;# | IOSTANDARD=LVCMOS33; #MON5
111 #NET LEDS<6> LOC=K10;# | IOSTANDARD=LVCMOS33; #MON6
112 #NET LEDS<7> LOC=J9;# | IOSTANDARD=LVCMOS33; #MON7
113 #NET LEDS<8> LOC=L10;# | IOSTANDARD=LVCMOS33; #MON8
114 #NET LEDS<9> LOC=K9;# | IOSTANDARD=LVCMOS33; #MON9
115 #NET LEDS<10> LOC=F5 | IOSTANDARD=LVCMOS33; #MON16
116 #NET LEDS<11> LOC=A4 | IOSTANDARD=LVCMOS33; #MON17
117 #NET LEDS<12> LOC=D5 | IOSTANDARD=LVCMOS33; #MON18
118 
119 # NET LEDS<3> LOC=C1;
120 # NET LEDS<4> LOC=C2;
121 # NET LEDS<5> LOC=B1;
122 # NET LEDS<6> LOC=K10;
123 # NET LEDS<7> LOC=J9;
124 # NET LEDS<8> LOC=L10;
125 # NET LEDS<9> LOC=K9;
126 # NET LEDS<10> LOC=F5 | IOSTANDARD=LVCMOS33;
127 # NET LEDS<11> LOC=A4 | IOSTANDARD=LVCMOS33; #MON17
128 # NET LEDS<12> LOC=D5 | IOSTANDARD=LVCMOS33; #MON18
129 
130 
131 #NET "ScrodStatus_TbFifoCnt<*><*>" TIG;
132 #NET "ScrodStatus_TbFifoFullCnt<*><*>" TIG;
133 #NET "ScrodStatus_QtFifoFullCnt<*>" TIG;
134 #NET "ScrodStatus_TrgCnt<*>" TIG;
135 #NET "ScrodStatus_TrgProcCnt<*>" TIG;
136 #NET "ScrodStatus_HitsOverflowCnt<*>" TIG;
137 
138 #NET "ScrodConfig_DummyHitsNumber<*>" TIG;
139 #NET "ScrodConfig_TBLookBack<*>" TIG;
140 #NET "ScrodConfig_TBLookBackWidth<*>" TIG;
141 #NET "ScrodConfig_TBHitsNumMax<*>" TIG;
142 #NET "ScrodConfig_ReadoutMode<*>" TIG;
143 #NET "ScrodConfig_TestModeCntMax<*>" TIG;
144 #NET "ScrodConfig_TBScalersPeriod<*>" TIG;
145 #NET "ScrodConfig_ScalersAsicN<*>" TIG;
146 #NET "ScrodConfig_TxLatchPeriod<*>" TIG;
147 #NET "ScrodConfig_TxLoadPeriod<*>" TIG;
148 #NET "ScrodConfig_TxProcMask<*>" TIG;
149 #NET "readout_simple_i/i_scalers_all<*><*><*>" TIG;
150 
151 #NET "b2tt_ins/map_decode/map_pa/sig_runreset" TIG;
152 #NET "b2tt_ins/map_decode/map_pa/buf_rstmask" TIG;
153 
154 
155 ## CK: Comment these two out b/c SYS_CLK_GRP and SYS_CLK2X_GRP are not defined. 2020/07/21.
156 ## [Clk_0 period * N cycles]
157 # TIMESPEC TS_CCD_TDC2SYS = FROM "SYS_CLK_GRP" TO "SYS_CLK2X_GRP" TS_SYS_CLK2X DATAPATHONLY;
158 ## [Clk_1 period * N cycles]
159 # TIMESPEC TS_CCD_SYS2TDC = FROM "SYS_CLK2X_GRP" TO "SYS_CLK_GRP" TS_SYS_CLK2X DATAPATHONLY;
160 
161 ###########################################################
162 #Location Constraints
163 ###########################################################
164 
165 ##############################
166 # GTP
167 ##############################
168 #INST klm_intfc_i/aurora_ins/klm_aurora_ins/gtp_wrapper_i/gtp_tile_inst/CCL?_GEN.gtpa1_dual_i LOC=GTPA1_DUAL_X0Y1;
169 
170 ##############################
171 #EXT TRIG
172 ##############################
173 #NET ex_trig1 LOC=D22 | IOSTANDARD=LVCMOS33 | PULLUP;
174 
175 
176 ##############################
177 #B2TT
178 ##############################
179 NET TTDACKP LOC=AD14 | IOSTANDARD=LVDS_25;
180 NET TTDACKN LOC=AF14 | IOSTANDARD=LVDS_25;
181 NET TTDTRGP LOC=AB14 | IOSTANDARD=LVDS_25 | DIFF_TERM=TRUE; # N.B. NOT TERMINATED SCROD
182 NET TTDTRGN LOC=AC14 | IOSTANDARD=LVDS_25 | DIFF_TERM=TRUE;
183 NET TTDCLKP LOC=AE13 | IOSTANDARD=LVDS_25 | DIFF_TERM=TRUE;
184 NET TTDCLKN LOC=AF13 | IOSTANDARD=LVDS_25 | DIFF_TERM=TRUE;
185 NET TTDRSVP LOC=AE15 | IOSTANDARD=LVCMOS25;
186 NET TTDRSVN LOC=AF15 | IOSTANDARD=LVCMOS25;
187 
188 
189 
190 ###############################
191 ##SFP
192 ###############################
193 NET MGTTXFAULT[1] LOC=A5 | IOSTANDARD=LVCMOS33;
194 NET MGTTXDIS[1] LOC=E8 | IOSTANDARD=LVCMOS33;
195 NET MGTMOD2[1] LOC=A12 | IOSTANDARD=LVCMOS33;
196 NET MGTMOD1[1] LOC=B12 | IOSTANDARD=LVCMOS33;
197 NET MGTMOD0[1] LOC=C5 | IOSTANDARD=LVCMOS33;
198 NET MGTLOS[1] LOC=B5 | IOSTANDARD=LVCMOS33;
199 NET mgtRXP LOC=D7;
200 NET mgtRXN LOC=C7;
201 NET mgtTXP LOC=B6;
202 NET mgtTXN LOC=A6;
203 NET mgtclk0p LOC = B10 | IOSTANDARD=LVDS_25; #TTD clock
204 NET mgtclk0n LOC = A10 | IOSTANDARD=LVDS_25;
205 NET mgtclk1p LOC = D11 | IOSTANDARD=LVDS_25; #onboard oscillator
206 NET mgtclk1n LOC = C11 | IOSTANDARD=LVDS_25;
207 ##############################
208 
209 ##############################
210 #Fake
211 ##############################
212 #NET status_fake LOC=F16 | IOSTANDARD=LVCMOS33;
213 #NET control_fake LOC=J17 | IOSTANDARD=LVCMOS33;
214 
215 
216 ############################################
217 #analog MUX lines for ADC readout of MPPC currents
218 ############################################
219 
220 # NET TDC_AMUX_S<0> LOC= Y17; #CK FW module needs work
221 # NET TDC_AMUX_S<1> LOC= AA17; #CK FW module needs work
222 # NET TDC_AMUX_S<2> LOC= AA8; #CK FW module needs work
223 # NET TDC_AMUX_S<3> LOC= Y9; #CK FW module needs work
224 # NET TOP_AMUX_S<0> LOC= N18; #CK FW module needs work
225 # NET TOP_AMUX_S<1> LOC= T19; #CK FW module needs work
226 # NET TOP_AMUX_S<2> LOC= V12; #CK FW module needs work
227 # NET TOP_AMUX_S<3> LOC= W12; #CK FW module needs work
228 
229 NET TDC_CS_DAC<0> LOC= V11; # TDC1_CS_DAC, J3_065_T19
230 NET TDC_CS_DAC<1> LOC= V13; # TDC2_CS_DAC, J3_064_R19
231 NET TDC_CS_DAC<2> LOC= V16; # TDC3_CS_DAC, J3_062_R21
232 NET TDC_CS_DAC<3> LOC= Y21; # TDC4_CS_DAC, J3_061_P21
233 NET TDC_CS_DAC<4> LOC= AA22; # TDC5_CS_DAC,
234 NET TDC_CS_DAC<5> LOC= N17; # TDC6_CS_DAC,
235 NET TDC_CS_DAC<6> LOC= P17; # TDC7_CS_DAC,
236 NET TDC_CS_DAC<7> LOC= R18; # TDC8_CS_DAC,
237 NET TDC_CS_DAC<8> LOC= Y11; # TDC9_CS_DAC,
238 NET TDC_CS_DAC<9> LOC= AA11; # TDC10_CS_DAC,
239 
240 NET SCLK<0> LOC= K3;
241 NET SHOUT<0> LOC= F3;
242 NET SIN<0> LOC= M3;
243 NET PCLK<0> LOC= H3; # TDC1_PCLK, J1_098_K1
244 NET SCLK<1> LOC= L3;
245 NET SHOUT<1> LOC= G3;
246 NET SIN<1> LOC= N3;
247 NET PCLK<1> LOC= J3; # TDC2_PCLK, J1_078_N5
248 NET SCLK<2> LOC= G2;
249 NET SHOUT<2> LOC= H1;
250 NET SIN<2> LOC= F1;
251 NET PCLK<2> LOC= G1; # TDC3_PCLK, J1_026_AD1
252 NET SCLK<3> LOC= U8;
253 NET SHOUT<3> LOC= V7;
254 NET SIN<3> LOC= U9;
255 NET PCLK<3> LOC= U5; # TDC4_PCLK, J1_042_N4
256 NET SCLK<4> LOC= R10;
257 NET SHOUT<4> LOC= R8;
258 NET SIN<4> LOC= P3;
259 NET PCLK<4> LOC= R9; # TDC5_PCLK,
260 NET SCLK<5> LOC= N20;
261 NET SHOUT<5> LOC= P21;
262 NET SIN<5> LOC= E1;
263 #NET SIN<5> LOC= AF23; # TDC6_SIN, # use this for MB Rev B
264 NET PCLK<5> LOC= U21; # TDC6_PCLK,
265 NET SCLK<6> LOC= W24;
266 NET SHOUT<6> LOC= V21;
267 NET SIN<6> LOC= V23;
268 NET PCLK<6> LOC= AC23; # TDC7_PCLK,
269 NET SCLK<7> LOC= AC26;
270 NET SHOUT<7> LOC= AA26;
271 NET SIN<7> LOC= AC25;
272 NET PCLK<7> LOC= AB26; # TDC8_PCLK,
273 NET SCLK<8> LOC= M26;
274 NET SHOUT<8> LOC= L25;
275 NET SIN<8> LOC= N25;
276 NET PCLK<8> LOC= L26; # TDC9_PCLK,
277 NET SCLK<9> LOC= AB24;
278 NET SHOUT<9> LOC= Y24;
279 NET SIN<9> LOC= AC24;
280 NET PCLK<9> LOC= AA24; # TDC10_PCLK,
281 
282 NET SSTIN_N<0> LOC= AA12 | IOSTANDARD=LVDS_25; # TDC1_SSTIN_N, J1_007_R1
283 NET SSTIN_P<0> LOC= Y12 | IOSTANDARD=LVDS_25; # TDC1_SSTIN_P, J1_008_R2
284 NET SSTIN_N<1> LOC= AF4 | IOSTANDARD=LVDS_25; # TDC2_SSTIN_N, J1_069_W3
285 NET SSTIN_P<1> LOC= AD4 | IOSTANDARD=LVDS_25; # TDC2_SSTIN_P, J1_070_V4
286 NET SSTIN_N<2> LOC= AF6 | IOSTANDARD=LVDS_25; # TDC3_SSTIN_N, J1_015_W1
287 NET SSTIN_P<2> LOC= AD6 | IOSTANDARD=LVDS_25; # TDC3_SSTIN_P, J1_016_W2
288 NET SSTIN_N<3> LOC= AC6 | IOSTANDARD=LVDS_25; # TDC4_SSTIN_N, J1_023_AC1
289 NET SSTIN_P<3> LOC= AB7 | IOSTANDARD=LVDS_25; # TDC4_SSTIN_P, J1_024_AC2
290 NET SSTIN_N<4> LOC= W9 | IOSTANDARD=LVDS_25; # TDC5_SSTIN_N
291 NET SSTIN_P<4> LOC= W10 | IOSTANDARD=LVDS_25; # TDC5_SSTIN_P
292 NET SSTIN_N<5> LOC= AB21 | IOSTANDARD=LVDS_25; # TDC6_SSTIN_N,
293 NET SSTIN_P<5> LOC= AA21 | IOSTANDARD=LVDS_25; # TDC6_SSTIN_P,
294 NET SSTIN_N<6> LOC= AB19 | IOSTANDARD=LVDS_25; # TDC7_SSTIN_N,
295 NET SSTIN_P<6> LOC= AA19 | IOSTANDARD=LVDS_25; # TDC7_SSTIN_P,
296 NET SSTIN_N<7> LOC= W18 | IOSTANDARD=LVDS_25; # TDC8_SSTIN_N,
297 NET SSTIN_P<7> LOC= W17 | IOSTANDARD=LVDS_25; # TDC8_SSTIN_P,
298 NET SSTIN_N<8> LOC= Y16 | IOSTANDARD=LVDS_25; # TDC9_SSTIN_N,
299 NET SSTIN_P<8> LOC= W16 | IOSTANDARD=LVDS_25; # TDC9_SSTIN_P,
300 NET SSTIN_N<9> LOC= AA13 | IOSTANDARD=LVDS_25; # TDC10_SSTIN_N,
301 NET SSTIN_P<9> LOC= AB13 | IOSTANDARD=LVDS_25; # TDC10_SSTIN_P,
302 
303 
304 
305 
306 ##############################
307 # TARGET ASIC
308 ##############################
309 
310 ############################################################################
311 
312 ##########################################################################
313 #Pin mappings and timing constraints here are based on the SCROD_revA3.
314 
315 #TARGETX 9U Motherboard JUN-11-2014
316 #The following was generated using a script to extract the code from the xcel sheet entries (on right side)
317 #Then manually edited for bus routings
318 ############################################################################
319 
320 NET BUSA_CLR LOC= N9; # BUSA_CLR
321 
322 NET BUSA_DO<0> LOC= N7; # BUSA_DO_1
323 NET BUSA_DO<1> LOC= N6; # BUSA_DO_2
324 NET BUSA_DO<2> LOC= N5; # BUSA_DO_3
325 NET BUSA_DO<3> LOC= N4; # BUSA_DO_4
326 NET BUSA_DO<4> LOC= P10; # BUSA_DO_5
327 NET BUSA_DO<5> LOC= P8; # BUSA_DO_6, J2_009_AF5
328 NET BUSA_DO<6> LOC= P6; # BUSA_DO_7, J2_011_AE5
329 NET BUSA_DO<7> LOC= P5; # BUSA_DO_8, J2_012_AF6
330 NET BUSA_DO<8> LOC= AA6; # BUSA_DO_9, J2_013_AD6
331 NET BUSA_DO<9> LOC= W8; # BUSA_DO_10, J2_015_AA10
332 NET BUSA_DO<10> LOC= W7; # BUSA_DO_11, J2_016_AA9
333 NET BUSA_DO<11> LOC= AD3; # BUSA_DO_12, J2_017_V11
334 NET BUSA_DO<12> LOC= AC4; # BUSA_DO_13, J2_019_Y11
335 NET BUSA_DO<13> LOC= AC3; # BUSA_DO_14, J2_020_AB13
336 NET BUSA_DO<14> LOC= AB5; # BUSA_DO_15, J2_021_V12
337 #NET BUSA_DO<15> LOC= AB4; # BUSA_DO_16, J2_023_AA12
338 NET BUSA_RAMP LOC=AC2; # BUSA_RAMP, J2_097_W7
339 NET BUSA_RD_COLSEL<0> LOC= T6; # BUSA_RD_CS_S0, J2_088_W10
340 NET BUSA_RD_COLSEL<1> LOC= R3; # BUSA_RD_CS_S1, J2_089_W9
341 NET BUSA_RD_COLSEL<3> LOC= T4; # BUSA_RD_CS_S2, J2_090_Y9
342 NET BUSA_RD_COLSEL<2> LOC= U7; # BUSA_RD_CS_S3, J2_092_AA8-- Col2 and Col3 were switched out in DC Rev B, fixed here -- swaped again for Rev C
343 NET BUSA_RD_COLSEL<4> LOC= U4; # BUSA_RD_CS_S4, J2_093_AB7
344 NET BUSA_RD_COLSEL<5> LOC= V5; # BUSA_RD_CS_S5, J2_094_AC6
345 NET BUSA_RD_ENA LOC= M10; # BUSA_RD_ENA, J2_082_AA11
346 NET BUSA_RD_ROWSEL<0> LOC= AD1; # BUSA_RD_RS_S0, J2_084_V10
347 NET BUSA_RD_ROWSEL<1> LOC= AE1; # BUSA_RD_RS_S1, J2_085_AB9
348 NET BUSA_RD_ROWSEL<2> LOC= AE2; # BUSA_RD_RS_S2, J2_086_AB11
349 NET BUSA_SAMPLESEL<0> LOC= AA4; # BUSA_SAMPLESEL_S1, J2_076_V13
350 NET BUSA_SAMPLESEL<1> LOC= AA3; # BUSA_SAMPLESEL_S2, J2_077_Y12
351 NET BUSA_SAMPLESEL<2> LOC= Y6; # BUSA_SAMPLESEL_S3, J2_078_Y13
352 NET BUSA_SAMPLESEL<3> LOC= Y5; # BUSA_SAMPLESEL_S4, J2_080_W12
353 NET BUSA_SAMPLESEL<4> LOC= W3; # BUSA_SAMPLESEL_S5, J2_081_AA13
354 
355 NET BUSA_SCK_DAC LOC= U15;
356 NET BUSA_DIN_DAC LOC= U13; # BUSA_DIN_DAC
357 
358 NET BUSA_SR_CLEAR LOC= AA7; # BUSA_SR_CLEAR, J3_019_Y6
359 NET BUSA_SR_SEL LOC= AB11; # BUSA_SR_SEL, J3_020_K9
360 NET BUSA_WR_ADDRCLR LOC= U3; # BUSA_WR_ADDRCLR, J2_096_AD5
361 
362 
363 ########################BUSB signals########################################
364 NET BUSB_CLR LOC= B24; # BUSB_CLR, J2_045_B24
365 
366 NET BUSB_DO<0> LOC= A25; # BUSB_DO_1, J2_024_AA6
367 NET BUSB_DO<1> LOC= B25; # BUSB_DO_2, J2_025_P10
368 NET BUSB_DO<2> LOC= B26; # BUSB_DO_3, J2_027_M10_SDA
369 NET BUSB_DO<3> LOC= C25; # BUSB_DO_4, J2_028_L10_SCL
370 NET BUSB_DO<4> LOC= C26; # BUSB_DO_5, J2_029_K10_SDA
371 NET BUSB_DO<5> LOC= D26; # BUSB_DO_6, J2_031_AA15
372 NET BUSB_DO<6> LOC= E25; # BUSB_DO_7, J2_032_V14
373 NET BUSB_DO<7> LOC= E26; # BUSB_DO_8, J2_033_Y15
374 NET BUSB_DO<8> LOC= H21; # BUSB_DO_9, J2_035_AA18
375 NET BUSB_DO<9> LOC= H22; # BUSB_DO_10, J2_035_W16
376 NET BUSB_DO<10> LOC= J24; # BUSB_DO_11, J2_037_AA19
377 NET BUSB_DO<11> LOC= H20; # BUSB_DO_12, J2_039_U15
378 NET BUSB_DO<12> LOC= J22; # BUSB_DO_13, J2_040_Y17
379 NET BUSB_DO<13> LOC= J23; # BUSB_DO_14, J2_041_AA21
380 NET BUSB_DO<14> LOC= J20; # BUSB_DO_15, J2_043_W17
381 #NET BUSB_DO<15> LOC= K24; # BUSB_DO_16, J2_044_AF22
382 
383 NET BUSB_RAMP LOC= F24; # BUSB_RAMP, J2_048_W20
384 NET BUSB_RD_COLSEL<0> LOC= L23; # BUSB_RD_CS_S0, J2_058_W18
385 NET BUSB_RD_COLSEL<1> LOC= L24; # BUSB_RD_CS_S1, J2_060_AB21
386 NET BUSB_RD_COLSEL<3> LOC= M18; # BUSB_RD_CS_S2, J2_061_AA17
387 NET BUSB_RD_COLSEL<2> LOC= M19; # BUSB_RD_CS_S3, J2_062_V16 Col2 and Col3 were switched out in DC Rev B, fixed here, swaped again for Rev C
388 NET BUSB_RD_COLSEL<4> LOC= M21; # BUSB_RD_CS_S4, J2_064_AB19
389 NET BUSB_RD_COLSEL<5> LOC= M24; # BUSB_RD_CS_S5, J2_065_Y16
390 
391 NET BUSB_RD_ENA LOC= D24; # BUSB_RD_ENA, J2_049_Y21
392 NET BUSB_RD_ROWSEL<0> LOC= E23; # BUSB_RD_RS_S0, J2_052_AA22
393 NET BUSB_RD_ROWSEL<1> LOC= E24; # BUSB_RD_RS_S1, J2_053_Y20
394 NET BUSB_RD_ROWSEL<2> LOC= D23; # BUSB_RD_RS_S2, J2_054_AC22
395 
396 NET BUSB_SAMPLESEL<0> LOC= K20; # BUSB_SAMPLESEL_S1, J2_066_AB17
397 NET BUSB_SAMPLESEL<1> LOC= K21; # BUSB_SAMPLESEL_S2, J2_068_AA16
398 NET BUSB_SAMPLESEL<2> LOC= K19; # BUSB_SAMPLESEL_S3, J2_069_V15
399 NET BUSB_SAMPLESEL<3> LOC= K18; # BUSB_SAMPLESEL_S4, J2_070_AB15
400 NET BUSB_SAMPLESEL<4> LOC= L20; # BUSB_SAMPLESEL_S5, J2_072_P17
401 
402 NET BUSB_DIN_DAC LOC = AC1;
403 NET BUSB_SCK_DAC LOC = AB1;
404 
405 NET BUSB_SR_CLEAR LOC= G20; # BUSB_SR_CLEAR, J2_073_W14
406 NET BUSB_SR_SEL LOC= G23; # BUSB_SR_SEL, J2_074_U13
407 NET BUSB_WR_ADDRCLR LOC= M23; # BUSB_WR_ADDRCLR, J2_047_AB22
408 
409 
410 #NET BUS_REGCLR LOC= M9;
411 
412 #NET EX_TRIGGER_MB LOC= V10 ; #Goes to a 2.5 V Bank on teh FPGA
413 #NET EX_TRIGGER_SCROD LOC= D22 | IOSTANDARD=LVCMOS33;
414 #NET EX_TRIGGER_SCROD LOC= D22 | IOSTANDARD=LVCMOS33 | OUT_TERM=UNTUNED_50; #The on scrod ex_trigger
415 
416 # NET SCL_MON LOC= A2 | IOSTANDARD=LVCMOS33; # SCL_MON, J3_021_H13_SCL0
417 # NET SDA_MON LOC= A3 | IOSTANDARD=LVCMOS33; # SDA_MON, J3_023_F14_SDA0
418 
419 #NET target_tb16<1> LOC= "G4"; #TDC1_TRG_16
420 #NET target_tb16<2> LOC= "AD4"; #TDC2_TRG_16
421 #NET target_tb16<3> LOC= "Y12"; #TDC3_TRG_16
422 #NET target_tb16<4> LOC= "K8"; #TDC4_TRG_16
423 #NET target_tb16<5> LOC= "U8"; #TDC5_TRG_16
424 #NET target_tb16<6> LOC= "AD26"; #TDC6_TRG_16
425 #NET target_tb16<7> LOC= "AA15"; #TDC7_TRG_16
426 #NET target_tb16<8> LOC= "AB21"; #TDC8_TRG_16
427 #NET target_tb16<9> LOC= "N19"; #TDC9_TRG_16
428 #NET target_tb16<10> LOC= "U20"; #TDC10_TRG_16
429 
430 
431 ####TARGETX Daughtercard#1
432 NET TARGET_TB<1><1> LOC= L9; # TDC1_TRG_1, J1_087_G4
433 NET TARGET_TB<1><2> LOC= K8; # TDC1_TRG_2, J1_089_F3
434 NET TARGET_TB<1><3> LOC= D3; # TDC1_TRG_3, J1_090_E3
435 NET TARGET_TB<1><4> LOC= L4; # TDC1_TRG_4, J1_094_M1
436 NET TARGET_TB<1><5> LOC= G4; # TDC1_TRG_5, J1_095_L2
437 
438 
439 ####TARGETX Daughtercard#2
440 NET TARGET_TB<2><1> LOC= B2; # TDC2_TRG_1, J1_065_AB3
441 NET TARGET_TB<2><2> LOC= L8; # TDC2_TRG_2, J1_066_AA3
442 NET TARGET_TB<2><3> LOC= E3; # TDC2_TRG_3, J1_067_Y3
443 NET TARGET_TB<2><4> LOC= M4; # TDC2_TRG_4, J1_071_U5
444 NET TARGET_TB<2><5> LOC= J4; # TDC2_TRG_5, J1_073_U3
445 
446 
447 ####TARGETX Daughtercard#3
448 NET TARGET_TB<3><1> LOC= T8; # TDC3_TRG_1, J1_110_D1
449 NET TARGET_TB<3><2> LOC= T9; # TDC3_TRG_2, J1_111_C2
450 NET TARGET_TB<3><3> LOC= J2; # TDC3_TRG_3, J1_113_C1
451 NET TARGET_TB<3><4> LOC= J1; # TDC3_TRG_4, J1_114_E1
452 NET TARGET_TB<3><5> LOC= K1; # TDC3_TRG_5, J1_115_F1
453 
454 
455 ####TARGETX Daughtercard#4
456 NET TARGET_TB<4><1> LOC= W2; # TDC4_TRG_1, J1_035_J3
457 NET TARGET_TB<4><2> LOC= W1; # TDC4_TRG_2, J1_036_J5
458 NET TARGET_TB<4><3> LOC= V6; # TDC4_TRG_3, J1_038_K5
459 NET TARGET_TB<4><4> LOC= V4; # TDC4_TRG_4, J1_039_L4
460 NET TARGET_TB<4><5> LOC= W5; # TDC4_TRG_5, J1_040_M4
461 
462 
463 ####TARGETX Daughtercard#5
464 
465 NET TARGET_TB<5><1> LOC= Y1; # TDC5_TRG_1,
466 NET TARGET_TB<5><2> LOC= AA1; # TDC5_TRG_2,
467 NET TARGET_TB<5><3> LOC= R7; # TDC5_TRG_3,
468 NET TARGET_TB<5><4> LOC= R6; # TDC5_TRG_4,
469 NET TARGET_TB<5><5> LOC= R4; # TDC5_TRG_5,
470 
471 
472 ####TARGETX Daughtercard#6
473 NET TARGET_TB<6><1> LOC= E2; # TDC6_TRG_1,
474 NET TARGET_TB<6><2> LOC= D1; # TDC6_TRG_2,
475 NET TARGET_TB<6><3> LOC= U22; # TDC6_TRG_3,
476 NET TARGET_TB<6><4> LOC= P22; # TDC6_TRG_4,
477 NET TARGET_TB<6><5> LOC= N23; # TDC6_TRG_5,
478 
479 
480 
481 ####TARGETX Daughtercard#7
482 NET TARGET_TB<7><1> LOC= R21; # TDC7_TRG_1, J4_085_F22
483 NET TARGET_TB<7><2> LOC= N21; # TDC7_TRG_2, J4_086_F24
484 NET TARGET_TB<7><3> LOC= R20; # TDC7_TRG_3, J4_087_E24
485 NET TARGET_TB<7><4> LOC= AF22; # TDC7_TRG_4, J4_089_D24
486 NET TARGET_TB<7><5> LOC= U20; # TDC7_TRG_5, J4_090_C24
487 
488 
489 
490 ####TARGETX Daughtercard#8
491 NET TARGET_TB<8><1> LOC= AD26; # TDC8_TRG_1,
492 NET TARGET_TB<8><2> LOC= AE26; # TDC8_TRG_2,
493 NET TARGET_TB<8><3> LOC= AA25; # TDC8_TRG_3,
494 NET TARGET_TB<8><4> LOC= Y26; # TDC8_TRG_4,
495 NET TARGET_TB<8><5> LOC= W26; # TDC8_TRG_5,
496 
497 
498 ####TARGETX Daughtercard#9
499 NET TARGET_TB<9><1> LOC= N26; # TDC9_TRG_1,
500 NET TARGET_TB<9><2> LOC= P26; # TDC9_TRG_2,
501 NET TARGET_TB<9><3> LOC= K26; # TDC9_TRG_3,
502 NET TARGET_TB<9><4> LOC= J26; # TDC9_TRG_4,
503 NET TARGET_TB<9><5> LOC= J25; # TDC9_TRG_5,
504 
505 
506 ####TARGETX Daughtercard#10
507 NET TARGET_TB<10><1> LOC= G24; # TDC10_TRG_1,
508 NET TARGET_TB<10><2> LOC= F22; # TDC10_TRG_2,
509 NET TARGET_TB<10><3> LOC= V24; # TDC10_TRG_3,
510 NET TARGET_TB<10><4> LOC= N24; # TDC10_TRG_4,
511 NET TARGET_TB<10><5> LOC= T24; # TDC10_TRG_5,
512 
513 
514 
515 ####TARGETX Daughtercard#1
516 # NET TDC_DONE<0> LOC= K7; # TDC1_DONE, J1_105_G1
517 # NET TDC_MON_TIMING<0> LOC= M8; # TDC1_MON_TIMING, J1_106_B1
518 NET SAMPLESEL_ANY<0> LOC= L6; # TDC1_SAMPLESEL_ANY, J1_102_H1
519 NET SR_CLOCK<0> LOC= H6; # TDC1_SR_CLOCK, J1_103_G2
520 
521 NET WL_CLK_N<0> LOC= AF5 | IOSTANDARD=LVDS_25; # TDC1_WL_CLK_N, J1_093_N1
522 NET WL_CLK_P<0> LOC= AE5 | IOSTANDARD=LVDS_25; # TDC1_WL_CLK_P, J1_091_N2
523 
524 NET WR1_ENA<0> LOC= K5; # TDC1_WR1_ENA, J1_107_E2
525 NET WR2_ENA<0> LOC= H5; # TDC1_WR2_ENA, J1_109_B2
526 
527 
528 
529 ####TARGETX Daughtercard#2
530 # NET TDC_DONE<1> LOC= L7; # TDC2_DONE, J1_081_M3
531 # NET TDC_MON_TIMING<1> LOC= J7; # TDC2_MON_TIMING, J1_079_N3
532 NET SAMPLESEL_ANY<1> LOC= M6; # TDC2_SAMPLESEL_ANY, J1_083_K3
533 NET SR_CLOCK<1> LOC= K6; # TDC2_SR_CLOCK, J1_082_L3
534 
535 NET WL_CLK_N<1> LOC= AD5 | IOSTANDARD=LVDS_25; # TDC2_WL_CLK_N, J1_062_AC4
536 NET WL_CLK_P<1> LOC= AC5 | IOSTANDARD=LVDS_25;
537 NET WR1_ENA<1> LOC= E4; # TDC2_WR1_ENA, J1_085_J4
538 NET WR2_ENA<1> LOC= J5; # TDC2_WR2_ENA, J1_086_H5
539 
540 
541 ####TARGETX Daughtercard#3
542 # NET TDC_DONE<2> LOC= N1; # TDC3_DONE, J1_018_Y1
543 # NET TDC_MON_TIMING<2> LOC= R5; # TDC3_MON_TIMING, J1_022_AB1
544 NET SAMPLESEL_ANY<2> LOC= M1; # TDC3_SAMPLESEL_ANY, J1_010_T1
545 NET SR_CLOCK<2> LOC= N2; # TDC3_SR_CLOCK, J1_014_V1
546 
547 NET WL_CLK_N<2> LOC= Y13 | IOSTANDARD=LVDS_25; # TDC3_WL_CLK_N, J1_011_U1
548 NET WL_CLK_P<2> LOC= W14 | IOSTANDARD=LVDS_25; # TDC3_WL_CLK_P, J1_012_U2
549 
550 NET WR1_ENA<2> LOC= L2; # TDC3_WR1_ENA, J1_032_G3
551 NET WR2_ENA<2> LOC= L1; # TDC3_WR2_ENA, J1_034_H3
552 
553 ####TARGETX Daughtercard#4
554 # NET TDC_DONE<3> LOC= U2; # TDC4_DONE, J1_048_U4
555 # NET TDC_MON_TIMING<3> LOC= V1; # TDC4_MON_TIMING, J1_050_V3
556 NET SAMPLESEL_ANY<3> LOC= R2; # TDC4_SAMPLESEL_ANY, J1_047_T4
557 NET SR_CLOCK<3> LOC= U1; # TDC4_SR_CLOCK, J1_054_Y5
558 
559 NET WL_CLK_N<3> LOC= AA16 | IOSTANDARD=LVDS_25; # TDC4_WL_CLK_N, J1_019_AA1
560 NET WL_CLK_P<3> LOC= Y15 | IOSTANDARD=LVDS_25; # TDC4_WL_CLK_P, J1_020_AA2
561 
562 NET WR1_ENA<3> LOC= P1; # TDC4_WR1_ENA, J1_055_AA4
563 NET WR2_ENA<3> LOC= R1; # TDC4_WR2_ENA, J1_056_AB4
564 
565 ####TARGETX Daughtercard#5
566 # NET TDC_DONE<4> LOC= N8; # TDC5_DONE,
567 # NET TDC_MON_TIMING<4> LOC= AA2; # TDC5_MON_TIMING,
568 NET SAMPLESEL_ANY<4> LOC= AB3; # TDC5_SAMPLESEL_ANY,
569 NET SR_CLOCK<4> LOC= AA10; # TDC5_SR_CLOCK,
570 
571 NET WL_CLK_N<4> LOC= AB9 | IOSTANDARD=LVDS_25; # TDC5_WL_CLK_N,
572 NET WL_CLK_P<4> LOC= AA9 | IOSTANDARD=LVDS_25; # TDC5_WL_CLK_P,
573 
574 NET WR1_ENA<4> LOC= V3; # TDC5_WR1_ENA,
575 NET WR2_ENA<4> LOC= Y3; # TDC5_WR2_ENA,
576 
577 ####TARGETX Daughtercard#6
578 # NET TDC_DONE<5> LOC= P19; # TDC6_DONE,
579 # NET TDC_MON_TIMING<5> LOC= V20; # TDC6_MON_TIMING,
580 NET SAMPLESEL_ANY<5> LOC= AA23; # TDC6_SAMPLESEL_ANY
581 NET SR_CLOCK<5> LOC= T23; # TDC6_SR_CLOCK,
582 
583 NET WL_CLK_N<5> LOC= AC22 | IOSTANDARD=LVDS_25; # TDC6_WL_CLK_N,
584 NET WL_CLK_P<5> LOC= AB22 | IOSTANDARD=LVDS_25; # TDC6_WL_CLK_P,
585 
586 NET WR1_ENA<5> LOC= R23; # TDC6_WR1_ENA,
587 NET WR2_ENA<5> LOC= P24; # TDC6_WR2_ENA,
588 
589 
590 ####TARGETX Daughtercard#7
591 # NET TDC_DONE<6> LOC= N22; # TDC7_DONE,
592 # NET TDC_MON_TIMING<6> LOC= T22; # TDC7_MON_TIMING,
593 NET SAMPLESEL_ANY<6> LOC= R19; # TDC7_SAMPLESEL_ANY,
594 NET SR_CLOCK<6> LOC= U19; # TDC7_SR_CLOCK,
595 
596 NET WL_CLK_N<6> LOC= Y20 | IOSTANDARD=LVDS_25; # TDC7_WL_CLK_N,
597 NET WL_CLK_P<6> LOC= W20 | IOSTANDARD=LVDS_25; # TDC7_WL_CLK_P,
598 
599 NET WR1_ENA<6> LOC= T20; # TDC7_WR1_ENA, J4_113_R25
600 NET WR2_ENA<6> LOC= N19; # TDC7_WR2_ENA, J4_114_R26
601 
602 
603 ####TARGETX Daughtercard#8
604 # NET TDC_DONE<7> LOC= AD24; # TDC8_DONE,
605 # NET TDC_MON_TIMING<7> LOC= AE25; # TDC8_MON_TIMING,
606 NET SAMPLESEL_ANY<7> LOC= U26; # TDC8_SAMPLESEL_ANY,
607 NET SR_CLOCK<7> LOC= U25; # TDC8_SR_CLOCK,
608 
609 NET WL_CLK_N<7> LOC= AB17 | IOSTANDARD=LVDS_25; # TDC8_WL_CLK_N,
610 NET WL_CLK_P<7> LOC= AA18 | IOSTANDARD=LVDS_25; # TDC8_WL_CLK_P,
611 
612 NET WR1_ENA<7> LOC= W25; # TDC8_WR1_ENA,
613 NET WR2_ENA<7> LOC= V26; # TDC8_WR2_ENA,
614 
615 ####TARGETX Daughtercard#9
616 # NET TDC_DONE<8> LOC= T26; # TDC9_DONE,
617 # NET TDC_MON_TIMING<8> LOC= R24; # TDC9_MON_TIMING,
618 NET SAMPLESEL_ANY<8> LOC= G25; # TDC9_SAMPLESEL_ANY,
619 NET SR_CLOCK<8> LOC= F26; # TDC9_SR_CLOCK,
620 
621 NET WL_CLK_N<8> LOC= AB15 | IOSTANDARD=LVDS_25; # TDC9_WL_CLK_N,
622 NET WL_CLK_P<8> LOC= AA15 | IOSTANDARD=LVDS_25; # TDC9_WL_CLK_P,
623 
624 NET WR1_ENA<8> LOC= H26; # TDC9_WR1_ENA,
625 NET WR2_ENA<8> LOC= G26; # TDC9_WR2_ENA,
626 
627 ####TARGETX Daughtercard#10
628 # NET TDC_DONE<9> LOC= C24; # TDC10_DONE,
629 # NET TDC_MON_TIMING<9> LOC= F23; # TDC10_MON_TIMING,
630 NET SAMPLESEL_ANY<9> LOC= K22; # TDC10_SAMPLESEL_ANY,
631 NET SR_CLOCK<9> LOC= H24; # TDC10_SR_CLOCK
632 
633 NET WL_CLK_N<9> LOC= V15 | IOSTANDARD=LVDS_25; # TDC10_WL_CLK_N,
634 NET WL_CLK_P<9> LOC= V14 | IOSTANDARD=LVDS_25; # TDC10_WL_CLK_P,
635 
636 NET WR1_ENA<9> LOC= L19; # TDC10_WR1_ENA,
637 NET WR2_ENA<9> LOC= L21; # TDC10_WR2_ENA,
638 
639 
640 ######################################################################
641 #RAM for pedestals
642 #############################################
643 
644 NET RAM_CEb LOC= J15 | IOSTANDARD=LVCMOS33;
645 NET RAM_CE LOC= H19 | IOSTANDARD=LVCMOS33;
646 NET RAM_OEb LOC= H15 | IOSTANDARD=LVCMOS33;
647 NET RAM_WEb LOC= G19 | IOSTANDARD=LVCMOS33;
648 
649 
650 NET RAM_IO<0> LOC= G15 | IOSTANDARD=LVCMOS33;
651 NET RAM_IO<1> LOC= F15 | IOSTANDARD=LVCMOS33;
652 NET RAM_IO<2> LOC= K14 | IOSTANDARD=LVCMOS33;
653 NET RAM_IO<3> LOC= H14 | IOSTANDARD=LVCMOS33;
654 NET RAM_IO<4> LOC= F14 | IOSTANDARD=LVCMOS33;
655 NET RAM_IO<5> LOC= E14 | IOSTANDARD=LVCMOS33;
656 NET RAM_IO<6> LOC= B14 | IOSTANDARD=LVCMOS33;
657 NET RAM_IO<7> LOC= A14 | IOSTANDARD=LVCMOS33;
658 
659 NET RAM_ADDR<0> LOC= F16 | IOSTANDARD=LVCMOS33;
660 NET RAM_ADDR<1> LOC= B23 | IOSTANDARD=LVCMOS33;
661 NET RAM_ADDR<2> LOC= A23 | IOSTANDARD=LVCMOS33;
662 NET RAM_ADDR<3> LOC= B22 | IOSTANDARD=LVCMOS33;
663 NET RAM_ADDR<4> LOC= A22 | IOSTANDARD=LVCMOS33;
664 NET RAM_ADDR<5> LOC= D21 | IOSTANDARD=LVCMOS33;
665 NET RAM_ADDR<6> LOC= C21 | IOSTANDARD=LVCMOS33;
666 NET RAM_ADDR<7> LOC= B21 | IOSTANDARD=LVCMOS33;
667 NET RAM_ADDR<8> LOC= F18 | IOSTANDARD=LVCMOS33;
668 NET RAM_ADDR<9> LOC= E18 | IOSTANDARD=LVCMOS33;
669 NET RAM_ADDR<10> LOC= J17 | IOSTANDARD=LVCMOS33;
670 NET RAM_ADDR<11> LOC= H17 | IOSTANDARD=LVCMOS33;
671 NET RAM_ADDR<12> LOC= G17 | IOSTANDARD=LVCMOS33;
672 NET RAM_ADDR<13> LOC= F17 | IOSTANDARD=LVCMOS33;
673 NET RAM_ADDR<14> LOC= J16 | IOSTANDARD=LVCMOS33;
674 NET RAM_ADDR<15> LOC= G16 | IOSTANDARD=LVCMOS33;
675 NET RAM_ADDR<16> LOC= H13 | IOSTANDARD=LVCMOS33;
676 NET RAM_ADDR<17> LOC= F20 | IOSTANDARD=LVCMOS33;
677 NET RAM_ADDR<18> LOC= E20 | IOSTANDARD=LVCMOS33;
678 NET RAM_ADDR<19> LOC= H18 | IOSTANDARD=LVCMOS33;
679 NET RAM_ADDR<20> LOC= F19 | IOSTANDARD=LVCMOS33;
680 NET RAM_ADDR<21> LOC= J13 | IOSTANDARD=LVCMOS33;
681 
682 ##########################################################################################
683 
684 
685 #NET TMP<1> LOC = "A13" | IOSTANDARD=LVCMOS33; # USB_CLKOUT
686 #NET TMP<2> LOC = "G10" | IOSTANDARD=LVCMOS33;
687 #NET TMP<3> LOC = "F11" | IOSTANDARD=LVCMOS33;
688 #NET TMP<4> LOC = "J11" | IOSTANDARD=LVCMOS33;
689 #NET TMP<5> LOC = "H12" | IOSTANDARD=LVCMOS33;
690 #NET TMP<6> LOC = "J12" | IOSTANDARD=LVCMOS33;
691 #NET TMP<7> LOC = "K12" | IOSTANDARD=LVCMOS33;
692 #NET TMP<8> LOC = "D13" | IOSTANDARD=LVCMOS33;
693 #NET TMP<9> LOC = "E13" | IOSTANDARD=LVCMOS33;
694 #NET TMP<10> LOC = "F12" | IOSTANDARD=LVCMOS33;
695 #NET TMP<11> LOC = "E12" | IOSTANDARD=LVCMOS33;
696 #NET TMP<12> LOC = "G11" | IOSTANDARD=LVCMOS33;
697 #NET TMP<13> LOC = "H10" | IOSTANDARD=LVCMOS33;
698 #NET TMP<14> LOC = "F10" | IOSTANDARD=LVCMOS33;
699 #NET TMP<15> LOC = "H9" | IOSTANDARD=LVCMOS33;
700 #NET TMP<16> LOC = "F9" | IOSTANDARD=LVCMOS33;
701 #NET TMP<17> LOC = "H8" | IOSTANDARD=LVCMOS33;
702 #NET TMP<18> LOC = "G7" | IOSTANDARD=LVCMOS33;
703 #NET TMP<19> LOC = "G6" | IOSTANDARD=LVCMOS33;
704 #NET TMP<20> LOC = "E6" | IOSTANDARD=LVCMOS33;
705 #NET TMP<21> LOC = "E5" | IOSTANDARD=LVCMOS33;
706 #NET TMP<22> LOC = "B4" | IOSTANDARD=LVCMOS33;
707 #NET TMP<23> LOC = "C3" | IOSTANDARD=LVCMOS33;
708 #NET TMP<24> LOC = "B3" | IOSTANDARD=LVCMOS33;
709 #NET TMP<25> LOC = "G13" | IOSTANDARD=LVCMOS33;
710 #NET TMP<26> LOC = "E10" | IOSTANDARD=LVCMOS33;
711 #NET TMP<27> LOC = "G9" | IOSTANDARD=LVCMOS33;
712 #NET TMP<28> LOC = "G8" | IOSTANDARD=LVCMOS33;
713 #NET TMP<29> LOC = "F7" | IOSTANDARD=LVCMOS33;
714 #NET TMP<30> LOC = "F6" | IOSTANDARD=LVCMOS33;
715 #NET TMP<31> LOC = "G12" | IOSTANDARD=LVCMOS33;