Date: Fri, 11 Feb 2011 12:49:39 -0500 From: Patrick Allison Subject: DDA rev B schematics Hi all: Just heard back from the board house - as it turns out, they're saying they changed their layer stackup 2 months ago - i.e. just around when the DDAs were ordered. I had asked about the stackup earlier when the DDAs were still being finalized. I think they're offering to run the design again, so I'm sending around the schematics/layout for the DDA rev B. List of changes: 1: Low-pass filter on both the DAC outputs (Vdly and VadjN), nominally 1k/10 nF (time constant of 10 us). This is to smooth out the DAC outputs to absorb the digital feedthrough. Obviously this can be removed if needed, but it should've been there from the beginning. 2: Add pads to allow for either an ADM1176 or an ADM1178 to be used for the hot-swap controller. This was what required the first mods to the DDA rev A to allow it to turn on - the 1176/1178 are almost functionally identical except the 1176 uses pin 10 for GATE whereas the 1178 uses pin 9 for GATE. Also added information on the silkscreen to indicate which pads to populate for which part. 3: Add R29/R30 pads to allow for either an IRS2 or an IRS to be used, along with information on silkscreen as to which pads to populate. R30 is a (permanent) 4 way switch made out of 4 0603 pads - install 0 ohm resistors vertically for one configuration, and horizontally for the other configuration. R29 is a (permanent) DPST switch made out of 3 0603 pads - install a 0 ohm resistor between pads 1-2 for one configuration, between 2-3 for the other. (Leaving in the IRS configuration is essentially free since the voltage regulator, etc. were already on the board). IRS: pin 118: VADJN2 pin 119: VADJN1 pin 120: VADJP2 (GND) pin 121: VADJP1 (GND) IRS2: pin 118: 2.5V pin 119: TRGthref (GND) pin 120: VADJ pin 121: VADP (GND) Switches on the schematic are shown for the IRS configuration, and details are on the schematic for the IRS2 configuration. 4: Pin 24 on J6/J7-A is now IRS/IRS2 pin 125, TSA_CLOSE (was TSTCLR) and pin 22 is reserved (was TSTST). TSTST and TSTCLR are now driven by a PCA9536, a 4-port I2C GPIO expander. Since TSTST/TSTCLR only need to be driven extremely rarely, it makes sense to drive them via I2C and reclaim their pins for the second TSA (which closes the sampling window). The PCA9536 is on page 10 (U5). The turn-on sequence for the DDA will basically be "turn on, write 1100 to GPIO output register, write 0100 to control register, write 1110 to output register, write 1101 to output register, write 1100 to output register." This will pulse TSTCLR high, then TSTST. 5: The remaining 2 ports on the PCA9536 are used as a disable for the 2.5V regulator for the IRS2 (IRS_PWR_EN) with a pullup (since on power-on, the PCA9536 has all outputs in high-impedance) and an LED (X2)... for fun, I guess. 6: The sense resistor on the hot-swap controller was lowered from 0.2 ohms to 0.1 ohms to push the current limit per board up to 1 amp. 7: The voltage reference for the AD5667 now has text indicating that it's an ADR121 (2.5V). 8: Trace widths for the RF inputs were reduced from 37.6 mil to 14.39 mil to match the (actual) 8 mil layer spacing of the board house. Any comments are appreciated. Patrick