# 2012-06-05 revised for SCROD revA2

#Using on-board 250 MHz oscillator
NET BOARD_CLOCK_250MHz_P	LOC = "U25" | IOSTANDARD = LVDS_25;
NET BOARD_CLOCK_250MHz_N	LOC = "U26" | IOSTANDARD = LVDS_25;

#EEPROM and temperature sensor
NET "SCL"						LOC = "B23"	| IOSTANDARD = LVCMOS33;
NET "SDA"						LOC = "A23"	| IOSTANDARD = LVCMOS33 | PULLUP;

# new things for SCROD revA2:
#NET DO_NOT_USE_ME LOC = "AF3"; # on SCROD revA2, CSO_B (pin AF3) should not be driven low during normal running!
#NET 250_DIS LOC = "D22"; # test to see if jumper is installed; drive low to disable oscillator
#NET 156_DIS LOC = "D21"; # test to see if jumper is installed; drive low to disable oscillator
#NET thermal_alarm_active_low LOC = "E16"; # this is low if the temperature sensor got too hot (settable threshold) until an I2C transfer is initiated to clear it


#FTSW Inputs
NET RJ45_ACK_P		LOC = "ad14" | IOSTANDARD = LVDS_25;
NET RJ45_ACK_N		LOC = "af14" | IOSTANDARD = LVDS_25;
NET RJ45_TRG_P		LOC = "ab14" | IOSTANDARD = LVDS_25 | diff_term=true;
NET RJ45_TRG_N		LOC = "ac14" | IOSTANDARD = LVDS_25 | diff_term=true;
NET RJ45_RSV_P		LOC = "ae15" | IOSTANDARD = LVDS_25;
NET RJ45_RSV_N		LOC = "af15" | IOSTANDARD = LVDS_25;
NET RJ45_CLK_P		LOC = "ae13" | IOSTANDARD = LVDS_25 | diff_term=true;
NET RJ45_CLK_N		LOC = "af13" | IOSTANDARD = LVDS_25 | diff_term=true;

#Pins for controlling external DACs - separated by column.
NET DAC_SCL_C<0>		LOC = "H13" | IOSTANDARD = LVCMOS33; #DAC1 on SCROD schematic
NET DAC_SDA_C<0>		LOC = "F14" | IOSTANDARD = LVCMOS33; #DAC2 on SCROD schematic
NET DAC_SCL_C<1>		LOC = "E14" | IOSTANDARD = LVCMOS33; #DAC3 on SCROD schematic
NET DAC_SDA_C<1>		LOC = "K14" | IOSTANDARD = LVCMOS33; #DAC4 on SCROD schematic
NET DAC_SCL_C<2>		LOC = "H14" | IOSTANDARD = LVCMOS33; #DAC5 on SCROD schematic
NET DAC_SDA_C<2>		LOC = "J15" | IOSTANDARD = LVCMOS33; #DAC6 on SCROD schematic
NET DAC_SCL_C<3>		LOC = "H15" | IOSTANDARD = LVCMOS33; #DAC7 on SCROD schematic
NET DAC_SDA_C<3>		LOC = "J16" | IOSTANDARD = LVCMOS33; #DAC8 on SCROD schematic

#Pins for ASIC sampling and analog storage
NET	AsicIn_SAMPLING_HOLD_MODE_C<0>				LOC = 	W8;	#SST_IN_A
NET	AsicIn_SAMPLING_HOLD_MODE_C<1>				LOC = 	AE2;	#SST_IN_B
NET	AsicIn_SAMPLING_HOLD_MODE_C<2>				LOC = 	AC3;	#SST_IN_C
NET	AsicIn_SAMPLING_HOLD_MODE_C<3>				LOC = 	N19;	#SST_IN_D
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<2>		LOC = 	W14;	#WR_ADDR_0  #swapped with pin 2 relative to IRS2 schematic
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<1>		LOC = 	P17;	#WR_ADDR_1
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<0>		LOC = 	AB15;	#WR_ADDR_2  #swapped with pin 0 relative to IRS2 schematic
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<3>		LOC = 	V15;	#WR_ADDR_3
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<4>		LOC = 	Y26;	#WR_ADDR_4
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<5>		LOC = 	W26;	#WR_ADDR_5
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<6>		LOC = 	U24;	#WR_ADDR_6
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<7>		LOC = 	T26;	#WR_ADDR_7
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS<8>		LOC = 	R26;	#WR_ADDR_8
NET	AsicIn_SAMPLING_TO_STORAGE_ADDRESS_ENABLE	LOC = 	AD26;	#WR_ADDR_9
NET	AsicIn_SAMPLING_TO_STORAGE_TRANSFER_C<0>	LOC = 	AA9;	#WR_STRB_A
NET	AsicIn_SAMPLING_TO_STORAGE_TRANSFER_C<1>	LOC = 	W17;	#WR_STRB_B
NET	AsicIn_SAMPLING_TO_STORAGE_TRANSFER_C<2>	LOC = 	J9;	#WR_STRB_C
NET	AsicIn_SAMPLING_TO_STORAGE_TRANSFER_C<3>	LOC = 	L19;	#WR_STRB_D
NET	AsicIn_SAMPLING_TRACK_MODE_C<0>				LOC = 	AD4;	#SSP_IN_A
NET	AsicIn_SAMPLING_TRACK_MODE_C<1>				LOC = 	AE1;	#SSP_IN_B
NET	AsicIn_SAMPLING_TRACK_MODE_C<2>				LOC = 	AB4;	#SSP_IN_C
NET	AsicIn_SAMPLING_TRACK_MODE_C<3>				LOC = 	P19;	#SSP_IN_D

#Pins for ASIC digitizing and readout
NET	AsicIn_DATA_BUS_CHANNEL_ADDRESS<0>			LOC = 	W19;	#CH_SEL0 # on SCROD revA2, this is overloaded with the SPI signals (which shouldn't matter during normal operation)
NET	AsicIn_DATA_BUS_CHANNEL_ADDRESS<1>			LOC = 	V18;	#CH_SEL1 # on SCROD revA2, this is overloaded with the SPI signals (which shouldn't matter during normal operation)
NET	AsicIn_DATA_BUS_CHANNEL_ADDRESS<2>			LOC = 	AC22;	#CH_SEL2
NET	AsicIn_DATA_BUS_SAMPLE_ADDRESS<0>			LOC = 	Y20;	#SMPL_SEL0
NET	AsicIn_DATA_BUS_SAMPLE_ADDRESS<1>			LOC = 	AA22;	#SMPL_SEL1
NET	AsicIn_DATA_BUS_SAMPLE_ADDRESS<2>			LOC = 	P26;	#SMPL_SEL2
NET	AsicIn_DATA_BUS_SAMPLE_ADDRESS<3>			LOC = 	R25;	#SMPL_SEL3
NET	AsicIn_DATA_BUS_SAMPLE_ADDRESS<4>			LOC = 	U23;	#SMPL_SEL4
NET	AsicIn_DATA_BUS_SAMPLE_ADDRESS<5>			LOC = 	V26;	#SMPL_SEL5
NET	AsicIn_DATA_BUS_OUTPUT_ENABLE					LOC = 	W18;	#SMPL_SEL_ALL
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C0_R<0>		LOC = 	P1;	#DBUS_A_SDC0
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C1_R<0>		LOC = 	J3;	#DBUS_B_SDC4
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C2_R<0>		LOC = 	L7;	#DBUS_C_SDC9
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C3_R<0>		LOC = 	K21;	#DBUS_D_SDC13
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C0_R<1>		LOC = 	R1;	#DBUS_A_SDC1
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C1_R<1>		LOC = 	J5;	#DBUS_B_SDC5
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C2_R<1>		LOC = 	M6;	#DBUS_C_SDC10
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C3_R<1>		LOC = 	H20;	#DBUS_D_SDC14
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C0_R<2>		LOC = 	R2;	#DBUS_A_SDC2
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C1_R<2>		LOC = 	K5;	#DBUS_B_SDC6
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C2_R<2>		LOC = 	N6;	#DBUS_C_SDC11
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C3_R<2>		LOC = 	G20;	#DBUS_D_SDC15
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C0_R<3>		LOC = 	T1;	#DBUS_A_SDC3
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C1_R<3>		LOC = 	L4;	#DBUS_B_SDC7
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C2_R<3>		LOC = 	N8;	#DBUS_C_SDC12
NET	AsicIn_DATA_BUS_OUTPUT_DISABLE_C3_R<3>		LOC = 	R19;	#DBUS_D_SDC16
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<2>			LOC = 	Y16;	#RD_ADDR_0  #swapped with pin 2 relative to IRS2 schematic
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<1>			LOC = 	AB19;	#RD_ADDR_1
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<0>			LOC = 	V16;	#RD_ADDR_2  #swapped with pin 0 relative to IRS2 schematic
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<3>			LOC = 	AA17;	#RD_ADDR_3
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<4>			LOC = 	AC25;	#RD_ADDR_4
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<5>			LOC = 	AA26;	#RD_ADDR_5
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<6>			LOC = 	AE26;	#RD_ADDR_6
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<7>			LOC = 	AC26;	#RD_ADDR_7
NET	AsicIn_STORAGE_TO_WILK_ADDRESS<8>			LOC = 	AB26;	#RD_ADDR_8
NET	AsicIn_STORAGE_TO_WILK_ADDRESS_ENABLE		LOC = 	AA25;	#RD_ADDR_9
NET	AsicIn_STORAGE_TO_WILK_ENABLE					LOC = 	AB21;	#RD_ENA
NET	AsicIn_WILK_COUNTER_RESET						LOC = 	W25;	#TDC_CLR
NET	AsicIn_WILK_COUNTER_START_C<0>				LOC = 	AA12;	#TDC_START_A
NET	AsicIn_WILK_COUNTER_START_C<1>				LOC = 	Y21;	#TDC_START_B
NET	AsicIn_WILK_COUNTER_START_C<2>				LOC = 	T9;	#TDC_START_C
NET	AsicIn_WILK_COUNTER_START_C<3>				LOC = 	L24;	#TDC_START_D
NET	AsicIn_WILK_RAMP_ACTIVE							LOC = 	U13;	#RAMP
NET	AsicOut_DATA_BUS_C0<0>							LOC = 	U1;	#DAT0_A
NET	AsicOut_DATA_BUS_C0<1>							LOC = 	U2;	#DAT1_A
NET	AsicOut_DATA_BUS_C0<2>							LOC = 	V1;	#DAT2_A
NET	AsicOut_DATA_BUS_C0<3>							LOC = 	W1;	#DAT3_A
NET	AsicOut_DATA_BUS_C0<4>							LOC = 	W2;	#DAT4_A
NET	AsicOut_DATA_BUS_C0<5>							LOC = 	Y1;	#DAT5_A
NET	AsicOut_DATA_BUS_C0<6>							LOC = 	AA1;	#DAT6_A
NET	AsicOut_DATA_BUS_C0<7>							LOC = 	AA2;	#DAT7_A
NET	AsicOut_DATA_BUS_C0<8>							LOC = 	AB1;	#DAT8_A
NET	AsicOut_DATA_BUS_C0<9>							LOC = 	AC1;	#DAT9_A
NET	AsicOut_DATA_BUS_C0<10>							LOC = 	AC2;	#DAT10_A
NET	AsicOut_DATA_BUS_C0<11>							LOC = 	AD1;	#DAT11_A
NET	AsicOut_DATA_BUS_C1<0>							LOC = 	M4;	#DAT0_B
NET	AsicOut_DATA_BUS_C1<1>							LOC = 	N4;	#DAT1_B
NET	AsicOut_DATA_BUS_C1<2>							LOC = 	P3;	#DAT2_B
NET	AsicOut_DATA_BUS_C1<3>							LOC = 	R3;	#DAT3_B
NET	AsicOut_DATA_BUS_C1<4>							LOC = 	R5;	#DAT4_B
NET	AsicOut_DATA_BUS_C1<5>							LOC = 	T4;	#DAT5_B
NET	AsicOut_DATA_BUS_C1<6>							LOC = 	U4;	#DAT6_B
NET	AsicOut_DATA_BUS_C1<7>							LOC = 	V3;	#DAT7_B
NET	AsicOut_DATA_BUS_C1<8>							LOC = 	V5;	#DAT8_B
NET	AsicOut_DATA_BUS_C1<9>							LOC = 	W5;	#DAT9_B
NET	AsicOut_DATA_BUS_C1<10>							LOC = 	Y5;	#DAT10_B
NET	AsicOut_DATA_BUS_C1<11>							LOC = 	AA4;	#DAT11_B
NET	AsicOut_DATA_BUS_C2<0>							LOC = 	P8;	#DAT0_C
NET	AsicOut_DATA_BUS_C2<1>							LOC = 	R7;	#DAT1_C
NET	AsicOut_DATA_BUS_C2<2>							LOC = 	T6;	#DAT2_C
NET	AsicOut_DATA_BUS_C2<3>							LOC = 	U7;	#DAT3_C
NET	AsicOut_DATA_BUS_C2<4>							LOC = 	V6;	#DAT4_C
NET	AsicOut_DATA_BUS_C2<5>							LOC = 	Y6;	#DAT5_C
NET	AsicOut_DATA_BUS_C2<6>							LOC = 	K9;	#DAT6_C
NET	AsicOut_DATA_BUS_C2<7>							LOC = 	V20;	#DAT7_C
NET	AsicOut_DATA_BUS_C2<8>							LOC = 	U19;	#DAT8_C
NET	AsicOut_DATA_BUS_C2<9>							LOC = 	U21;	#DAT9_C
NET	AsicOut_DATA_BUS_C2<10>							LOC = 	T20;	#DAT10_C
NET	AsicOut_DATA_BUS_C2<11>							LOC = 	R20;	#DAT11_C
NET	AsicOut_DATA_BUS_C3<0>							LOC = 	N24;	#DAT0_D
NET	AsicOut_DATA_BUS_C3<1>							LOC = 	N22;	#DAT1_D
NET	AsicOut_DATA_BUS_C3<2>							LOC = 	P22;	#DAT2_D
NET	AsicOut_DATA_BUS_C3<3>							LOC = 	R23;	#DAT3_D
NET	AsicOut_DATA_BUS_C3<4>							LOC = 	T23;	#DAT4_D
NET	AsicOut_DATA_BUS_C3<5>							LOC = 	N17;	#DAT5_D
NET	AsicOut_DATA_BUS_C3<6>							LOC = 	U22;	#DAT6_D
NET	AsicOut_DATA_BUS_C3<7>							LOC = 	V23;	#DAT7_D
NET	AsicOut_DATA_BUS_C3<8>							LOC = 	Y24;	#DAT8_D
NET	AsicOut_DATA_BUS_C3<9>							LOC = 	AA23;	#DAT9_D
NET	AsicOut_DATA_BUS_C3<10>							LOC = 	AC24;	#DAT10_D
NET	AsicOut_DATA_BUS_C3<11>							LOC = 	AD24;	#DAT11_D

##Pins for ASIC feedback loops
##Trigger monitoring
NET AsicIn_MONITOR_TRIG								LOC = 	AF23;	#TRIG_IN # on SCROD revA2, J4_091_B24 is now J4_091_AF23/MOSI/MISO0
NET	AsicOut_MONITOR_TRIG_C0_R<0>					LOC = 	AE5;	#TRIG_MON_DC0
NET	AsicOut_MONITOR_TRIG_C1_R<0>					LOC = 	M1;	#TRIG_MON_DC1
NET	AsicOut_MONITOR_TRIG_C2_R<0>					LOC = 	J7;	#TRIG_MON_DC2
NET	AsicOut_MONITOR_TRIG_C3_R<0>					LOC = 	D23;	#TRIG_MON_DC3
NET	AsicOut_MONITOR_TRIG_C0_R<1>					LOC = 	AF6;	#TRIG_MON_DC4
NET	AsicOut_MONITOR_TRIG_C1_R<1>					LOC = 	L2;	#TRIG_MON_DC5
NET	AsicOut_MONITOR_TRIG_C2_R<1>					LOC = 	K7;	#TRIG_MON_DC6
NET	AsicOut_MONITOR_TRIG_C3_R<1>					LOC = 	N25;	#TRIG_MON_DC7
NET	AsicOut_MONITOR_TRIG_C0_R<2>					LOC = 	AD6;	#TRIG_MON_DC8
NET	AsicOut_MONITOR_TRIG_C1_R<2>					LOC = 	L1;	#TRIG_MON_DC9
NET	AsicOut_MONITOR_TRIG_C2_R<2>					LOC = 	L6;	#TRIG_MON_DC10
NET	AsicOut_MONITOR_TRIG_C3_R<2>					LOC = 	N26;	#TRIG_MON_DC11
NET	AsicOut_MONITOR_TRIG_C0_R<3>					LOC = 	AA10;	#TRIG_MON_DC12
NET	AsicOut_MONITOR_TRIG_C1_R<3>					LOC = 	K1;	#TRIG_MON_DC13
NET	AsicOut_MONITOR_TRIG_C2_R<3>					LOC = 	L8;	#TRIG_MON_DC14
NET	AsicOut_MONITOR_TRIG_C3_R<3>					LOC = 	C24;	#TRIG_MON_DC15
##Wilkinson count rate monitoring
NET	AsicIn_MONITOR_WILK_COUNTER_RESET			LOC = 	AB17;	#TST_CLEAR
NET	AsicIn_MONITOR_WILK_COUNTER_START			LOC = 	AA16;	#TST_START
NET	AsicOut_MONITOR_WILK_COUNTER_C0_R<0>		LOC = 	V11	| PULLDOWN;	#TST_OUT_DC0
NET	AsicOut_MONITOR_WILK_COUNTER_C1_R<0>		LOC = 	W20	| PULLDOWN;	#TST_OUT_DC1
NET	AsicOut_MONITOR_WILK_COUNTER_C2_R<0>		LOC = 	L9		| PULLDOWN;	#TST_OUT_DC2
NET	AsicOut_MONITOR_WILK_COUNTER_C3_R<0>		LOC = 	H21	| PULLDOWN;	#TST_OUT_DC3
NET	AsicOut_MONITOR_WILK_COUNTER_C0_R<1>		LOC = 	Y11	| PULLDOWN;	#TST_OUT_DC4
NET	AsicOut_MONITOR_WILK_COUNTER_C1_R<1>		LOC = 	AB22	| PULLDOWN;	#TST_OUT_DC5
NET	AsicOut_MONITOR_WILK_COUNTER_C2_R<1>		LOC = 	M9		| PULLDOWN;	#TST_OUT_DC6
NET	AsicOut_MONITOR_WILK_COUNTER_C3_R<1>		LOC = 	J20	| PULLDOWN;	#TST_OUT_DC7
NET	AsicOut_MONITOR_WILK_COUNTER_C0_R<2>		LOC = 	AB13	| PULLDOWN;	#TST_OUT_DC8
NET	AsicOut_MONITOR_WILK_COUNTER_C1_R<2>		LOC = 	B24	| PULLDOWN;	#TST_OUT_DC9 # on SCROD revA2, J2_045_AF23 is now J2_045_B24
NET	AsicOut_MONITOR_WILK_COUNTER_C2_R<2>		LOC = 	N9		| PULLDOWN;	#TST_OUT_DC10
NET	AsicOut_MONITOR_WILK_COUNTER_C3_R<2>		LOC = 	K20	| PULLDOWN;	#TST_OUT_DC11
NET	AsicOut_MONITOR_WILK_COUNTER_C0_R<3>		LOC = 	V12	| PULLDOWN;	#TST_OUT_DC12
NET	AsicOut_MONITOR_WILK_COUNTER_C1_R<3>		LOC = 	AF22	| PULLDOWN;	#TST_OUT_DC13
NET	AsicOut_MONITOR_WILK_COUNTER_C2_R<3>		LOC = 	R9		| PULLDOWN;	#TST_OUT_DC14
NET	AsicOut_MONITOR_WILK_COUNTER_C3_R<3>		LOC = 	L21	| PULLDOWN;	#TST_OUT_DC15
## Sampling rate monitoring using SSP_OUT
NET	AsicOut_SAMPLING_TRACK_MODE_C0_R<0>			LOC = 	AC5;	#SSP_OUT_DC0
NET	AsicOut_SAMPLING_TRACK_MODE_C1_R<0>			LOC = 	D3;	#SSP_OUT_DC1
NET	AsicOut_SAMPLING_TRACK_MODE_C2_R<0>			LOC = 	AD3;	#SSP_OUT_DC2
NET	AsicOut_SAMPLING_TRACK_MODE_C3_R<0>			LOC = 	N21;	#SSP_OUT_DC3
NET	AsicOut_SAMPLING_TRACK_MODE_C0_R<1>			LOC = 	R10;	#SSP_OUT_DC4 # on SCROD revA2, J2_007_AF3 is now J2_007_R10
NET	AsicOut_SAMPLING_TRACK_MODE_C1_R<1>			LOC = 	E4;	#SSP_OUT_DC5
NET	AsicOut_SAMPLING_TRACK_MODE_C2_R<1>			LOC = 	H6;	#SSP_OUT_DC6
NET	AsicOut_SAMPLING_TRACK_MODE_C3_R<1>			LOC = 	M21;	#SSP_OUT_DC7
NET	AsicOut_SAMPLING_TRACK_MODE_C0_R<2>			LOC = 	AF4;	#SSP_OUT_DC8
NET	AsicOut_SAMPLING_TRACK_MODE_C1_R<2>			LOC = 	G3;	#SSP_OUT_DC9
NET	AsicOut_SAMPLING_TRACK_MODE_C2_R<2>			LOC = 	K6;	#SSP_OUT_DC10
NET	AsicOut_SAMPLING_TRACK_MODE_C3_R<2>			LOC = 	L20;	#SSP_OUT_DC11
NET	AsicOut_SAMPLING_TRACK_MODE_C0_R<3>			LOC = 	AF5;	#SSP_OUT_DC12
NET	AsicOut_SAMPLING_TRACK_MODE_C1_R<3>			LOC = 	H3;	#SSP_OUT_DC13
NET	AsicOut_SAMPLING_TRACK_MODE_C2_R<3>			LOC = 	K8;	#SSP_OUT_DC14
NET	AsicOut_SAMPLING_TRACK_MODE_C3_R<3>			LOC = 	K19;	#SSP_OUT_DC15
## Trigger output bits from each of the 8 channels of 16 ASICs
NET 	AsicIn_TRIG_ON_RISING_EDGE			LOC = 	AE25; #TRG_SGN
NET	AsicOut_TRIG_OUTPUT_R0_C0_CH<0>	LOC = 	F1;	#TRG_DC0_CH0
NET	AsicOut_TRIG_OUTPUT_R0_C0_CH<1>	LOC = 	D1;	#TRG_DC0_CH1
NET	AsicOut_TRIG_OUTPUT_R0_C0_CH<2>	LOC = 	AA7;	#TRG_DC0_CH2
NET	AsicOut_TRIG_OUTPUT_R0_C0_CH<3>	LOC = 	AB7;	#TRG_DC0_CH3
NET	AsicOut_TRIG_OUTPUT_R0_C0_CH<4>	LOC = 	W10;	#TRG_DC0_CH4
NET	AsicOut_TRIG_OUTPUT_R0_C0_CH<5>	LOC = 	AA11;	#TRG_DC0_CH5
NET	AsicOut_TRIG_OUTPUT_R0_C0_CH<6>	LOC = 	Y12;	#TRG_DC0_CH6
NET	AsicOut_TRIG_OUTPUT_R0_C0_CH<7>	LOC = 	G1;	#TRG_DC0_CH7
NET	AsicOut_TRIG_OUTPUT_R0_C1_CH<0>	LOC = 	F3;	#TRG_DC1_CH0
NET	AsicOut_TRIG_OUTPUT_R0_C1_CH<1>	LOC = 	K3;	#TRG_DC1_CH1
NET	AsicOut_TRIG_OUTPUT_R0_C1_CH<2>	LOC = 	W16;	#TRG_DC1_CH2
NET	AsicOut_TRIG_OUTPUT_R0_C1_CH<3>	LOC = 	AA21;	#TRG_DC1_CH3
NET	AsicOut_TRIG_OUTPUT_R0_C1_CH<4>	LOC = 	N5;	#TRG_DC1_CH4
NET	AsicOut_TRIG_OUTPUT_R0_C1_CH<5>	LOC = 	U3;	#TRG_DC1_CH5
NET	AsicOut_TRIG_OUTPUT_R0_C1_CH<6>	LOC = 	Y3;	#TRG_DC1_CH6
NET	AsicOut_TRIG_OUTPUT_R0_C1_CH<7>	LOC = 	AC4;	#TRG_DC1_CH7
NET	AsicOut_TRIG_OUTPUT_R0_C2_CH<0>	LOC = 	A25;	#TRG_DC2_CH0
NET	AsicOut_TRIG_OUTPUT_R0_C2_CH<1>	LOC = 	C25;	#TRG_DC2_CH1
NET	AsicOut_TRIG_OUTPUT_R0_C2_CH<2>	LOC = 	M8;	#TRG_DC2_CH2
NET	AsicOut_TRIG_OUTPUT_R0_C2_CH<3>	LOC = 	R8;	#TRG_DC2_CH3
NET	AsicOut_TRIG_OUTPUT_R0_C2_CH<4>	LOC = 	F26;	#TRG_DC2_CH4
NET	AsicOut_TRIG_OUTPUT_R0_C2_CH<5>	LOC = 	J26;	#TRG_DC2_CH5
NET	AsicOut_TRIG_OUTPUT_R0_C2_CH<6>	LOC = 	U9;	#TRG_DC2_CH6
NET	AsicOut_TRIG_OUTPUT_R0_C2_CH<7>	LOC = 	K18;	#TRG_DC2_CH7
NET	AsicOut_TRIG_OUTPUT_R0_C3_CH<0>	LOC = 	H24;	#TRG_DC3_CH0
NET	AsicOut_TRIG_OUTPUT_R0_C3_CH<1>	LOC = 	K24;	#TRG_DC3_CH1
NET	AsicOut_TRIG_OUTPUT_R0_C3_CH<2>	LOC = 	F22;	#TRG_DC3_CH2
NET	AsicOut_TRIG_OUTPUT_R0_C3_CH<3>	LOC = 	M19;	#TRG_DC3_CH3
NET	AsicOut_TRIG_OUTPUT_R0_C3_CH<4>	LOC = 	M24;	#TRG_DC3_CH4
NET	AsicOut_TRIG_OUTPUT_R0_C3_CH<5>	LOC = 	P24;	#TRG_DC3_CH5
NET	AsicOut_TRIG_OUTPUT_R0_C3_CH<6>	LOC = 	V24;	#TRG_DC3_CH6
NET	AsicOut_TRIG_OUTPUT_R0_C3_CH<7>	LOC = 	AC23;	#TRG_DC3_CH7
NET	AsicOut_TRIG_OUTPUT_R1_C0_CH<0>	LOC = 	E1;	#TRG_DC4_CH0
NET	AsicOut_TRIG_OUTPUT_R1_C0_CH<1>	LOC = 	B2;	#TRG_DC4_CH1
NET	AsicOut_TRIG_OUTPUT_R1_C0_CH<2>	LOC = 	W7;	#TRG_DC4_CH2
NET	AsicOut_TRIG_OUTPUT_R1_C0_CH<3>	LOC = 	AA8;	#TRG_DC4_CH3
NET	AsicOut_TRIG_OUTPUT_R1_C0_CH<4>	LOC = 	AB11;	#TRG_DC4_CH4
NET	AsicOut_TRIG_OUTPUT_R1_C0_CH<5>	LOC = 	AA13;	#TRG_DC4_CH5
NET	AsicOut_TRIG_OUTPUT_R1_C0_CH<6>	LOC = 	V13;	#TRG_DC4_CH6
NET	AsicOut_TRIG_OUTPUT_R1_C0_CH<7>	LOC = 	G2;	#TRG_DC4_CH7
NET	AsicOut_TRIG_OUTPUT_R1_C1_CH<0>	LOC = 	E3;	#TRG_DC5_CH0
NET	AsicOut_TRIG_OUTPUT_R1_C1_CH<1>	LOC = 	J4;	#TRG_DC5_CH1
NET	AsicOut_TRIG_OUTPUT_R1_C1_CH<2>	LOC = 	AA18;	#TRG_DC5_CH2
NET	AsicOut_TRIG_OUTPUT_R1_C1_CH<3>	LOC = 	Y17;	#TRG_DC5_CH3
NET	AsicOut_TRIG_OUTPUT_R1_C1_CH<4>	LOC = 	N3;	#TRG_DC5_CH4
NET	AsicOut_TRIG_OUTPUT_R1_C1_CH<5>	LOC = 	T3;	#TRG_DC5_CH5
NET	AsicOut_TRIG_OUTPUT_R1_C1_CH<6>	LOC = 	W3;	#TRG_DC5_CH6
NET	AsicOut_TRIG_OUTPUT_R1_C1_CH<7>	LOC = 	AB5;	#TRG_DC5_CH7
NET	AsicOut_TRIG_OUTPUT_R1_C2_CH<0>	LOC = 	B26;	#TRG_DC6_CH0
NET	AsicOut_TRIG_OUTPUT_R1_C2_CH<1>	LOC = 	D26;	#TRG_DC6_CH1
NET	AsicOut_TRIG_OUTPUT_R1_C2_CH<2>	LOC = 	N7;	#TRG_DC6_CH2
NET	AsicOut_TRIG_OUTPUT_R1_C2_CH<3>	LOC = 	T8;	#TRG_DC6_CH3
NET	AsicOut_TRIG_OUTPUT_R1_C2_CH<4>	LOC = 	G26;	#TRG_DC6_CH4
NET	AsicOut_TRIG_OUTPUT_R1_C2_CH<5>	LOC = 	J25;	#TRG_DC6_CH5
NET	AsicOut_TRIG_OUTPUT_R1_C2_CH<6>	LOC = 	R18;	#TRG_DC6_CH6
NET	AsicOut_TRIG_OUTPUT_R1_C2_CH<7>	LOC = 	V21;	#TRG_DC6_CH7
NET	AsicOut_TRIG_OUTPUT_R1_C3_CH<0>	LOC = 	G24;	#TRG_DC7_CH0
NET	AsicOut_TRIG_OUTPUT_R1_C3_CH<1>	LOC = 	J23;	#TRG_DC7_CH1
NET	AsicOut_TRIG_OUTPUT_R1_C3_CH<2>	LOC = 	F24;	#TRG_DC7_CH2
NET	AsicOut_TRIG_OUTPUT_R1_C3_CH<3>	LOC = 	N20;	#TRG_DC7_CH3
NET	AsicOut_TRIG_OUTPUT_R1_C3_CH<4>	LOC = 	K22;	#TRG_DC7_CH4
NET	AsicOut_TRIG_OUTPUT_R1_C3_CH<5>	LOC = 	N23;	#TRG_DC7_CH5
NET	AsicOut_TRIG_OUTPUT_R1_C3_CH<6>	LOC = 	T22;	#TRG_DC7_CH6
NET	AsicOut_TRIG_OUTPUT_R1_C3_CH<7>	LOC = 	AB24;	#TRG_DC7_CH7
NET	AsicOut_TRIG_OUTPUT_R2_C0_CH<0>	LOC = 	C1;	#TRG_DC8_CH0
NET	AsicOut_TRIG_OUTPUT_R2_C0_CH<1>	LOC = 	E2;	#TRG_DC8_CH1
NET	AsicOut_TRIG_OUTPUT_R2_C0_CH<2>	LOC = 	AD5;	#TRG_DC8_CH2
NET	AsicOut_TRIG_OUTPUT_R2_C0_CH<3>	LOC = 	Y9;	#TRG_DC8_CH3
NET	AsicOut_TRIG_OUTPUT_R2_C0_CH<4>	LOC = 	AB9;	#TRG_DC8_CH4
NET	AsicOut_TRIG_OUTPUT_R2_C0_CH<5>	LOC = 	W12;	#TRG_DC8_CH5
NET	AsicOut_TRIG_OUTPUT_R2_C0_CH<6>	LOC = 	AA6;	#TRG_DC8_CH6
NET	AsicOut_TRIG_OUTPUT_R2_C0_CH<7>	LOC = 	H1;	#TRG_DC8_CH7
NET	AsicOut_TRIG_OUTPUT_R2_C1_CH<0>	LOC = 	N2;	#TRG_DC9_CH0
NET	AsicOut_TRIG_OUTPUT_R2_C1_CH<1>	LOC = 	H5;	#TRG_DC9_CH1
NET	AsicOut_TRIG_OUTPUT_R2_C1_CH<2>	LOC = 	Y15;	#TRG_DC9_CH2
NET	AsicOut_TRIG_OUTPUT_R2_C1_CH<3>	LOC = 	U15;	#TRG_DC9_CH3
NET	AsicOut_TRIG_OUTPUT_R2_C1_CH<4>	LOC = 	M3;	#TRG_DC9_CH4
NET	AsicOut_TRIG_OUTPUT_R2_C1_CH<5>	LOC = 	R4;	#TRG_DC9_CH5
NET	AsicOut_TRIG_OUTPUT_R2_C1_CH<6>	LOC = 	V4;	#TRG_DC9_CH6
NET	AsicOut_TRIG_OUTPUT_R2_C1_CH<7>	LOC = 	AB3;	#TRG_DC9_CH7
NET	AsicOut_TRIG_OUTPUT_R2_C2_CH<0>	LOC = 	B25;	#TRG_DC10_CH0
NET	AsicOut_TRIG_OUTPUT_R2_C2_CH<1>	LOC = 	E26;	#TRG_DC10_CH1
NET	AsicOut_TRIG_OUTPUT_R2_C2_CH<2>	LOC = 	P6;	#TRG_DC10_CH2
NET	AsicOut_TRIG_OUTPUT_R2_C2_CH<3>	LOC = 	U8;	#TRG_DC10_CH3
NET	AsicOut_TRIG_OUTPUT_R2_C2_CH<4>	LOC = 	G25;	#TRG_DC10_CH4
NET	AsicOut_TRIG_OUTPUT_R2_C2_CH<5>	LOC = 	K26;	#TRG_DC10_CH5
NET	AsicOut_TRIG_OUTPUT_R2_C2_CH<6>	LOC = 	L25;	#TRG_DC10_CH6
NET	AsicOut_TRIG_OUTPUT_R2_C2_CH<7>	LOC = 	U20;	#TRG_DC10_CH7
NET	AsicOut_TRIG_OUTPUT_R2_C3_CH<0>	LOC = 	F23;	#TRG_DC11_CH0
NET	AsicOut_TRIG_OUTPUT_R2_C3_CH<1>	LOC = 	H22;	#TRG_DC11_CH1
NET	AsicOut_TRIG_OUTPUT_R2_C3_CH<2>	LOC = 	E24;	#TRG_DC11_CH2
NET	AsicOut_TRIG_OUTPUT_R2_C3_CH<3>	LOC = 	P21;	#TRG_DC11_CH3
NET	AsicOut_TRIG_OUTPUT_R2_C3_CH<4>	LOC = 	J22;	#TRG_DC11_CH4
NET	AsicOut_TRIG_OUTPUT_R2_C3_CH<5>	LOC = 	M23;	#TRG_DC11_CH5
NET	AsicOut_TRIG_OUTPUT_R2_C3_CH<6>	LOC = 	T24;	#TRG_DC11_CH6
NET	AsicOut_TRIG_OUTPUT_R2_C3_CH<7>	LOC = 	AA24;	#TRG_DC11_CH7
NET	AsicOut_TRIG_OUTPUT_R3_C0_CH<0>	LOC = 	C2;	#TRG_DC12_CH0
NET	AsicOut_TRIG_OUTPUT_R3_C0_CH<1>	LOC = 	B1;	#TRG_DC12_CH1
NET	AsicOut_TRIG_OUTPUT_R3_C0_CH<2>	LOC = 	AC6;	#TRG_DC12_CH2
NET	AsicOut_TRIG_OUTPUT_R3_C0_CH<3>	LOC = 	W9;	#TRG_DC12_CH3
NET	AsicOut_TRIG_OUTPUT_R3_C0_CH<4>	LOC = 	V10;	#TRG_DC12_CH4
NET	AsicOut_TRIG_OUTPUT_R3_C0_CH<5>	LOC = 	Y13;	#TRG_DC12_CH5
NET	AsicOut_TRIG_OUTPUT_R3_C0_CH<6>	LOC = 	P10;	#TRG_DC12_CH6
NET	AsicOut_TRIG_OUTPUT_R3_C0_CH<7>	LOC = 	J1;	#TRG_DC12_CH7
NET	AsicOut_TRIG_OUTPUT_R3_C1_CH<0>	LOC = 	N1;	#TRG_DC13_CH0
NET	AsicOut_TRIG_OUTPUT_R3_C1_CH<1>	LOC = 	G4;	#TRG_DC13_CH1
NET	AsicOut_TRIG_OUTPUT_R3_C1_CH<2>	LOC = 	V14;	#TRG_DC13_CH2
NET	AsicOut_TRIG_OUTPUT_R3_C1_CH<3>	LOC = 	AA19;	#TRG_DC13_CH3
NET	AsicOut_TRIG_OUTPUT_R3_C1_CH<4>	LOC = 	L3;	#TRG_DC13_CH4
NET	AsicOut_TRIG_OUTPUT_R3_C1_CH<5>	LOC = 	P5;	#TRG_DC13_CH5
NET	AsicOut_TRIG_OUTPUT_R3_C1_CH<6>	LOC = 	U5;	#TRG_DC13_CH6
NET	AsicOut_TRIG_OUTPUT_R3_C1_CH<7>	LOC = 	AA3;	#TRG_DC13_CH7
NET	AsicOut_TRIG_OUTPUT_R3_C2_CH<0>	LOC = 	C26;	#TRG_DC14_CH0
NET	AsicOut_TRIG_OUTPUT_R3_C2_CH<1>	LOC = 	E25;	#TRG_DC14_CH1
NET	AsicOut_TRIG_OUTPUT_R3_C2_CH<2>	LOC = 	R6;	#TRG_DC14_CH2
NET	AsicOut_TRIG_OUTPUT_R3_C2_CH<3>	LOC = 	V7;	#TRG_DC14_CH3
NET	AsicOut_TRIG_OUTPUT_R3_C2_CH<4>	LOC = 	H26;	#TRG_DC14_CH4
NET	AsicOut_TRIG_OUTPUT_R3_C2_CH<5>	LOC = 	L26;	#TRG_DC14_CH5
NET	AsicOut_TRIG_OUTPUT_R3_C2_CH<6>	LOC = 	M26;	#TRG_DC14_CH6
NET	AsicOut_TRIG_OUTPUT_R3_C2_CH<7>	LOC = 	T19;	#TRG_DC14_CH7
NET	AsicOut_TRIG_OUTPUT_R3_C3_CH<0>	LOC = 	E23;	#TRG_DC15_CH0
NET	AsicOut_TRIG_OUTPUT_R3_C3_CH<1>	LOC = 	G23;	#TRG_DC15_CH1
NET	AsicOut_TRIG_OUTPUT_R3_C3_CH<2>	LOC = 	D24;	#TRG_DC15_CH2
NET	AsicOut_TRIG_OUTPUT_R3_C3_CH<3>	LOC = 	R21;	#TRG_DC15_CH3
NET	AsicOut_TRIG_OUTPUT_R3_C3_CH<4>	LOC = 	J24;	#TRG_DC15_CH4
NET	AsicOut_TRIG_OUTPUT_R3_C3_CH<5>	LOC = 	L23;	#TRG_DC15_CH5
NET	AsicOut_TRIG_OUTPUT_R3_C3_CH<6>	LOC = 	R24;	#TRG_DC15_CH6
NET	AsicOut_TRIG_OUTPUT_R3_C3_CH<7>	LOC = 	W24;	#TRG_DC15_CH7

#Pins for connecting up to the TMP112 temperature sensors
NET	TMP_SCL	LOC = M18;
NET	TMP_SDA	LOC = N18	| PULLUP;

#DIAGNOSTIC PINS (LEDS, MONITOR HEADER, etc.)
NET LEDS<0>		LOC = "f18"  | IOSTANDARD = LVCMOS33;
NET LEDS<1>		LOC = "e18"  | IOSTANDARD = LVCMOS33;
NET LEDS<2>		LOC = "g16"  | IOSTANDARD = LVCMOS33;
NET LEDS<3>		LOC = "f17"  | IOSTANDARD = LVCMOS33;
NET LEDS<4>		LOC = "f20"  | IOSTANDARD = LVCMOS33;
NET LEDS<5>		LOC = "e20"  | IOSTANDARD = LVCMOS33;
NET LEDS<6>		LOC = "h17"  | IOSTANDARD = LVCMOS33;
NET LEDS<7>		LOC = "g17"  | IOSTANDARD = LVCMOS33;
NET LEDS<8>		LOC = "c21"  | IOSTANDARD = LVCMOS33;
NET LEDS<9>		LOC = "b21"  | IOSTANDARD = LVCMOS33;
NET LEDS<10>	LOC = "h18"  | IOSTANDARD = LVCMOS33;
NET LEDS<11>	LOC = "h19"  | IOSTANDARD = LVCMOS33;
NET LEDS<12>	LOC = "b22"  | IOSTANDARD = LVCMOS33;
NET LEDS<13>	LOC = "a22"  | IOSTANDARD = LVCMOS33;
NET LEDS<14>	LOC = "g19"  | IOSTANDARD = LVCMOS33;
NET LEDS<15>	LOC = "f19"  | IOSTANDARD = LVCMOS33;
NET MONITOR_INPUTS<0>	LOC = "J2" | IOSTANDARD = LVCMOS25 | PULLUP;
NET MONITOR_OUTPUTS<0>	LOC = "M10" | IOSTANDARD = LVCMOS25;

#Timing constraints
NET map_clocking_and_ftsw_interface/map_FTSW_interface/sig_jclk 								PERIOD = 7.8 ns;
NET map_clocking_and_ftsw_interface/map_FTSW_interface/map_belle2clk/map_pll/sig_clk1  PERIOD = 7.8 ns;
NET map_clocking_and_ftsw_interface/internal_BOARD_CLOCK_250MHz								PERIOD = 4.0 ns;
NET internal_CLOCK_SST																						PERIOD = 47.1 ns;
NET internal_CLOCK_4xSST																					PERIOD = 11.7 ns;
#NET map_clocking_and_ftsw_interface/internal_CLOCK_83kHz											CLOCK_DEDICATED_ROUTE = FALSE;
#NET map_clocking_and_ftsw_interface/internal_CLOCK_80Hz											CLOCK_DEDICATED_ROUTE = FALSE;

#The location of the FTSW receiver PLL seems to only work in specific locations.
#The one below is verified working... others may also work but have not been
#systematically tried.
INST map_clocking_and_ftsw_interface/map_FTSW_interface/map_belle2clk/map_pll/map_pll 	LOC = PLL_ADV_X0Y0;




############FIBEROPTIC PINS AND SIGNALS########################
# UCF generated for xc6slx150t-fgg676-3 by coregen
# modified 2011-06 by kurtis
# modified 2011-07 to 2011-09 by mza
# copied 2011-10-03 from pseudo-data_by_fiber branch
#################################################################################

# 156.25MHz GTP Reference clock contraint
NET "FR/Aurora_data_link/Aurora_RocketIO_GTP_MGT_101_CLOCK_156_MHz_left" TNM_NET = GT_REFCLK;
TIMESPEC TS_Aurora_RocketIO_GTP_MGT_101_CLOCK_156_MHz_left = PERIOD "GT_REFCLK" 156.25 MHz HIGH 50%;
#NET "FR/Aurora_data_link/aurora_module_i/gtp_wrapper_i/REFCLK" TNM_NET = GT_REFCLK;
#TIMESPEC TS_Aurora_CLOCK_156_MHz_left = PERIOD "GT_REFCLK" 156.25 MHz HIGH 50%;

# User Clock Contraint: Value is selected based on the line rate (3.125 Gbps) and lane width (4-Byte)
#NET "internal_Aurora_78MHz_clock" TNM_NET = "TNM_Aurora_78MHz_clock";
#NET "FR/Aurora_data_link/internal_Aurora_78MHz_clock" TNM_NET = "TNM_Aurora_78MHz_clock";
#NET "FR/Aurora_data_link/clock_module_i/clkout0_o" TNM_NET = "TNM_Aurora_78MHz_clock";
#PIN "FR/Aurora_data_link/clock_module_i/user_clk_net_i.O" CLOCK_DEDICATED_ROUTE = TRUE;
#NET "internal_Aurora_78MHz_clock" CLOCK_DEDICATED_ROUTE = TRUE;
NET "FR/Aurora_78MHz_clock" TNM_NET = "TNM_Aurora_78MHz_clock";
TIMESPEC "TS_Aurora_78MHz_clock" = PERIOD "TNM_Aurora_78MHz_clock" 12.8 ns HIGH 50%; # generated by aurora core


# Sync Clock Contraint: Value is selected based on the line rate (3.125 Gbps) and lane width (4-Byte)
NET "FR/Aurora_data_link/sync_clk_i" TNM_NET = "TNM_SYNC_CLK";
TIMESPEC "TS_SYNC_CLK_I" = PERIOD "TNM_SYNC_CLK" 3.2 ns HIGH 50%;

###### No cross clock domain analysis. Domains are not related ############## 
#TIMESPEC "TS_TIG1" = FROM "INIT_CLK" TO "USER_CLK" TIG; 
TIMESPEC "TS_TIG1" = FROM "INIT_CLK" TO "TNM_Aurora_78MHz_clock" TIG; 
INST "FR/Aurora_data_link/aurora_module_i/gtp_wrapper_i/gtp_tile_inst/gtpa1_dual_i" LOC=GTPA1_DUAL_X0Y1;

# GT REFCLK = 156.25 MHz
NET Aurora_RocketIO_GTP_MGT_101_CLOCK_156_MHz_P LOC = B10 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
NET Aurora_RocketIO_GTP_MGT_101_CLOCK_156_MHz_N LOC = A10 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;

# fiber optic transceiver 0
NET FIBER_TRANSCEIVER_0_DISABLE_MODULE                      LOC = "e10" | IOSTANDARD = LVCMOS33; # TX_DIS0 on schematic # on SCROD revA2, TX_DIS0 is connected to e10
NET FIBER_TRANSCEIVER_0_LASER_FAULT_DETECTED_IN_TRANSMITTER LOC = "g12" | IOSTANDARD = LVCMOS33; # TX_FAULT0 on schematic # on SCROD revA2, TX_FAULT0 is connected to g12
NET FIBER_TRANSCEIVER_0_LOSS_OF_SIGNAL_DETECTED_BY_RECEIVER LOC = "b5"  | IOSTANDARD = LVCMOS33; # LOS_0 on schematic
NET FIBER_TRANSCEIVER_0_MODULE_DEFINITION_0_LOW_IF_PRESENT  LOC = "a13" | IOSTANDARD = LVCMOS33; # MOD0_0 on schematic
NET Aurora_RocketIO_GTP_MGT_101_lane0_Receive_P  LOC = "D7";
NET Aurora_RocketIO_GTP_MGT_101_lane0_Receive_N  LOC = "C7";
NET Aurora_RocketIO_GTP_MGT_101_lane0_Transmit_P LOC = "B6";
NET Aurora_RocketIO_GTP_MGT_101_lane0_Transmit_N LOC = "A6";

# fiber optic transceiver 1
NET FIBER_TRANSCEIVER_1_DISABLE_MODULE LOC = "g13" | IOSTANDARD = LVCMOS33; # TX_DIS1 on schematic # on SCROD revA2, TX_DIS1 is connected to g13


#########Pins that are not used right now but may be desired in the future######
#USB Pins
#NET IFCLK      	LOC = "b14"  | IOSTANDARD = LVCMOS33; # on SCROD revA2, IFCLK is connected to b14
#NET CLKOUT     	LOC = "e13"  | IOSTANDARD = LVCMOS33; # on SCROD revA2, CLKOUT is connected to e13
#NET FD<0>			LOC = "f5"   | IOSTANDARD = LVCMOS33;
#NET FD<1>			LOC = "e6"   | IOSTANDARD = LVCMOS33;
#NET FD<2>			LOC = "e5"   | IOSTANDARD = LVCMOS33;
#NET FD<3>			LOC = "h9"   | IOSTANDARD = LVCMOS33;
#NET FD<4>			LOC = "g9"   | IOSTANDARD = LVCMOS33;
#NET FD<5>			LOC = "a3"   | IOSTANDARD = LVCMOS33;
#NET FD<6>			LOC = "a2"   | IOSTANDARD = LVCMOS33;
#NET FD<7>			LOC = "f9"   | IOSTANDARD = LVCMOS33;
#NET FD<8>			LOC = "e8"   | IOSTANDARD = LVCMOS33;
#NET FD<9>			LOC = "d5"   | IOSTANDARD = LVCMOS33;
#NET FD<10>			LOC = "c5"   | IOSTANDARD = LVCMOS33;
#NET FD<11>			LOC = "h10"  | IOSTANDARD = LVCMOS33;
#NET FD<12>			LOC = "g10"  | IOSTANDARD = LVCMOS33;
#NET FD<13>			LOC = "b4"   | IOSTANDARD = LVCMOS33;
#NET FD<14>			LOC = "a4"   | IOSTANDARD = LVCMOS33;
#NET FD<15>			LOC = "f10"  | IOSTANDARD = LVCMOS33;
#NET PA0        	LOC = "g7"   | IOSTANDARD = LVCMOS33;
#NET PA1        	LOC = "h8"   | IOSTANDARD = LVCMOS33;
#NET PA2        	LOC = "g8"   | IOSTANDARD = LVCMOS33;
#NET PA3        	LOC = "f7"   | IOSTANDARD = LVCMOS33;
#NET PA4        	LOC = "f6"   | IOSTANDARD = LVCMOS33;
#NET PA5        	LOC = "c3"   | IOSTANDARD = LVCMOS33;
#NET PA6        	LOC = "b3"   | IOSTANDARD = LVCMOS33;
#NET PA7        	LOC = "g6"   | IOSTANDARD = LVCMOS33;
#NET CTL0       	LOC = "f12"  | IOSTANDARD = LVCMOS33;
#NET CTL1       	LOC = "e12"  | IOSTANDARD = LVCMOS33;
#NET CTL2       	LOC = "j11"  | IOSTANDARD = LVCMOS33;
#NET RDY0       	LOC = "g11"  | IOSTANDARD = LVCMOS33;
#NET RDY1       	LOC = "h12"  | IOSTANDARD = LVCMOS33;
#NET WAKEUP     	LOC = "f11"  | IOSTANDARD = LVCMOS33;
#
##Unsorted?  Not really an ASIC pin but still applicable...
#NET ASIC_CARRIER1_CAL_OUT LOC = "AA15";


## attempt to clean up map errors by constraining the feedback section
#INST "map_ASIC_feedback_and_monitoring*" AREA_GROUP = "pblock_mp_ASC_fdbck_and_mntrng";
#AREA_GROUP "pblock_mp_ASC_fdbck_and_mntrng" RANGE=SLICE_X2Y4:SLICE_X33Y187;
#AREA_GROUP "pblock_mp_ASC_fdbck_and_mntrng" RANGE=DSP48_X0Y1:DSP48_X0Y46;
#AREA_GROUP "pblock_mp_ASC_fdbck_and_mntrng" RANGE=RAMB16_X0Y2:RAMB16_X1Y92;
#AREA_GROUP "pblock_mp_ASC_fdbck_and_mntrng" RANGE=RAMB8_X0Y2:RAMB8_X1Y93;