Pre-Amplifer for Cyclotron radiation Monitoring Application Node
(PACMAN Boards)
Rev : A
Note : Formally Know as PAXMAN

Active Member :  Gary Varner,  Matt Andrew, & Julien Cercillieux
········ Hungry for Dat Electron. ·····•····· ᗤ ᗣᗣᗣᗣ

Introduction :

Required Spec: 
Total Gain :  <20dB(10x)
Bandwidth : >750MHz (Roll off of IRSX)
Min Gain Bandwidth : 7500
Expected Load : 50 Ohm ***
Current draw per channel :  < 35mA*
Noise :   < 20nV | < 20pA**
Number of gain : Unlimited
Requires DC Coupling Input for all stage of application. (No AC Coupling)*****
Package Type :  SOIC8, SOT-6 &
Per Channel Amplifiers Chains Occupation : < 45 mm x 5.5mm
Supply Voltage : Single > 3.3V - 5V or Dual > ±5V  
Number of Layer : <12


* Due to the # channel per square inch
e.g if Vsupply=5V & Isupply= 35mA #Chan = 8*4 =32
Pamp = 5 * 0.0035 * 32 = 0.56 W per board.
** Voltage expected from 1mV therefore needs a low noise as possible.
*** From the HV filter calculation load,  The value series with the appropriately 30k~61k Depending on the load expected.
****Due to the difficulty of DC coupling with gain of 60dB,  It has been changed to AC to the amplifier but with a termination of 50 ohm


Update 18-July-2018:
Going back to
Agilent Function Generators Pulse with 3mV :  [html]
Examination of the stability and the cross-talk between channel
Agilent Funtion Generators Pulse with :  [html]
Top - Amplified signal / Bottom : Input signal

 


Update 15-May-2018:Update 15-May-2018:Update 15-May-2018:
[pcblib]
OSH PARK Stencil came back yesterday.
Top [png]
Bottom [png]
Needed to cut the stencil border edge 
This is the project view that i was seen before I've submitted. [.png]

Update 11-May-2018:
Gereral Tasklist
-Created a Silkscreen Logo Altium Footprint Library used in XRM AMP. [pcblib]
-Image that used to make the logo. [zip]


Update 9-May-2018:
General Tasklist
-Created addition Stencil Frame Component in Altium Footprint Library for OSH Park stencil. [.pcblib]
-Emailed Rayjet/Trotec regarding the warranty still valid. 
-Ordered Stencil from OSH PARK Stencil.  (Top and Bottom .4mm thick Stainless Steel.)  *Get Request Refunds.
-Add function to the plotting.revD script to incorporate edge detection. 
-Updated the main website.  *Added links
-Take a image for Terry about the IDL_18_020 Slightly Over-sized.
-Contact Terry about the getting a quote for this DC board and get a quote from him after some of fix as suggested during mRICH design review. 
-Determine whether the amplifiers were fixed.

Examine the Channel 5. 
I didn't have chance to take the DC values after the first gain resistors been replaced.  I've took the data and it looks better.  

Channels (TOP_Layer)
 Average OUTPUT VOLTAGE (V)**
0.1
 n:1.54376 o:1.430
0.2
 n:1.33 o:1.28
0.3
 n:1.0478 o:1.00
0.4
 n:1.2289 o:1.27
0.5
 n:.78611 o:.73648
0.6
 n:1.05V o:1.09
0.7
 n:1.129 o:1.19
0.8
 n:.75189 o:.813

This did not change the dc Gain seen from the chained output.   suspicious,  I investigated the other side to see if they follow the similar trend.
Channels (Bottom_Layer)
 Average OUTPUT VOLTAGE (V)**
1.8
 1.3395
1.7
 1.18
1.6
 .99678
1.5
 .78678
1.4
 1.2261
1.3
 1.0578
1.2
 1.47
1.1
 .950

So I've check to see if there mistake in the last stage gain amplifiers for channel 5

 Rg Value @ second stage Measured w/ SMT Probe (Expected : 25.5OHM) Rf Value @ second stage Measured w/ SMT Probe (Expected : 499OHM)
Channel_5       
26.8 OHM
 489

Seems to be correct values.   Tomorrow Step will be in investigate whether the First stage rfeedback had the same values and then I'll replace the Ch5 on the top layer to see if this will change the gain.  

Update 8-May-2018:
General Tasklist
-Catch up with plotting data.
-Update the website with new data-plots.
-Show the Ali the how to populate the amplifiers. (Gone over with him the assembly instruction and the part kit to be sure on everything were included.)

Schedule for this week :
Attempt to do at least 3 Boards in total.  

Update 7-May-2018:
There seems to be my previous were correct.

The gain resistors where not the same for the channel 5 & channel 8
As a comparison to what is populated near by,  I've also depopulated the Channel 4

Rg Value @ First stage Measured w/ SMT Probe
Channel 4 (Expected range)
 20 OHM
Channel 5 (Suspected wrong component/ value)
 22.7-23.3 OHM
Channel 8 (Suspected wrong component/ value)
 22.4-ish* OHM

*This component  few off and couldn't recover to see the range.

Another interesting thing I found interesting was that there is a Observation I saw in the oscillatory state of the amplifiers.   E3613A power supply current draw jumps from typical range when the oscillation are taking place.

.530-.531 A (Non Oscillatory condition)
.557-.558 A (Oscillation Current Draw)
   
But when I place a probe on the state when they are oscillating.  it stops more non oscillatory condition state.  [html] (Placeholder) => [html] (Placeholder)

There is Urgent need for ordering parts digikey so need to make a part list.

RMCF0402FT20R0TR-ND - RES 20 OHM 1% 1/16W 0402 - $0.00191 - 10,000 - $19.06
LTC6240HVIS5#TRMPBFCT-ND - IC OPAMP GP 18MHZ RRO TSOT23-5 - 2.23990 - 100 - $223.99
296-20952-1-ND - IC I/O EXPANDER I2C 4B 8VSSOP - 1.19100 - 20 - $23.82

Sending this to Jan.

Update 6-May-2018:
Minor Task
 - Ordered More Solder-paste
 - Start list of part for the next Requisition Form for Digikey. 
    1) Buffer : LT6240 - x20?
    2) 47nF X7R - 10,000 Reels?  (Still need to determine if we need this.)
    3) Temperature Sensors - STT
    4) 12k & 7.5k Ohm Resistors 3x12 = QTY: 36
    5) 20 OHM?
- Set up a gerber file output for the Stencil TOP & Bottom (Didn't have time today).  I might want this for the if we want to further increase our production of this board. Ask Matt and Gary for whether if this is still a option.

Current Task
- Figure out why there is oscillation present on the Amplifiers Channel 5.  
- Figure out the source of the weird wiggle at the last week plots. 

Figuring out the Origin of the wiggle. 
The issue seems to be when I've had this connected to the signal generators.   These are without and without the function generators connected to the input.  [html] (Placeholder)
I suspect as such but now there is definitive proof that even if the output is disabled. it is inductively coupling the to the output.  
Most like situation are that relay switches the output when it enabled but when disabled,  they are terminated to 50ohm. 
but due to the near to the source or not properly terminated,  they are radiating this function. 

However,  I am see Ringing occasionally when the amplifiers on This could be indicative of a instability of these amplifiers.  [html] (Placeholder)

It's in the reference dataset on the .csv files.
Examine the Oscillation of the Second stage. 
Changed Note on Board #3
Minor Changes
Top Channel 5, 8 (AKA 0.5 & 0.8)
CAH => N/A to 0.1uF X7F (These were supposed capacitors near output of the first stage VAP buffer.)*
*Typically They are populated with 47nF
TOP&BOTTOM Channel 1-8 (0.1-0.8&1.1-1.8)
CAK => N/A to 200pF NP0 (These are Additional decoupling capacitors near the amplifiers)
TOP Channel 5,6
CAL => ()

Observation  Note
1) None of the CAG which are the VPEDB going to the negative side of the amplifier are populated at the bottom. 
So we can rule out the issue with the loading the unity gain buffer the capacitors with buffer.
2) When the 50 load are not connected,  we are at the output of the each amplifier,   they are initially all output are oscillating when the power is applied but eventually will stop oscillating then the amplfier seen to be stable.
3) On the Bottom side CAH is not populated except Channel 3.
4) There are difference in the DC voltage at the output of amplifiers.  Currently The Each of the Buffer output is the following VAP = 1.26V, VAN = 1.24V & VBP = 1.24V
Channels (TOP_Layer)
 Average OUTPUT VOLTAGE (V)**
0.1
 1.430
0.2
 1.28
0.3
 1.00
0.4
 1.27
0.5
 .73648***
0.6
 1.09
0.7
 1.19
0.8
 .813***

 ** Measured with the oscilloscope with no load present.  Also,  there are no source at the input.  This pure DC analysis of the amplifier's output.
*** Something is wrong with this channel.   And this was the channel that was oscillating when the 50OHM load were present.

After Over-serving this condition.  The Channel 5 & 8's amplifiers are not either functioning properly.  due to the DC gain is wrong.  Also this where the channel that were causing issue before therefore,   It might be worth the time to investigate the issue.

I've also checked to see what voltage were at the supply voltage.
All are 4.02±0.01V Thru out the 0.1~0.8 Channel.

If there is a difference voltage seen by the positive and negative terminal we might be seen that voltage input difference for the second stage...  

Channel
(TOP_Layer)
 V- (Volt)
 V+ (Volt)*x5 ±0.005V **** (V+ - V-) (Volt)
0.1
 1.2681
 1.26 0.0081
0.2
 1.2697
 1.26
 0.0097
0.3
 1.2690
 1.26
 0.009
0.4
 1.2698
 1.26
 0.0098
0.5
 1.2689
 1.26
 0.0089
0.6
 1.2701
 1.26
 0.0101
0.7
 1.2706
 1.26
 0.0106
0.8
 1.2709
 1.26
 0.0109

**** This is a VPED VOLTAGE
*x5 This coming from the output of first stage.

As you can see there is a 0.3 and 0.5 should roughly same difference in voltage but getting a huge difference in output .73643 ~/~ 1.00  
also like to mention that the 0.2 and 0.4 should be roughly the same since it's seen the same difference at the terminal.  And we are seen expected result at the output 1.28 vs 1.27 
But as you can see the higher the difference the low the output voltage.  As expected since this is inverting amplifiers. So the Channel 8 Seems to be working just fine. 

But this does shows that that each channel will have the difference in voltage due to the VPED trace width were not carefully chosen.    
If I do a quick math on the resistance expect between each traces.     ******
Trace Width : 0.203mm
Length Wire : 0.949mm + 3.044mm + 0.716mm = 4.70900 millimeters
Copper pour thickness :  0.0178mm (0.5 oz)
Copper p :  1.72 x 10-8 Ω.m * 1000 = 1.72 x 10-5 Ω.mm
1/7*Total_R = pL/A = 1.72 x 10-5 Ω.mm * (4.70900 millimeters/(0.0178mm * 0.203mm0.203mm)) = 0.02241512149 OHM
Total_R = 0.15690585044 OHM

It's Barely nothing.

******Wrong Conclusion.  It's not the VPED.  It's the output from the first stage are causing the main problem....
I've taken a multimeter to probe the issue and  found this striking result.

Channels (TOP_Layer)
 Average VPED1 (V)
0.1
 1.2698
0.2
 1.2712
0.3
 1.2733
0.4
 1.2723
0.5
 1.2753
0.6
 1.2731
0.7
 1.2729
0.8
 1.2746

So this offset are coming from the VPED but the mistake in the populating the gain resistors for the first stage.  

My conclusion from these data,  The Channel 5 and 8 has either somthing wrong at the gain resistors @ first stage.   This should be 20 OHM for the all first stage but i'll confirm this tomorrow morning.
But I suspect this to be 25.5 OHM.  since when populating this board i had reel of 25.5OHM from the single channel board and in the 20 OHM for the multchannel boards were not purchased in reel yet.

Update 5-May-2018:
XRMAMP REV B Assembly Guide : [pdf]
Note : this may subject to change.

Update 1-May-2018:
Examination of the stability and the cross-talk between channel
Agilent Funtion Generators Pulse with :  [html]

Update 15-April-2018:
Last week,  we discussed the following
       -Collect data with averaging enable to reduce noise contribution from measurement error.
       -Order more boards to complete 3 modules worth of amplifiers

 Avtech Pulse (Amplitude : 10mV) With Averaging Signal : 64
 Agilent Pulse with :  [html]  [image]

Task still need to be done.
        -Use the network analyzer to create a bode plot. (I might need a peters help.)
        -Populate a full board to see if there is a effect on the cross talk.  (Maybe this week get started)

Still need to be done

Update 9-April-2018:
Rev B Testing Notes
Each resulting plots are divided into three waveform.  First one been the original Signal,  Second from probing the output from the first amplifiers stage,  and the last waveform are from the last stage of the amplifiers.

All of the current data were taken from the Key-sight MZOX6004A Oscilloscope and all of the data can be downloaded from here. [zip]

To determine the functionality of the amplifiers,  we first injected the pulse signal from a Function Generators. Then after we determined that the stability and functionality of the amplifiers chains.  The measurement where all taken with passive probes (500MHz - 1MOhm ) to prevent the loading the circuits.

Pulse (Amplitude : 10mV)
 Agilent Pulser with 120ns 90% duty cycle With Bandwidth Limited = 200MHz :  [html]  [image]
Running the FFT with pulse [html]  [image]
Agilent Pulser with 120ns 10% duty cycle With No Bandwidth Limits [html]  [image]
FFT Results with Pulse [html]  [image]

##################################
 Calculated Data
##################################

total Gain expected from the amplfier chains :  380
Interm of dB  : 51.5956719323
pulse amplitudes expected : 0.01 V
Expected pulse height at the last stage 3.8
Sampling interval :  0.5 ns
Medium Values :  0.94639120996
1.24764643238 0.64513598755
average High level and low level :  1.39827404358 0.494508376345
averaged pulsed heights :  0.903765667233
true gain:  90.3765667233
true gain in db:  39.1211167816 dB
comparison between the expected and result (dV):  2.89623433277 mV

The next step where to determine if the amplifiers chains where stable at the higher frequency.   We used the Agilent signal generators for our sources

Sine Waves (Attenuated to desired Amplitude : 10mV )
Using Signal Generators to inject Sine wave 200MHz signal into the Amplifier Chains [html]  [image]
Resulting FFT Result from 200Mhz Sine waves [html]  [image]
Using Signal Generators to inject Sine wave 500MHz signal into the Amplifier Chains [html]  [image]
Resulting FFT Result from 500MHz Sine wave [html]  [image]

The final characterization are done with injecting a the fast rising time pulse from the AVTECH pulsor.

Fast Rise Time Pulse (Attenuated to desired Amplitude : 10mV)
 Avtech_Pulse_Input_nolimit.html [html]  [image]
Avtech_Pulse_Input_nolimitfft.html [html]  [image]

There is still need to determine the rise time for each pulse.  Using the curse on the scope shows that output rising edge is 1.4ns ~1.6ns

Current tasks are to set this amplifiers with

Python Script to generate these file are posted here [py]

Update 4-April-2018:
Rev B Testing Notes
Removed the 1nF from the feedback path for both amplifiers chains.

Found an missing feedback resistors on the second

Input @ 50Ohm Vias
laser-diode-diff24.csv [csv]

First stage  dY = 175.00mV, dX = 31 ns, dx period =  200ns
laser-diode-diff22.csv [csv]
laser-diode-diff23.csv [csv]

Second stage Measured dY = 850mV, dX = 28ns (returned to base) Expected width 180 ns
laserdidoee-diff21.csv [csv]

plotting script :  [py][plt] 


Update 3-April-2018:
Comment on the Rev B
Placed the regulator's output backwards.
replaced with another boards reggie 
VPED - GND : 530KOHM

Instead of Reggie VPED will be provided by 33220A Power Supply

So far on the scope view we are not seen any signal. 

Here is updated Schedules:
Boards Arriving ~ March 29 2018
Populating boards Top ~ March 30 2018 [Completed]
First result! ~ April 3,2018  April 11 2018
    - Oscilloscope/ Signal IN/OUT test
    - Bandwidth with network analyzer

Update 2-April-2018:
Comment about the Rev B. 
forgot to Didn't have pull up on regulators. So the current boards has Reg Disable flowing.
When Powered with reg enable.   0.055A on the E3613A When the reg is disabled,  ~7 mA

Oscilloscope : InfiniiVision MSOX6004A
modifying the ERF840pos with a 50ohm termination,  The active probe will be used take initial data.   

Signal is generated by Agilent 33220A with 10mVpp and frequency of the 20MHz Pulse

Manually need to inject the Vped. The Reggie were populated with output voltage of 1.21V
and soldered on the VPED nets. 

Noise Level Seen by the scope : 20mV
Image of the signal at the inputs of the amplifiers (defaultlabeled2.csv)

Currently The buffer vped voltage is not functioning. 
Vped1A Voltage: 0.01V
Vped1B Voltage: 0.4 V
Vped2B Voltage : 0.02V  

Linear Injectors Boards Rev B
Modified Schematic :  [sch]
Comment : The boards required Additional termination resistors.
Added additional test pads to the boards to make them easier to probe with active probe



Update 29-Mar-2018:
Comment on Populating Rev B
The Boards #2 will be Populated. Starting from the Bottom.  
Bottom

Injectors boards Pin 36 - > Rev B Pin 36
Injectors boards Pin 35 - > Rev B Pin 35
So the Channel will be populated are ASIC 1.8 & 0.1
Regulators for VCC1 will be Populated.
Changed in Values during population the boards
10nH to 1uH =>Part # : 445-3163-1-ND
10nF to 47uH =>Part # : 445-7754-1-ND0402 47nF -> 0603 47nF
Note : Time Constant : f = 1/2*pi*sqrt(LC) =  1/(2*pi*sqrt((47E-6)*1E-6)) = 23215.1344209 Hz
0402 499OHM -> 0402 470OHM (RHM470CDT-ND)  New Gain 1 + 470/49.9 ~ 10 ish
0402 4.99OHM -> 0402 2OHM
0402 647OHM  -> 0402 649OHM (P649LCT-ND) (Order More 647 and 976 OHM 0402)
0603 0OHM -> 0603 1OHM
3PM -> 9PM = 6 hours process Solderpaste

Reflowed twice*
Once with LF2-MEDIUM profile (*Did not reflow. Looked Dried out.)
During the removal,  One of the HV capacitors came off (47uF) -> Needed to be Reinstalled
Twice with PB-MEDIUM profile  (Finally Reflows.  Looked tinned)
Check for shorts : 0.59 MOHM Between RAW-GND
During the Reflow,  One of the 0402 25.5 Ohm flow off. Attached to input pin.   

Top
Required Making a Boards Support so the component on the bottom of the boards does not interfere for the boards to be flush against the stencil.
3d printing component [solidwork file][STL]
(side note : If you upload the stl to the octoprint,  The printer sometime gets the orinationation incorrect)
Realized that by placing the connectors,  board are not flush against the stencil.  Connectors needs to be removed.

Checked if the female 80pin ERF8 Vertical had the same as the Male.  Update :  Yes "D" = 34.8 for both connector

Mechanical Connection between the Interconnections looks fine.  Tested with the #1 (Bad Board) and the connection showed no signed of additional force for mating.

Rev B Boards Image

I was able to remove the connectors but,  after realizing the difficulty, and to reduce the danging the dielectric material from thermal,  The best course of action maybe to
remake the top layer of stencil with the connectors as a cut out.

New Top Stencil : [PDF]  (Need to be reprinted)

Update 28-Mar-2018:
Rev B Boards Image
Image above shows the new revision returned from the fab house.

Continuity Checks on the Rev B Result. (W/ Fluke 287 [ds] )
Raw - GND
#1 :  0.011Ω (Bad Boards)
#2 :  2MΩ
#3 :  1.9MΩ
VCC1 - GND
#1 :  2.9MΩ
#2 :  51MΩ
#3 :  OL
VCC17 - GND
#1 :  2.1MΩ
#2 :  29MΩ
#3 :  63MΩ

Started Populating Boards Starting from the top to bottom.
For Boards #2 & #3...

Rev B BOM [xls]

The boards will be populated with 2 channel

Update 27-Mar-2018 :
Delayed in the shipping the boards.
Tracking Number : 9400110200830880888817

Here is updated Schedules:
Boards Arriving ~ March 29 2018
Populating boards Top ~ March 30 2018
First result! ~ April 3 2018
    - Oscilloscope/ Signal IN/OUT test
    - Bandwidth with network analyzer

Made Assembly Preparation :
Assembly Instruction Bottom : [PDF]
Assembly Instruction Top : [PDF]


Update 26-Mar-2018 :
- Corrected the Schematics for the THS4303 version boards.  (THS4303 - Altium Library : PAC)
-

Update 20-Mar-2018 :
Planning Schedules
Board Ordered - March 14th 2018
Top and Bottom Stencil - March 20 2018
Boards Arriving ~ March 28 2018
Populating boards Top ~ March 30 2018
First result! ~ April 3 2018
    - Oscilloscope/ Signal IN/OUT test
    - Bandwidth with network analyzer

PAXMAN Rev B (Layout G) [Final]
Stencil Generated Top and Bottom : [svg]

Mechanical Drawing
Flanged Plates Drawing Draft : [pdf] [.drw]

Update 14-Mar-2018 :
PAXMAN Rev B (Layout G) [Final]
Altium Layout/Schematics
Completed Layout pdf : [pdf]
Gerber : [zip]
pcb : [zip]
comment :

Update 28-Feb-2018 :
PAXMAN Rev B (Layout G)
Altium Layout/Schematics
Completed Layout pdf : [pdf]
Gerber : [zip]
pcb : [zip]
comment : Change the smallest annual ring to 6mil => 8mill :
reduced the number of vias in the design.  : 
Cleaned the routing analog line Rerouted the HV Lines : 

Update 27-Feb-2018 :
PAXMAN Rev B (Layout G)
Altium Layout/Schematics
Completed Layout pdf : [pdf]
Gerber : [zip]
pcb : [zip]
comment : Change the smallest annual ring to 6mil => 8mill :
reduced the number of vias in the design.  : 
Cleaned the routing analog line Rerouted the HV Lines : 

Update 2-Feb-2018 :
PAXMAN Rev A (Layout G)
Altium Layout/Schematics
Completed Layout pdf : [pdf]
Gerber : [zip]
pcb : [zip] (altium)
comment :
Starting the Rev B Version of the Boards (8 Layer), Wrote a script to upload the pcb file (Total file size around 200mb) Minor change :

Update 1-Feb-2018 :
PAXMAN Rev A (Layout G)
Altium Layout/Schematics
Completed Layout [pdf]
Gerber [zip]
comment : Modified planes, runed DRC, Fixed missing drill file, Fixed missing Board Outline, Wrote a managing script to update webpage, Place a internal plane cutout for both side of the HV & HVreturn
There might be an issue with the slots on the existing board for the OSH Park [web]

Download link to the OSH park's rule set for altium [web]

fixed the rounting on the amp_en, reg_dis, SDA, SCL, and VPED<1-4> on LDC side
Minor change

Update 31-Jan-2018 :
PAXMAN (Layout F)
Altium Layout/Schematics
Completed Layout [pdf]
Gerber [zip]

Update 05-November-2017 :
PAXMAN
Altium Layout/Schematics
/Routing Placement/ Schematic [pdf]

Status : Changed the routing to reflect the changed decal.  however,  until the buffer are no long ocilating in our test channel we are holding it off.

DCPAXMAN
Altium Layout/Schematics
Preliminary Image From First Stage [png]
Note :  Vpedan = 0.89V, Vpedap = 0.92V
Signal Generators setting [png]
10mVpp, DC offset : 1.25
 Preliminary Image From Second Stage
Note :  Vpedb = 2.4V (Oscillating/crap still similar)

Status : Correcting the Vped Values : By placing a  22uF @ the output of the buffer I've managed to stop the oscillation.   however,  the amplifier are no long getting the signal.

Update 02-November-2017 :
PAXMAN
Altium Layout/Schematics
/Routing Placement/ Schematic [pdf]

Status : Made the correction to the decal
Changed

DCPAXMAN
Altium Layout/Schematics
Rail Correction Image [png]
Preliminary Image From First Stage [png]
Note :  Vpedan = 1.6V, Vpedap = 1.16V
Preliminary Image From Second Stage [png]
Note :  Vpedb = 2.4V
 Preliminary Image From Last Stage [png]

Status : Correcting the Vped Values : 1.25V.  Mistake were found to be the cause of the voltage drop on the vcc. The decal were fixed on the multi-channels

Update 01-November-2017 :
Created Part Kits for the Dual Channel Paxman
Note : Some parts where changed due to lack of the correct values in stock. 
RAC, RAB - 4.99Ohm -> 8.1Ohm
RBU7, RBU6, RBU0, RBU9 - 4.99Ohm -> 8.1Ohm
RAJ - 54.9Ohm -> 49.9Ohm
IMON needed to be tied to GND for the operation voltage to 3.1V  (Before Tied to gnd : 0.9V)

Update 31-October-2017 :
PAXMAN
Altium Layout/Schematics
/Routing Placement/ Schematic [pdf]
One minute Speech Slides [pptx][pdf]

Status :  Fan-out of the ERM8 connectors are completed.
Started routing the routing inner layers. [completed]

Update 30-October-2017 :
PAXMAN
Altium Layout/Schematics
/Routing Placement/ Schematic [pdf]

Status :  Fan-out of the ERM8 connectors are completed.
Started routing the routing inner layers.
Still need to fix the connectors orientation as discover and current been fixed.
Still having issue with rules not forcing and causing the difficulty with the routing round corners.

Update 27-October-2017 :
PAXMAN
Altium Layout/Schematics
/Routing Placement/ Schematic [pdf]

Update 26-October-2017 :
PAXMAN
Altium Layout/Schematics
/Routing Placement/ Schematic [pdf]

Comment :  Added addition of MMCX HV input. (MMCX are rated fro 170V)
Moved the all of the amplifier chains to medial (2mm).
Moved the to the side of the boards.    Added the Input filter caps 

Status : Collecting Parts / Waiting for Parts

Update 25-October-2017 :
PAXMAN
Altium Layout/Schematics
/Routing Placement/ Schematic [pdf]
 
Comment : Layers thickness are adjusted to attain the correct impedance.
See link with detail [txt]
Correction were made to already routed trace width to 11mil -> 15.5mils (Top/Bottom Layers)
Corrected the pcb rules []
 
DCPAXMAN
Board Image Top [jpg]
Board Image Bottom [jpg]
Stencil TOP [PDF]
Stencil BOT [PDF]

Comment :  Current status are been assembled.

Update 24-October-2017 :
Comment :  Tested the presence of the all of the internal copper layers

Update 23-October-2017 :
PAXMAN
Altium Layout/Schematics
Layout A
Placement/ Schematic [pdf]

Layout B
Placement/ Schematic [pdf]
Step Model of short board [step] ,
Board Outline [GCODE] , [stl]
Channel Routing [png] [svg]
Comment : The Board are 15mm Shorter, New RF shield,
Status : Building Rules for all nets (Net Class Member specified are digital, RF, POWER, & HV)
Excepted to be done with routing this week.  If there is no trouble. (Expected Design Review W/Routing: October 26, 2017)
Q1 : Cutout for the HV routing?  It's only 75V

Update 22-October-2017 :
PAXMAN
Altium Layout/Schematics
Placement/ Schematic [pdf]

Update 16-October-2017 :
PAXMAN
Altium Layout/Schematics
Schamatic [pdf]
Signal Routing Internal,  Strip Asym :  Z0 : 48.145 Ohms
Layer # : 8 (1.Top,2.GND,3.PWR,4,VPED/I2C/HV/Other ... 8.Bottom)
DE Material : FR405 [Ask if you want the ds]
Comment :   Mux Still there (ADG1213 [ds] or  DG4053A [ds]) with external output (SMA) [ds]
Removed LT3066 and replaced with LT1963A Vin = 5, Vout = 4V
Total Thickness ~70mils [.png]

 Update 15-October-2017 :
PAXMAN
Altium Layout/Schematics
Schamatic [pdf]
Pick-n-Place File/xls [pck]/[xls] (pck are still not outputted correct.)
Layer # : 8 (1.Top,2.GND,3.PWR,4,VPED/I2C/HV/Other ... 8.Bottom)
DE Material : FR405 [Ask if you want the ds]
Comment :  Added Mux (ADG1213 [ds] or  DG4053A [ds]) with external output (SMA) [ds]
Found RF Shield
Covering the entire top : [ds] (Requires the change of the board outline to fit the power connectors. See suggested board dimension [.png])
Covering the Single ASIC's preamplifier Chains :  [ds] (Undetermined whether boards need to changes.)
 
DCPAXMAN
Part List/BOM : [xls]
Comment : Were sent out on October 14, 2017 - 5 day turn around - 4 layers - PCBU - Qty : 5

Update 12-October-2017 :
DCPAXMAN
Altium Layout/Schematics
Overview [pdf]
 PDF Output [pdf]
Altium Project File [.zip] 
Gerber File [.zip]
Instant Quote from PCBU [.png]
Comment :  Still need to pass error... : 500 error....
4 layers boards,  OSH Park ,  Material : FR408
SuperKEKBLogo Silkscreen [.zip]

Update 06-October-2017 :
DCPAXMAN
Altium Layout/Schematics
Overview [pdf]
 PDF Output [pdf]
Altium Project File [.zip] 
Gerber File [.zip]
Instant Quote from PCBU [.png]
Comment :  Still need to pass error... : 500 error....
4 layers boards,  OSH Park ,  Material : FR408

Update 04-October-2017 :
DCPAXMAN
Altium Layout/Schematics
Overview [pdf]
 PDF Output [pdf]
Altium Project File [.zip] 
Gerber File [.zip]
Instant Quote from PCBU [.png]
Comment :  Still need to pass error... : 500 error....
4 layers boards,  OSH Park ,  Material : FR408

Update 03-October-2017 :
DCPAXMAN
Altium Layout/Schematics
Overview [pdf]
 PDF Output [pdf]
Altium Project File [.zip] 
Gerber File [.zip]
Instant Quote from PCBU [.png]
Comment :  Still need to pass error... : 500 error....
4 layers boards,  OSH Park ,  Material : FR408

Update 02-October-2017 :
DCPAXMAN
Altium Layout/Schematics
Overview [pdf]
 PDF Output [pdf]
Altium Project File [.zip] 
Gerber File [.zip]
Comment :  Still need to pass error... : 500 error....
4 layers boards,  OSH Park ,  Material : FR408


 Update 28-September-2017 :
Altium Layout/Schematics
PDF Output [pdf]
Altium Project File [.zip] 
Comment :  Still need to pass error...
4 layers boards,  OSH Park ,  Material : FR408

Simulation
Schematic View
TransientAC AnalysisNoise Analysis
Lt-spice Simulation with V17 [zip]
- Requires Single Vped = 1.25V
- Removed All Resistors dividers
- Output : 309mV/4mV =  77V/V @ IRSX
- LMH6629x3 [ds] : Amplifier: 10x, 10x, Carries :  -10x
- Vped's Noise Introduced ~ 2mV (2mV More Kill our output efficiency)
- Added  Ability to switch on the switch.
- Needed to Added the termination between the PAX and CARRIER
- Current Sub-Version : 5_E 

Update 12-September-2017 :
Schematic View
TransientAC AnalysisNoise Analysis
Lt-spice Simulation with V17 [zip]
- Requires Single Vped = 1.25V
- Removed All Resistors dividers
- Output : 309mV/4mV =  77V/V @ IRSX
- LMH6629x3 [ds] : Amplifier: 10x, 10x, Carries :  -10x
- Vped's Noise Introduced ~ 2mV (2mV More Kill our output efficiency)

List of Changes
Added the Newly found feedback trace2plane capacitance (Labeled as {Ctp})
Added the decoupling cap to the VPED {Cby} with ESR of 0.2ohm
Added Back the resistors to the R6,R13,R8,R12 (Value 5R)
Changed the Series Resistance from 5 to 0 (R53 I don't know how i missed this)
Vped4 Values were changed to the 0V
Change the Label on the LTschematic to reflect the Altium Schematic

Comment :  


Update 28-August-2017 :
Schematic View
TransientAC AnalysisNoise Analysis
Lt-spice Simulation with V16 [.zip]
- Requires Single Vped = 1.25V
- Removed All Resistors dividers
- Output : 309mV/4mV =  77V/V @ IRSX
- LMH6629x3 [ds] : Amplifier: 10x, 10x, Carries :  -10x
- Vped's Noise Introduced ~ 2mV (2mV More Kill our output efficiency)
- Noise's FFT [img],
- Test Signal's FFT [img]  
Comment :  
Transients Analysis:
Tranimpedence Values => Stage 1 : 151Ω, Stage 1+2 :  1347.62 Ω, Stage 1+2+3: 1761.1Ω
Gain Stage =>  Stage 1 : 14.1683V/V, Stage 2 :  17.710V/V, Stage 3 :  2.32436V/V
x0: PP(v(vinp1))=0.00795782 V FROM 1.25831e-008 TO 1.81166e-008
x1: PP(v(vout1))=0.0406638 V FROM 1.25831e-008 TO 1.81166e-008
x2: PP(v(vout2))=0.312424 V FROM 1.25831e-008 TO 1.81166e-008
x3: PP(v(vout3))=0.408284 V FROM 1.25831e-008 TO 1.81166e-008
x4: PP(i(i4))=0.000114774 V FROM 1.25831e-008 TO 1.81166e-008
pwrch1: PP(v(vcc)*(i(r8)+i(r6)))=0.00559245 FROM 0 TO 7.86065e-008
pwrch32: PP(v(vcc)*(i(r8)+i(r6))*32)=0.178958 FROM 0 TO 7.86065e-008
pwrch128: PP(v(vcc)*(i(r8)+i(r6))*128)=0.715834 FROM 0 TO 7.86065e-008
AC Analysis :
tmp: MAX(mag(v(vout1)))=(-66.5646dB,0°) FROM 1e+007 TO 1e+010
tmp1: MAX(mag(v(vout2)))=(-46.0693dB,0°) FROM 1e+007 TO 1e+010
tmp2: MAX(mag(v(vout3)))=(-92.3511dB,0°) FROM 1e+007 TO 1e+010
tmp4: MAX(mag(v(voutsta)/v(in5+,in5-)))=(-24.0549dB,0°) FROM 1e+007 TO 1e+010
bw1=9.30522e+009 FROM 6.94782e+008 TO 1e+010
bw2=9.55934e+009 FROM 4.40656e+008 TO 1e+010
bw3=9.07876e+009 FROM 9.21239e+008 TO 1e+010
bw4=8.4895e+009 FROM 1.5105e+009 TO 1e+010

 Update 23-August-2017 :
Schematic View
TransientAC AnalysisNoise Analysis
Lt-spice Simulation with V15 [.zip]
- Requires Single Vped = 1.25V
- Removed All Resistors dividers
- Output : 309mV/4mV =  77V/V @ IRSX
- LMH6629x3 [ds] : Amplifier: 10x, 10x, Carries :  -10x
- Vped's Noise Introduced ~ 2mV (2mV More Kill our output efficiency)
Comment :

Update 14-August-2017 :
Schematic View
TransientAC AnalysisNoise Analysis
Lt-spice Simulation with V14 [.zip]
- Correction After Last meeting with Luca and Matt
- Requires Vped = 1.25V, DC Coupled Input.
- Output : 309mV/4mV =  77V/V @ IRSX
- LMH6629x3 [ds] : Amplifier: 10x, 10x, Carries :  -10x
- Vped's Noise ~ 1mV (More than this will kill the output amplification)
- Cb were removed from the feedback.
Comment :



Update 2-August-2017 :

Schematic View
TransientAC AnalysisNoise Analysis
Lt-spice Simulation with V11 [.zip]
- Correction V7
- Cb were removed from the feedback.
-  LMH6703 & two LMH6629 [ds] :  1st  = 1x, 2nd = 10x , 3rd = -10x
Comment :


Schematic View
TransientAC AnalysisNoise Analysis
Lt-spice Simulation with V12 [.zip]
- Correction V8
- Cb were removed from the feedback.
- AD8000 [ds] & Twin LMH6222 [ds]: 1st = 1x,  2nd = 10x, & 3rd = -10x
- Supply Rail 5V
Comment :

Update 1-August-2017 :
We will perform comparison with the initial amplifier choice due to the our roof of our current limit and revising the amplifier with High current maybe the choice we may need to make.

1:30pm Local Meeting
Attendance - Gary,  Luca, & Julien
Gone over the XRM Tasklist [Link]

Wirebond Boards
Confirm when the wire-bond boards from terry :   Afterward,  I've talked to Jan if she can email terry about the progress on the 12 board order.

Amplifers Board
Confirm V9.B with AD8045tranimpedence amplifiers are correctly setup.  :  Correction,  Found that AD8000 is the CFA and not AD8045. that was V8 I was recalling the previous model.  that was my mistake.
Suggested to remove the Transimpedence amplifiers DC bias pedestal at the output.  
1st Amplification stage has issue 0.5mV,  and final stage is a sign of oscillation instability.

Interconnect Board (Interconnect Boards Rev B)
There was a discussion regarding the revising this design soon. : Emailed Matt to ask him to send the layout.

Firmware/Readout
Q: topic on reusing the readout from the
A: No,  register configuration is same,  trigger and mashing are same as well.

HV Fitlering (Bicential Board Rev B?)
Review some previously run simulation. [link]

XTD
Still under investigation on why JTAG is working.

Mechanical Structures
ZJ are waiting for Solidworks model.  

Ended :  1:56pm
NOTE :

First,  Correction were made the to the previous model


Update 31-July-2017 :
Since removing the Cb,  We are no longer getting any gain from LMH6629.  


Schematic View
TransientAC AnalysisNoise Analysis
Lt-spice Simulation with V9 [.zip]
- Cb were removed from the feedback.
- AD8045 [ds] & Twin LMH6629 [ds]: 1st = 1x,  2nd = 10x, & 3rd = -10x
- Supply Rail 5V
Comment : 7/31/2017 - Current Model shows a issue with the that this at the second stage,  there is an issue were the there should be
20dB of gain and showing 150-90db = -40dB from previous amplifier stage.   This suggest there is something
wrong with this current model and we are investigating why this are the case.
 

Schematic View
Schematic ViewSchematic ViewSchematic View
Lt-spice Simulation with V9.B [.zip]
- Cb were removed from the feedback.
- AD8045 [ds] & Twin LMH6222 [ds]: 1st = 2x,  2nd = 10x, & 3rd = -10x
- Supply Rail Changed to 5/-5V
Comment :  7/31/2017 - These too shows the same incorrect gains seen by the second stage.   Require thural investigation.
Still need to perform Noise analysis,  


Schematic View
Schematic ViewSchematic ViewSchematic View
Lt-spice Simulation with V10 [.zip]
- Cb were removed from the feedback.
- AD4817 [ds] & Twin LMH6222 [ds] : 1st = 2x,  2nd = 10x, & 3rd = -10x
- Supply Rail Changed to 5/-5V
Comment :

Addition list of task before the photon factory visit are made available.  [Link]

Added more information on the Archive Section of the page.
updated the required spec to the

Archive
HV board are going to be separate due to the difficultly of space constraint. 
Most of filtering capacitors had a diameter of two inch thus taking half of the boards.  
The HV filtering will have the separated page.  Link HERE

Potential Amplifier's Choice. (Updated Date: 7/31/2017)

 Name (Manf)
 -3dB BW (@Gain, Supply, Single?)
 Noise*
 Type
  Slew rate
 Vsupply
 ISupply
 Package
 SM
 [ds]
1
 AD8000 (Analog)
 1.5 GHz (x1, 3.3V, Yes) 1.6 nV/√Hz CFA
 4100 V/μs 4.5 V to 12 V 13.5 mA

[ds]
2
 AD8045 (Analog)
 1.2 GHz  (x1, 3.3V, Yes) 3 nV/√Hz / 3 fA/√Hz VFA
 1350 V/μs 3.3 V to 12 V 15 mA LFCSP/SOIC []
 [ds]
3
 ADA4817 (Analog)
 1.05 GHz (x1, 3.3V, Yes) 4 nV/√Hz / 2.5 fA/√Hz VFA
 870 V/μs 5 V to 10 V 19 mA SOIC
 []
 [ds]











4
 LMH6629 (TI)
 820 MHz (x10, 3.3V, Yes)
 0.69 nV/√Hz / 2.6 pA/√Hz VFA (SiG)
 1000 V/μs @ Comp=LO
511 V/μs @ Comp=HI
 2.7 V to 5.5 V 13.7 mA
 WSON8/SOT23-5 []
 [ds]
5
 LMH6703 (TI)
 1.2 GHz (x2, 5V , Yes?**)
 2.3 nV/√Hz / 3 pA/√Hz CFA
 4500 V/μs 5 V to 10 V 11 mA SOIC8/SOT6
[ds]
6
 OP847 (TI)
 600 MHz (x12, 3.3V, Yes)
 0.98 nV/√Hz / 3.7 pA/√Hz VFA
 950 V/μs 5 V to 10 V 18.1mA SOIC8/SOT6
[ds]
7
 THS3001 (TI)
 400 MHz (x1, 3.3V, Yes) 1.6 nV/√Hz / 16 pA/√Hz CFA
 6500 V/μs 9 V to 33 V 10 mA SOIC8/SOT6
[ds]
8
 THS4302 (TI)
 2.4GHz (x5, 3V and 5V )
 2.8 nV/√Hz N/A
 5500 V/μs 3V to 5V
 48mA
 QFN16
[ds]
9
 THS4303 (TI)
 1.8GHz (x10, 3V and 5V, yes)
 2.5 nV/√Hz
5500 V/μs 3V to 5V 48mA QFN16
[ds]
10
 THS4304 (TI)
 900 Ghz (x2, 3V, Yes)
 2.4 nV/√Hz / 2.1 pA/√Hz VFA (SiG)
 830V/μs 2.7 V to 5.5 V 18 mA
 MSOP/SOIC/SOT6
[ds]

* if CFA,  then there will be current input noise and voltage input noise.   pA
**Mentions that it is possible but doesn't specify the range.

Previous Simulation are now posted Now.

Lt-spice Simulation with V8 & V9 [.zip]
-  LMH6703 & two LMH6629 [ds] :  1st  = 1x, 2nd = 10x , 3rd = -10x
-  Sweepting Rf & Rg
Comment : - 7/31/2017 - Correction still need to be made to this model to reflect the removal of Cb

Lt-spice Simulation with V7 [.zip]
-  LMH6703 & two LMH6629 [ds] :  1st  = 1x, 2nd = 10x , 3rd = -10x
- 
Comment : - 7/31/2017 - Correction still need to be made to this model to reflect the removal of Cb

Lt-spice Simulation with V6 [.zip]
-  LMH6703 & two LMH6629 [ds] :  1st  = 1x, 2nd = 10x , 3rd = -10x
- 

Lt-spice Simulation with V5 [.zip]
- Sweeping through the Rf and Rg to determine any signal were seen when the Cb were removed from the feedback.
- Twin LMH6629 [ds] : 1st = 10x , 2nd = -10x

Lt-spice Simulation with V4 [.zip]

Step model Pre-Amplifers board Rev A [.stp]

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Website Last Updated (7/31/2017)