Altium

Design Rule Verification Report

Date: 4/23/2019
Time: 5:15:34 PM
Elapsed Time: 00:00:00
Filename: F:\JDC\Project\PCB\pp_19_002-amp_testboard_reva\tstboardrevA.PcbDoc
Warnings: 1
Rule Violations: 30

Summary

Warnings Count
Design contains shelved or modified (but not repoured) polygons. The result of DRC is not correct. Recommended to restore/repour all polygons and proceed with DRC again 1
Total 1

Rule Violations Count
Clearance Constraint (Gap=10mil) (All),(All) 2
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 1
Width Constraint (Min=10mil) (Max=30mil) (Preferred=20mil) (Disabled)(InNetClass('3V3')) 0
Width Constraint (Min=10mil) (Max=30mil) (Preferred=20mil) (Disabled)(InNet('GND')) 0
Width Constraint (Min=20mil) (Max=40mil) (Preferred=30mil) (Disabled)(InNetClass('Power')) 0
Width Constraint (Min=6mil) (Max=400mil) (Preferred=8mil) (Disabled)(All) 0
Minimum Annular Ring (Minimum=4mil) (All) 0
Hole Size Constraint (Min=10mil) (Max=265mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=5mil) (IsPad),(All) 4
Silk to Silk (Clearance=0mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (All) 23
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (Disabled)(All) 0
Total 30

Warnings

Design contains shelved or modified (but not repoured) polygons. The result of DRC is not correct. Recommended to restore/repour all polygons and proceed with DRC again
Polygon named: L1-GND

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Clearance Constraint (Gap=10mil) (All),(All)
Clearance Constraint: (7.261mil < 8mil) Between Pad L1-1(2050mil,1435mil) on L1 And Polygon Region (24 hole(s)) L1
Clearance Constraint: (3.656mil < 8mil) Between Pad L1-3(1930mil,1555mil) on L1 And Polygon Region (24 hole(s)) L1

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Modified Polygon (Allow modified: No), (Allow shelved: No)
Modified Polygon: Polygon Not Repour After Edit (L1-GND) on L1

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Silk To Solder Mask (Clearance=5mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (3.784mil < 5mil) Between Arc (1237.52mil,1697.109mil) on Top Overlay And Pad DF-2(1237.913mil,1697.109mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [3.784mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad L1-1(2050mil,1435mil) on L1 And Track (2070mil,1410mil)(2070mil,1580mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad L1-3(1930mil,1555mil) on L1 And Track (1910mil,1410mil)(1910mil,1580mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R2-1(1624.37mil,1560mil) on L4 And Text "R1" (1644mil,1593mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]

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Board Clearance Constraint (Gap=0mil) (All)
Board Outline Clearance(Outline Edge): (9.922mil < 15mil) Between Board Edge And Pad K1-1(1108.347mil,1325mil) on L1
Board Outline Clearance(Outline Edge): (9.922mil < 15mil) Between Board Edge And Pad K1-2(1108.347mil,1160mil) on L1
Board Outline Clearance(Outline Edge): (9.922mil < 15mil) Between Board Edge And Pad K1-2(1108.347mil,1160mil) on L4
Board Outline Clearance(Outline Edge): (9.922mil < 15mil) Between Board Edge And Pad K1-2(1108.347mil,1490mil) on L1
Board Outline Clearance(Outline Edge): (9.922mil < 15mil) Between Board Edge And Pad K1-2(1108.347mil,1490mil) on L4
Board Outline Clearance(Outline Edge): (11.575mil < 15mil) Between Board Edge And Pad K2-1(2370mil,1325mil) on L1
Board Outline Clearance(Outline Edge): (11.575mil < 15mil) Between Board Edge And Pad K2-2(2370mil,1160mil) on L1
Board Outline Clearance(Outline Edge): (11.575mil < 15mil) Between Board Edge And Pad K2-2(2370mil,1160mil) on L4
Board Outline Clearance(Outline Edge): (11.575mil < 15mil) Between Board Edge And Pad K2-2(2370mil,1490mil) on L1
Board Outline Clearance(Outline Edge): (11.575mil < 15mil) Between Board Edge And Pad K2-2(2370mil,1490mil) on L4
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (1005.236mil,1555.377mil)(1005.236mil,1838.842mil) on Top Overlay
Board Outline Clearance(Outline Edge): (2.737mil < 15mil) Between Board Edge And Track (1005.236mil,1555.377mil)(1784.764mil,1555.377mil) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (1005.236mil,1838.842mil)(1784.764mil,1838.842mil) on Top Overlay
Board Outline Clearance(Outline Edge): (2.048mil < 15mil) Between Board Edge And Track (1010.142mil,1100mil)(1220mil,1100mil) on Top Overlay
Board Outline Clearance(Outline Edge): (7.189mil < 15mil) Between Board Edge And Track (1010.142mil,1550mil)(1220mil,1550mil) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (1036.732mil,1555.377mil)(1036.732mil,1838.842mil) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (1036.732mil,1838.842mil)(1753.268mil,1838.842mil) on Top Overlay
Board Outline Clearance(Outline Edge): (2.048mil < 15mil) Between Board Edge And Track (1220mil,1100mil)(1220mil,1550mil) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (1753.268mil,1555.377mil)(1753.268mil,1838.842mil) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (1784.764mil,1555.377mil)(1784.764mil,1838.842mil) on Top Overlay
Board Outline Clearance(Outline Edge): (2.048mil < 15mil) Between Board Edge And Track (2258.347mil,1100mil)(2258.347mil,1550mil) on Top Overlay
Board Outline Clearance(Outline Edge): (2.048mil < 15mil) Between Board Edge And Track (2258.347mil,1100mil)(2468.205mil,1100mil) on Top Overlay
Board Outline Clearance(Outline Edge): (8.843mil < 15mil) Between Board Edge And Track (2258.347mil,1550mil)(2468.205mil,1550mil) on Top Overlay

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