LAPPD Electronics Microgroup (ID Lab page)

champ encapsulatedchamp open cavitychamp die photo

Local scheduling of effort:   [xls]   [pdf]

Meetings/Agendas now hosted on the UChicago [TRAC]


Dial-in information:  (866) 740-1260  (toll free USA, Canada)

                               0800 94 2408   (Toll free Int'l [France])

        Access code:  8147808  (followed by "#")

Current TDR page:  [link]


Weekly Meeting  (10:00 am HST, 2:00 pm CST, 9:00 pm CET)

Summary of where Sergey got to with IRS3B-based ceramic tile readout [doc]

08-FEB-2012 Meeting  (10:00 am HST, 2:00 pm CST, 9:00 pm CET)

  1. PSEC-4:
  2. PSEC-3 paper - godparent committee set
  3. Merging Hawaii digitizers with Chicago boards
  4. Discussion - switch agendas to [TRAC]?
  5. AOB?

Deferred?
  1. Anode paper progress?  Draft still ongoing?


01-FEB-2012 Meeting  (10:00 am HST, 2:00 pm CST, 9:00 pm CET)

  1. PSEC-4:
  2. PSEC-3 paper (Eric, Herve)
  3. Merging Hawaii digitizers with Chicago boards
  4. AOB?

Deferred?
  1. Anode paper progress?  Draft still ongoing?


25-JAN-2012 Meeting  (10:00 am HST, 2:00 pm CST, 9:00 pm CET)

  1. Anode progress / paper [link from Tue. mtg] (Herve, Razib)
  2. PSEC-4:
  3. PSEC-3 paper (Eric, Herve)
  4. AOB?

19-JAN-2012 Meeting + Central Card Design Review  (10:30 am HST, 2:30 pm CST, 9:30 pm CET)

  1. PSEC-4:
  2. PSEC-3 paper updates (Eric, Herve)
  3. Anode progress / paper (Herve, Razib)
  4. Relevant experience from T-1019 [link] (Kurtis, Matt, Gary)
  5. AOB?
  1. Central card design review [link to schematics/layout]

13-JAN-2012 Digital Card Design Review Part 2: The Layout Strikes Back  (10:30 am HST, 2:30 pm CST, 9:30 pm CET)


12-JAN-2012 Digital Card Design Review  (9am HST, 1pm CST, 8pm CET)

  1. Digital card information [link]

11-JAN-2012 Meeting  (10am HST, 2pm CST, 9pm CET)

  1. PSEC-4:
  2. PSEC-3 paper updates (Eric)
  3. Anode progress / paper (Herve, Razib)
  4. Relevant experience from T-1019 (Kurtis, Matt, Gary)
  5. AOB?

7-DEC-2011 Meeting  (10am HST, 2pm CST, 9pm CET)

  1. PSEC-4:
  2. PSEC-3 paper updates (Eric)
  3. Firmware/software tables for collab. meeting (Ed)  [elec. blog link]
  4. AOB?



30-NOV-2011 Meeting  (10am HST, 2pm CST, 9pm CET)

  1. PSEC-4:
  2. PSEC-3 paper updates (Eric)
  3. AOB?



23-NOV-2011 Meeting  (10am HST, 2pm CST, 9pm CET)

  1. PSEC-4:
  2. PSEC-3 paper updates (Eric)
  3. Timing resolution simulations (J.F.) - [blog link]
  4. Action items from last few weeks:
  5. AOB?

16-NOV-2011 Meeting  (9am HST, 1pm CST, 8pm CET)

  1. PSEC4:
  2. PSEC3 paper updates (Eric)
  3. Action items from last couple weeks - all handled?:
  4. AOB?

9-NOV-2011 Meeting  (9am HST, 1pm CST, 8pm CET)

  1. PSEC4:
  2. Further comments on LAPPD NSS draft (Jean-Francois)?
  3. PSEC3 paper updates (Eric)
  4. Action items from last week - all handled?:
  5. AOB?

2-NOV-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)  

  1. PSEC4:
  2. Update on stripline development
  3. "RF pocket pulser" design for fast signal injection (Gary)
  4. Additional batch (239) IRS2 received [analog card + ?]
  5. PSEC3: close the book?
  6. Updated fun with (Daniel)-Boone  [link]
  7. Action items:
  8. AOB?

26-OCT-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC4:
  2. PSEC3: close the book?
  3. Fun with (Daniel)-Boone  [link]
  4. AOB?

19-OCT-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC4:
  2. PSEC3: close the book?
  3. IRS2/3 Analog card (Gary)
  4. Code to simulate PLL-based timing generation [main blog link] (Jean-Francois)
  5. AOB?   [link]

12-OCT-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC4:
  2. PSEC3: close the book?
  3. IRS2/3 Analog card (Gary)
  4. Update on Flip chip?
  5. Timing resolution for many sampling rates [png] (Jean-Francois)
  6. AOB?   [link]

5-OCT-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. System Readout Discussion  [link]
    1. Analog-digital card connection?
    2. Signalling/power cabling?
  2. Cost structure discussion (action item from last week)
  3. PSEC4:
  4. PSEC3: close the book?
  5. IRS2/3 Analog card (Gary)
  6. Update on Flip chip?
  7. AOB?   [link]

28-SEP-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC4:
  2. PSEC3:
  3. Status of TIPP drafts [Karen's link to current versions]
  4. AOB?

14-SEP-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC3:
  2. PSEC4 preparations
  3. Status of TIPP drafts [Karen's link to current versions]
  4. AOB?

7-SEP-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC3:
  2. PSEC4 preparations
  3. Status of TIPP drafts
  4. AOB?

31-AUGUST-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC3:
  2. PSEC4 preparations
  3. Status of TIPP drafts
  4. AOB?

23-AUGUST-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC3:
  2. PSEC4 preparations
  3. Status of TIPP drafts
  4. AOB?

18-AUGUST-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. Discussion on preparations for larger DAQ systems, DAQ/firmware interfaces
  2. PSEC3:
  3. PSEC4 preparations
  4. AOB?


20-JULY-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

Dial-in information:  (866) 740-1260  (toll free USA, Canada)

                               0800 94 2408   (Toll free Int'l [France])

        Access code:  8147808  (followed by "#")
  1. Godparent review followup:
  2. PSEC3:
  3. Anode update [Tue. presentation link] [calculation details link] (Herve)
  4. Algorithms/Data Processing:
  5. AOB?


13-JULY-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. Godparent review followup:
  2. PSEC3:
  3. Anode update (Herve)
  4. Software reorganization - summary from last week's meeting?
  5. AOB?


06-JULY-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. Godparent review followup:
  2. Reorganization of software/simulation/etc. web archive [link] (Ed, all)
  3. PSEC3:
  4. Anodes:
  5. Further CHAMP testing
  6. AOB?


29-JUN-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. Godparent review:
  2. PSEC3 related:
  3. AOB?


22-JUN-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. Godparent review related:
  2. Mock tile related:
  3. PSEC3 related:
  4. CHAMP related:
  5. AOB?


1-JUN-2011 Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. Post-godparent review items:
  2. PSEC3 related:


18-MAY-2011 post submission meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. Preparations for Electronics godparent review, Friday May 20th @ ANL
  2. TDR Update



11-MAY-2011 post submission meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. Preparations for Electronics godparent review:
  2. TDR Update
.

04-MAY-2011 Short Weekly Meeting for May 9 submission last minute questions/issues  (9am HST, 2pm CDT, 9pm CEST)

Dial-in information:  (866) 740-1260  (toll free USA, Canada)

                               0800 94 2408   (Toll free Int'l [France])

        Access code:  8147808  (followed by "#")

Short meeting this week focused on issues related to May 9 submission:
  1. Chicago ASIC Submission - PSEC3A
  2. Hawaii ASIC Submission - RITC

Other items deferred until next week, post-submission.

20-APR-2011 Regular Weekly Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC3
  2. CHAMP
  3. PCB designs
  4. Other ASIC related
  5. Software/DAQ issues?
  6. Next TDR updates [Gary, Kurtis]
  7. AOB?

Deferred
  1. Stripline PMT results from Hawaii - ideally incorporate with timing calibration TIPP results
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]
  2. Flip-chip board status - deferred until QFP fully tested [Mircea]
  3. Alternative ASICs  [link]


13-APR-2011 Regular Weekly MeetinG  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC3
  2. Anode testing
  3. CHAMP
  4. PCB designs
  5. Software/DAQ issues? [Ed, Kurtis, others]
  6. TIPP Abstracts (deadline extended to April 15)
  7. Next TDR updates [Gary, Kurtis]
  8. AOB?

Deferred
  1. Stripline PMT results from Hawaii - ideally incorporate with timing calibration TIPP results
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]
  2. Flip-chip board status - deferred until QFP fully tested [Mircea]
  3. Alternative ASICs  [link]



6-APR-2011 Regular Weekly Meeting  (9am HST, 2pm CDT, 9pm CEST)

  1. PSEC3 updates
  2. Anode testing
  3. CHAMP:
  4. Card designs:
  5. Software/DAQ issues? [Ed, Kurtis,others]
  6. TIPP Abstracts (deadline extended to April 15):
  7. Next TDR updates [Gary, Kurtis]
  8. AOB?



30-MAR-2011 Regular Weekly Meeting  (9am HST, 2pm CDT, 8pm CET)

  1. PSEC3 updates
  2. CHAMP:
  3. Card designs:
  4. Software/DAQ issues? [Ed, Kurtis,others]
  5. TIPP Abstracts (deadline extended to April 15):
  6. Next TDR updates [Gary, Kurtis]
  7. AOB?

Deferred
  1. Stripline PMT results from Hawaii - ideally incorporate with timing calibration TIPP results
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]
  2. Flip-chip board status - deferred until QFP fully tested [Mircea]


23-MAR-2011 Regular Weekly Meeting  (9am HST, 2pm CDT, 8pm CET)

  1. PSEC3 updates
  2. CHAMP:
  3. Card designs:
  4. Software/DAQ issues? [Ed, Kurtis,others]
  5. TIPP Abstracts (submitter - informal topic):
  6. AOB?

Deferred
  1. Stripline PMT results from Hawaii - ideally incorporate with timing calibration TIPP results
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]
  2. Flip-chip board status - deferred until QFP fully tested [Mircea]

Older & Perpetual items
  1. Overall software/DAQ approach / protocol
    1. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    2. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  2. Tray assembly status [pptx] [Mircea]
  3. TDR update  [ZIP] archive (Last update: 21-NOV-2010)
  4. ASIC options for large channel count [link]


16-MAR-2011 Regular Weekly Meeting  (TIME CHANGE FOR CHICAGO: 9am HST, 2pm CDT, 8pm CET)

  1. PSEC3 updates?
  2. CHAMP:
  3. Anode tests [blog link] [Hervé]
  4. Mezzanine card & Rev. B Digitizer, submitted? (and how many?) [Eric]
  5. Software/DAQ issues? [Ed, Kurtis,others]
  6. AOB?

Deferred
  1. Stripline PMT results from Hawaii
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]
  2. Flip-chip board status - deferred until QFP fully tested [Mircea]

Older & Perpetual items
  1. Overall software/DAQ approach / protocol
    1. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    2. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  2. Tray assembly status [pptx] [Mircea]
  3. TDR update  [ZIP] archive (Last update: 21-NOV-2010)
  4. ASIC options for large channel count [link]


9-MAR-2011 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

Dial-in information:  (866) 740-1260  (toll free USA, Canada)

                               0800 94 2408   (Toll free Int'l [France])

        Access code:  8147808  (followed by "#")
  1. PSEC3 updates?
  2. ASIC options for large channel count [link]
  3. CHAMP:
  4. Design reviews - follow-up? [Mircea]
  5. Flip-chip update - defer until QFP is tested?
  6. Software/DAQ issues? [Ed, Kurtis,others]
  7. Discussion of TIPP Submissions?
  8. AOB?

Deferred
  1. Stripline PMT results from Hawaii
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]

Older & Perpetual items
  1. Overall software/DAQ approach / protocol
    1. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    2. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  2. Tray assembly status [pptx] [Mircea]
  3. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  4. TDR update  [ZIP] archive (Last update: 21-NOV-2010)


2-MAR-2011 Regular Weekly Meeting

  1. Design reviews -- follow-up?? [Mircea]
  2. PSEC3 updates?
  3. Flip-chip update?
  4. CHAMP:
  5. Software/DAQ issues? [Ed, Kurtis,others]
  6. AOB?

Deferred
  1. Stripline PMT results from Hawaii
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]

Older & Perpetual items
  1. Overall software/DAQ approach / protocol
    1. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    2. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  2. Tray assembly status [pptx] [Mircea]
  3. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  4. TDR update  [ZIP] archive (Last update: 21-NOV-2010)


23-FEB-2011 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. Design reviews [Mircea]
    1. Mezzanine card documentation  [link]
    2. Rev. B Digitizer:
      1. schematics  [link]
      2. layout  [link]
  2. PSEC3 updates?
  3. Flip-chip update?
  4. CHAMP update?
    CHAMP flyer
  5. Software/DAQ issues? [Ed, Kurtis,others]
  6. AOB?

Deferred
  1. Stripline PMT results from Hawaii
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]

Older & Perpetual items
  1. Overall software/DAQ approach / protocol
    1. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    2. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  2. Tray assembly status [pptx] [Mircea]
  3. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  4. TDR update  [ZIP] archive (Last update: 21-NOV-2010)


16-FEB-2011 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. PSEC3
    1. Some assorted updates [blog post] from [Hervé]
      1. Requested 64-bit Cypress [driver], from "Cypress Suite USB 3.4.2"  [Kurtis]
    2. Previously discussed calibrations
      1. Initial [undocumented / uncommented code] (needs ROOT libraries to compile)
      2. Give documentation & example [Kurtis]
      3. Is PSEC3 sine wave data available somewhere? [Eric?]
    3. Other updates/plans?
  2. CHAMP
    1. Arrived in Hawaii Jan. 14, 71 total pieces, 69 available
      1. Die [photo(s)] (large, 1.2 MB)
    2. Hawaii to coordinate packaging [Matt]
      1. How many to package?  Can we package and still maintain access to probe pads?  Wire bonding ourselves does not seem to seem to be an option due to required 14mmx14mm QFP.
    3. CHAMP_eval - other parts have been ordered
      1. After packaging, assembly queue: 2 for Chicago, 2 for Hawaii
  3. Software/DAQ issues [Ed, Kurtis,others]
    1. USB reference design, stuck on some Cypress issues [Kurtis]
    2. Updating/porting previous Matlab code to Octave [Ed]
  4. AOB?

Deferred
  1. Stripline PMT results from Hawaii
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]

Older & Perpetual items
  1. Overall software/DAQ approach / protocol
    1. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    2. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  2. Tray assembly status [pptx] [Mircea]
  3. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  4. TDR update  [ZIP] archive (Last update: 21-NOV-2010)

09-FEB-2011 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. PSEC3
    1. PSEC3 summary report from main LAPPD meeting [pdf] [Eric]
    2. (Hopefully relevant) Hawaii calibration approaches & past experience [pdf] [Kurtis]
    3. Analog bandwidth considerations [ppt from blog] [Jean-Francois]
    4. Notes from discussion with Klaus [blog post] [Hervé]
  2. CHAMP
    1. To arrive in Hawaii "soon" - no further updates since Jan. 24
    2. Hawaii to coordinate packaging [Matt]
    3. CHAMP_eval - other parts have been / are being ordered
      1. Total: 2 for Chicago, 2 for Hawaii
  3. Future ASIC plans - Jean-Francois visiting Chicago, Gary to call Chicago later to discuss
  4. Software/DAQ issues [Ed, Kurtis,others]
    1. USB reference design still in progress [Kurtis]
    2. Updating/porting previous Matlab code to Octave [Ed]
  5. Stripline PMT results from Hawaii
    1. General trends seem okay (e.g., timing resolution vs. % transmission of neutral density filter) [pdf]
    2. Planning to take more data w/ more filters, better amplifiers (previously 20 dB only). [Kurtis]
  6. AOB?

Older & Perpetual items

  1. Overall software/DAQ approach / protocol
    1. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    2. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  2. Tray assembly status [pptx] [Mircea]
  3. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  4. TDR update  [ZIP] archive (Last update: 21-NOV-2010)

02-FEB-2011 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

Matt & Gary away; Chicago under blizzard!
  1. PSEC3
    1. Report from main LAPPD meeting [pdf] [Eric]
    2. Any other PSEC report?
    3. Regarding linearity discussions, some experience w/ BLAB3: [Kurtis]
      1. BLAB3 linearity & sine wave histogram [pdf]
      2. Note: above uses very compact comparator [schematic pdf]
  2. CHAMP
    1. To arrive in Hawaii soon(?)
    2. Hawaii to coordinate packaging [Matt, once back]
    3. CHAMP_eval - other parts have been ordered
  3. Software/DAQ issues [Ed, Kurtis,others]
    1. Working on USB sample/reference design... more details/documentation soon. [Kurtis]
    2. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    3. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  4. AOB?

Deferred today
  1. Stripline PMT results from Hawaii
    1. More data was taken - analysis still underway [Kurtis]
    2. Previous test results: [Second round, PDF] [First round, PDF]

Older & Perpetual items

  1. Tray assembly status [pptx] [Mircea]
  2. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  3. TDR update  [ZIP] archive (Last update: 21-NOV-2010)

26-JAN-2011 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. PSEC3
    1. Bandwidth-related: [pdf presentation from blog] [png Bode plot] [Hervé]
    2. Smith chart assistance request? [Hervé]
    3. Report on results of trying to remove ripple delay errors? [Eric]
  2. CHAMP
    1. Currently being diced, to be shipped to Hawaii
    2. Hawaii to coordinate packaging [Matt?]
    3. CHAMP_eval - how many needed, populated, for each group?
  3. Jean-Francois to visit Chicago early February - confirm?
  4. Stripline PMT results from Hawaii
    1. More data was taken - analysis still underway [Kurtis]
    2. Previous test results: [Second round, PDF] [First round, PDF]
  5. Software/DAQ issues [Ed, Kurtis,others]
    1. Working on USB sample/reference design... more details/documentation soon. [Kurtis]
    2. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    3. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  6. AOB?

Older & Perpetual items

  1. Tray assembly status [pptx] [Mircea]
  2. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  3. TDR update  [ZIP] archive (Last update: 21-NOV-2010)

19-JAN-2011 (Short) Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. PSEC3
    1. Report next week on results of trying to remove ripple delay errors [Eric]
    2. Bandwidth - Trying to plot Smith chart in Matlab... anyone have experience? [Hervé]
  2. BLAB3
    1. Board redesign needed to confirm/test amplifier stability [Gary]
  3. Other
    1. Jean-Francois to visit Chicago in early February, to be confirmed.

12-JAN-2011 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

Dial-in information:  (866) 740-1260  (toll free USA, Canada)

                               0800 94 2408   (Toll free Int'l [France])

        Access code:  8147808  (followed by "#")
  1. Reports from picosecond timing workshop in Krakow [Jean-Francois]
    1. Jean-Francois's report: [Part 2b] [Part 2c]
    2. Full report series: [Part 1] [Part 2a] [Part 2b] [Part 2c]
    3. [Full Meeting INDICO]
  2. Testing results
    1. Stripline anodes passed off to ANL for further testing w/ MCPs
    2. Stripline PMT results from Hawaii
      1. More data was taken - still need to analyze [Kurtis]
      2. Previous test results: [Second round, PDF] [First round, PDF]
  3. CHAMP
    1. CHAMP - expected late January. [email] from Kostas, as forwarded by Eric
    2. CHAMP packaging - follow-up on what we expect to receive?  [Eric]
    3. CHAMP_eval - received 9 total
  4. PSEC3
    1. Results reported at yesterday's main LAPPD meeting [pdf] [Eric/Hervé]
    2. Previously reported results:
      1. Eric's report from Jan-05 main LAPPD meeting [ppt]
      2. Lots of results available on the [electronics blog]
      3. Test of board input bandwidth [blog post]
  5. Software/DAQ issues [Ed, Kurtis,others]
    1. Continuing email discussions: [Ed Jan-05-2011] [Henry Jan-05-2011]
    2. Previous record of discussion: [Ed Nov-18-2010] [Kurtis Dec-08-2010] [Ed Dec-17-2010]
  6. AOB?

Older & Perpetual items

  1. Tray assembly status [pptx] [Mircea]
  2. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  3. TDR update  [ZIP] archive (Last update: 21-NOV-2010)

05-JAN-2011 First Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. Reports from Krakow [Jean-Francois]
    1. Jean-Francois's report: [Part 2b] [Part 2c]
    2. Full report series: [Part 1] [Part 2a] [Part 2b] [Part 2c]
    3. [Full Meeting INDICO]
  2. Testing results
    1. Stripline anodes passed off to ANL for further testing w/ MCPs
    2. Stripline PMT results from Hawaii [Kurtis - away]
      1. More data was taken, to be discussed when Kurtis returns next week
      2. Previous test results: [Second round, PDF] [First round, PDF]
  3. CHAMP
    1. CHAMP - expected late January. [email] from Kostas, as forwarded by Eric
    2. CHAMP packaging - follow-up on what we expect to receive?  [Eric]
    3. CHAMP_eval - received 9 total
  4. PSEC3 - Lots of new test results!
    1. Eric's report from main LAPPD meeting [ppt] [Eric]
    2. Lots of resluts listed on the [electronics blog] [Eric]
    3. Test of board input bandwidth [blog post] [Hervé]
  5. Tray assembly status [pptx] [Mircea]
  6. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  7. Software/DAQ issues [Ed, Kurtis - away]
    1. Postpone until next week when Kurtis returns, or continue by email
    2. Record of discussion: [Ed's suggestions] [Kurtis's thoughts / proposal] [Ed's response]
  8. AOB?

Older / Perpetual items

  1. TDR update  [ZIP] archive (Last update: 21-NOV-2010)

15-DEC-2010 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

Reports from Krakow? [Meeting INDICO] [Gary, Jean-Francois, Hervé]
    1. Jean-Francois's next report: [Part 2a]
  1. Testing results
    1. Anode testing plans - anodes passed off to ANL for testing with MCPs [Eric]
    2. Stripline PMT results from Hawaii [Kurtis]
      1. More data taken: [PDF, analysis-in-progress]
      2. Previous test results: [PDF]
  2. CHAMP
    1. CHAMP - expected late January. [email] from Kostas, as forwarded by Eric
    2. CHAMP packaging - follow-up on what we expect to receive?  [Eric?]
    3. CHAMP_eval - received 9 total
  3. PSEC3
    1. Received by Chicago!
    2. Test schedule / results - more on electronics blog and to be discussed next meeting
  4. BLAB3A
    1. Very preliminary analog bandwidth [results]
  5. Flip-chip board status [Mircea]
    1. Follow-ups with Davis, outside company, [Fraunhofer institute]
  6. Software/DAQ issues
    1. Previous suggestions from Ed on software/DAQ  [txt]
    2. Proposed data format for IRS/BLAB3/TARGET-based readouts [pdf, in-progress] [Kurtis]
  7. Meeting schedule for holiday and New Year?
  8. AOB?

Older / Perpetual items

  1. TDR update  [ZIP] archive (Last update: 21-NOV-2010)

08-DEC-2010 Regular Weekly Meeting  

  1. TDR update  [ZIP] archive (21-NOV-2010)
  2. Reports from Krakow? [Meeting INDICO] [Gary, Jean-Francois, Hervé]
    1. Jean-Francois's report: [Part 1]
  3. Testing results
    1. Follow-up on testing of existing anodes
      1. Last week's first test outline & results from Eric: [blog link] [pdf]
      2. Any new results or plans?
    2. Stripline PMT testing in Hawaii
      1. Last week's first timing results: [PDF]
      2. Corrected / updated results on number of p.e. in last tests [PDF]
      3. Future plans?
  4. CHAMP
    1. CHAMP_eval - submitted for fabrication (ordered 9 total), shipped Friday, expected Dec. 8 (today!)
    2. What are actually getting, and when?  No reponse yet from Kostas.
      1. Any others with contacts at CERN that could be helpful in such situations?
  5. PSEC3 - 30 bare die, 10 in ceramic package, another 10 at MOSIS for plastic packaging
    1. What is being / has been received?  30 bare die, 10 cermaic package, another 10 plastic packaged?
    2. PSEC3 test board (8 ordered) - shipped, expected las Friday.  Did it arrive?
  6. Flip-chip board status [Mircea]
    1. Possible follow-up with outside company. (Lower priority...?)
    2. Frauenhofer institute follow-up [email from Klaus]
  7. Software/DAQ issues
    1. Previous suggestions from Ed on software/DAQ  [txt]
    2. Proposed data format for IRS/BLAB3/TARGET-based readouts [pdf, in-progress] [Kurtis]
  8. AOB?

01-DEC-2010 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. TDR update  [ZIP] archive (21-NOV-2010)
  2. Follow-up on testing of existing anodes - first test outline & results from Eric [blog link] [pdf]
  3. CHAMP_eval - submitted for fabrication (ordered 9 total), expected to ship on Dec. 6
  4. PSEC3 - 30 bare die, 10 in ceramic package, another 10 at MOSIS for plastic packaging
    1. PSEC3 received at Chicago?
    2. PSEC3 test board (8 ordered) - shipped, expected in Friday
  5. Flip-chip board status follow-up [Mircea]
    1. Sierra sent back dies & PCB, can't stud bump for us.
    2. Possible follow-up with another company?
  6. Suggestions from Ed on software/DAQ  [txt]
    1. Arrange special discussion on software/DAQ - will write up a brief proposal on data formats to start discussion [Kurtis]
  7. First stripline PMT results in Hawaii [PDF]
    1. Next tests: add ampliers, try other same-strip timing algorithms (cross-correlation)
  8. AOB?

24-NOV-2010 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. TDR update  [ZIP] archive (21-NOV-2010)
  2. Update on anode strip simulations   [Jean-Francois]
    1. Results discussed (but not yet seen) during last week's meeting. [pdf] [original]
    2. New plots recently distributed [pdf]
  3. Follow-up from last week on testing of existing anodes?
  4. CHAMP_eval layout (10-NOV-2010)   [Gary]
    1. Posted... comment from Mircea on thermal ties.
    2. Any other comments? 
  5. Flip-chip board status follow-up [Mircea]
  6. PSEC3 received at CERN, shipping to Chicago [email]
  7. Mircea's hardware development scheduling slides from Tuesday's LAPPD meeting
    1. Ed's related [questions] (in PDF at the linked post)
  8. Suggestions from Ed on software/DAQ  [txt]
    1. Arrange special discussion on software/DAQ [Kurtis]
  9. Mircea's [request] for optical link protocol and schematic
    1. Protocol is Aurora from Xilinx
    2. Schematic for an example board is [here] (others are available as well)
    3. Here is an interesting study of using Aurora to communicate between Xilinx and Altera  [PDF]
  10. AOB?
  11. After main meeting - discussion on working with stripline PMT [Gary, Matt, Kurtis, Ed, Jean-Francois]

17-NOV-2010 Regular Weekly Meeting 

  1. Firmware update   [link]  [Eric]
  2. Update on anode strip simulations  [link]     [Jean-Francois]
  3. Follow-up from last week on testing of existing anodes?
  4. CHAMP_eval layout (10-NOV-2010)   [Gary]
    1. Posted... any comments?
  5. Mircea's hardware development scheduling slides from Tuesday's LAPPD meeting
    1. Ed's related [questions]
  6. Mircea's [request] for optical link protocol and schematic
    1. Protocol is Aurora from Xilinx
    2. Schematic for an example board is [here] (others are available as well)

10-NOV-2010 Regular Weekly Meeting  (9am HST, 1pm CDT, 8pm CET)

  1. Firmware update   [link]  [Eric]
  2. Update on anode strip simulations  [link]     [Jean-Francois]
  3. Follow-up from last week on testing of existing anodes?
  4. CHAMP_eval layout (10-NOV-2010)   [Gary]
    1. Layout files   [gerber]
    2. Layout files (independent layers)   [PDF]
    3. Final schematics   [PDF]
    4. PADS design files:   [schematics]   [layout]
  5. Follow-ups:
    1. PSEC2 flip-chip status   [Mircea]
    2. Revised system drawings -- TDR update, update   [Gary]
    3. Update on shipping MCP-PMT   [Ed]
    4. Update on sending PSEC1 and previous boards to UC-Davis  [Eric]
    5. More PSEC3 ASICs ?  (a tray requires 160 channels = 40 chips)   [Eric]
    6. Packaging for CHAMP ASICs  (quote once die back)   [Matt]
  6. Review Action Items from last meeting
  7. AOB?

3-NOV-2010 Regular Weekly Meeting  (9am HST, 2pm CDT, 8pm CET)

  1. Firmware update [link]  [Eric]
  2. Report on response uniformity of the inside-out anode plane versus strip terminations  [link]     [Jean-Francois]
  3. Hermetic Packaging Godparent Review (22-OCT-2010)   [link]
    1. Urgent issue to understand LBNE needs   [Henry??]
    2. Electronics for commercially produced modules?   [Henry??]
  4. Follow-ups:
    1. PSEC2 flip-chip status   [Mircea]
    2. Revised system drawings -- system overview talk   [Gary]
    3. Update on sending PSEC1 and previous boards to UC-Davis  [Eric]
    4. More PSEC3 ASICs ?  (a tray requires 160 channels = 40 chips)   [Eric]
    5. Packaging for CHAMP ASICs  (quote once die back)   [Matt]
  5. Review Action Items from last meeting
  6. AOB?

Follow-up/Action Items from the 27-OCT-2010 Weekly Meeting

  1. Review Godparent Committee Review report response   [Gary/all]
    1. TDR updates as a result
    2. Short/near term readout test bed needs  [Ed]
  2. Follow-up items on direct/indirect feedback from Hermetic Packaging Review
    1. Urgent issue to understand LBNE needs   [Henry]
    2. Electronics for commercially produced modules?   [Henry]
  3. Various specific item follow-ups:
    1. Update on anode transmission line simulations   [Jean-Francois]
    2. MCP-PMT with anode readout ship to Hawaii?   [Ed]
    3. PSEC1/test board update to UC-Davis?  [Eric]
    4. PSEC2 flip-chip testing procedures/confirmation   [Mircea]
    5. Contact Kostas about additional batch(es) of 40 PSEC3     [Jean-Francois]
    6. Minor change to PSEC3 eval board (protection diode) and fabrication status    [Mircea]
    7. CHAMP Eval layout review    [Gary]
    8. Connector/cable options for digital card/master interconnection    [Mircea]
    9. Power connector options and LV regulation scheme    [Mircea/all]
    10. HV connectors, distribution and filtering?    [all]


27-OCT-2010 Regular Weekly Meeting  (9am HST, 2pm CDT, 9pm CET)

  1. Review Action Items from last meeting
  2. Hermetic Packaging Godparent Review (22-OCT-2010)   [link]
    1. Urgent issue to understand LBNE needs   [Henry??]
    2. Electronics for commercially produced modules?   [Henry??]
  3. Follow-ups:
    1. PSEC2 flip-chip PCB testing OK -- PO status?   [Mircea]
    2. Revised system drawings   [Mircea]
      1. Revised Tray  [jpg]  and descriptive  [txt]  and further refined version (Rev. B)  [jpg]
      2. Revised analog/digital card  [jpg]  and descriptive  [txt] and further refined version (Rev. B)  [jpg]
      3. A possible cable family for board interconnect  [PDF]   [link]
    3. Update on sending PSEC1 and previous boards to UC-Davis  [Eric]
    4. How many PSEC3 ASICs to package?  (only will get 40 and not 200) ??  [Eric]
    5. More PSEC3 ASICs ??  (a tray requires 160 channels = 40 chips)   [Eric]
    6. Packaging for CHAMP ASICs ??  (same as STURM2?)   [Eric]
  4. Report on response uniformity of the inside-out anode plane versus strip terminations     [Jean-Francois]
  5. Final board design for PSEC3 Eval board  [link]     [Mircea]
  6. AOB?

Action Items from the 13-OCT-2010 Weekly Meeting

  1. Begin Drafting Response to:  Godparent Electronics Review recommendations  [doc]  [PDF]
    1. Not clear integration and feedback/interaction with rest of project
      1. Suggestion is to put something on the agenda to permit discussion/coordination
    2. Concern about electromechanical meshing, grounding, HV
      1. Suggestion is to emphasize/provide links to existing documents in the blog Library
    3. System aspects, such as global clock distribution, weren't presented
      1. Mircea did present some aspects in his talk
      2. Some of this information was presented previously; though in retrospect that may have been during Collaboration meeting and not repeated to committee
      3. Point is well taken that core documentation (TDR) is missing an overall system diagram.  This will be added to TDR.
      4. Comment to reinvolve John Anderson in the design/system aspects of jitter cleaner system
    4. Calibration issues weren't presented
      1. The electronics group has collective experience in this task and it seemed a bit too nuts/bolts
      2. Agree that the TDR should have add a section on this task that can be referenced
    5. Perhaps most serious issue raised -- inverted versus "conventional" stripline
      1. This item is still under study and will be resolved upon completion of this task
    6. Testing plan -- in particular with integrated photodetector -- was not presented.  Not clear what test systems needed when.
      1. Ed agreed to help refine the requirements
      2. A detailed description of the text system for a "first article" will be added to the TDR as documentation
      3. Decoupling of characterization of the electronics and the MCP/PC module needs clarification
    7. Manpower concerns for developing a full readout system in Year 2
      1. A data processing/recording system based upon existing designs and expertise at Chicago and Hawaii was subsequently adopted (one of the highlights to come out of the review).  It will be detailed in the TDR.  Some initial figures illustrating the working concept:
      2. Analog_Digital_card  [jpeg]
      3. Tray_Clocks  [jpeg]
    8. Contingency scenarios for PSEC3
      1. While our priority is to work hard and qualify the PSEC3 as the baseline readout on the 3-6month timeline from now; should a show-stopper be identified, the group is ready to implement an interim solution based upon existing ASICs (DRS4 or IRS2).  While these devices represent compromises on the ultimate performance parameters, they should be adequate for the first round of integrated testing
  2. Revised Electronics section of TDR  [J-F/Gary]
    1. Current working draft:  [PDF]
    2. Known corrections needed:
      1. Overview prior to section 5.1 -- very first suggestion...
      2. Text on digital part
      3. Revise:  DAQ, Clock, Slow control part
      4. System diagram Figure needed  (Mircea's as starting place)
      5. Use FINESSE DSP figure rather than cPCI_DSP
      6. Additional wording needed for section 5.12
    3. Full source files:  [tdr_20oct2010.zip]
  3. Outstanding Action Item from trip:
    1. Gary to bring back 25um MCP-PMT for testing with BLAB3/IRS ASICs
    2. Instead agreed:  Ed will ship to Hawaii.  Gary provided address via e-mail:  2505 Correa Road, Watanabe Hall Room 214, Honolulu, HI 96822
  4. Update on CHAMP_eval   [Gary]
    1. Updated schematics (11-OCT-2010 version)   [PDF] -->  Design suggestion:  don't tie Ref to VDD.  Agreed, changed:
    2. Revised schematics  (17-OCT-2010 version)   [PDF]
    3. Deferred until Nov. 3rd meeting
  5. Update from PSEC3 tester board  [Mircea]
    1. Schematics posted  [link]  -->  Design change:  add protection diodes from Aeroflex/Metalics [link]
    2. Part number:   SMPN7320-SOT23\
    3. Revised above
  6. Status of UC Davis processing  [Eric]
    1. Receipt of PSEC1, test boards  -->  via snail mail, Mani will receive this week -- follow-up above
  7. AOB:  Eric will get MOSIS Project ID/passwd for CHAMP from Jean-Francois

13-OCT-2010 Regular Weekly Meeting  (9am HST, 2pm CDT, 9pm CET)

  1. Godparent Electronics Review recommendations  [doc]  [PDF]
  2. Revised Electronics section of TDR  [J-F/Gary]
    1. Edited draft  [PDF]
    2. Original source files:  [TDR_Electronics.tex]  [TDR_shell.tex]
  3. Outstanding Action Items from trip:
    1. Gary to bring back 25um MCP-PMT for testing with BLAB3/IRS ASICs ??
  4. Update on CHAMP_eval   [Gary]
    1. Updated schematics (11-OCT-2010 version)   [PDF]
    2. Preliminary placement  [PDF]
  5. Update from PSEC3 tester board  [Mircea]
    1. Finished schematics posted  [link]
  6. Status of UC Davis processing  [Eric]
    1. Receipt of PSEC1, test boards?
    2. Schedule update?
  7. AOB?


Electronics Godparent Review  --  October 6th at ANL

  1. Agenda for Electronics Review at ANL on October 6th  [summary from previous GPC]
    1. Link to Zikri's ElectronicsGF page  [here]
    2. Introductory Questions to guide the material presented  [PDF]  [source tex file]
  2. Guiding questions (from Henry with GSV tweaks):  [PDF]  [source tex file]

Origination (draft) Agenda

A) Refining Electronics needs

  1. impact of SNR, analog BW, cost/performance trade-offs   [J-F]
  2. Project specific specifications  (LHCb, JPARC, LBNE, SuperB), PET, muon cooling ?)  [J-F]
  3. Fabrication process options (IBM 130nm and others?)   [Gary]    [pptx]   [PDF]

B) ASIC Developments

  1. Results and further testing plans for PSEC2  [Eric]
  2. Building block evaluation ASIC:  CHAMP design and evaluation plans  [Matt]   [pptx]    [PDF]
  3. PSEC3 design and evaluation plans                  [Hervé]

C) Integrated Design issues

  1. Simulation results for single photon detection [Jacob Li]   [PDF]
  2. Recent stripline anode readout simulations [J-F]
  3. Readout boards (analog/digital cards for supermodule), links,
     architecture overview and plans  [Mircea?]

D) Test and evaluation resources and requirements [Gary]      [pptx]    [PDF]

    1. Summary from previous GPC  [PDF]
    2. Link to Zikri's ElectronicsGF page  [here]
    3. Link to the latest version of the TDR (v1.03)   [PDF link]

29-SEP-2010 Regular Weekly Meeting  (11am HST, 4pm CDT, 11pm CET)

  1. Possible change of meeting time?  (a more European friendly time slot?)
    1. Decided to move to 2pm CDT, 9pm CET, 9am HST
  2. Review of Action Items from last meeting, with follow-ups:
    1. Follow-up on phone meeting with UC Davis --> 2pm PDT on Friday:  meeting [link]
    2. Consider TQFP packaging for PSEC3, CHAMP  [MOSIS LQFP128A package]
    3. Comments from Ed on software posted on blog   [link]
    4. Gary to bring back 25um MCP-PMT for testing with BLAB3/IRS ASICs
  3. Agenda for Electronics Review at ANL on October 6th  [summary from previous GPC]
    1. Link to Zikri's ElectronicsGF page  [here]
    2. Introductory Questions to guide the material presented  [PDF]  [source tex file]
    3. Refining Electronics needs:
      1. impact of SNR, analog BW, cost/performance trade-offs
      2. Project specific specifications
      3. Fabrication process options (besides IBM 130nm)
    4. ASIC Developments:
      1. Results and further testing plans for PSEC2
      2. Building block evaluation ASIC:  CHAMP
      3. PSEC3 design
    5. Integrated Design issues
      1. Simulation results for single photon detection
      2. Recent stripline anode readout simulations
      3. Readout boards (analog/digital cards for supermodule), links, architecture overview and plans
    6. Test and evaluation resources and requirements
    7. Other?
  4. Revise Electronics section of TDR:  [TDR_Electronics.tex]  [TDR_shell.tex]
  5. Update on CHAMP_eval   [Gary]
    1. TQFP chosen
    2. Want at least 20 as bare die (some test circuits require probe/internal wire bonding) 
    3. Updated schematics (29-SEP-2010 version)   [PDF]
    4. Preliminary placement  [PDF]
  6. Updates (via e-mail) from Mircea:
    1. Received 1 PSEC2 Flip Chip PCB, Mark will stuff ASAP, should test it this week
    2. Finished PSEC3 module schematics posted  [link]
    3. BOM is also finished, posted
  7. Further discussion on the UC Davis option?
    1. Stream of discussion in text format, message 1:  [txt]  and subsequent follow-ups  [txt]
    2. When to arrange a call?
    3. Use PSEC1 for first functional Au stud bond test?  
    4. A smaller test board?  (< 10cm x 10cm)
  8. AOB?


22-SEP-2010 Regular Weekly Meeting  (11am HST, 4pm CDT, 11pm CET)

  1. Review of Action Items from last meeting, with follow-ups:
    1. Henry will check on 3pm time on Friday for phone meeting with UC Davis
    2. Consider seriously TQFP packaging for PSEC3, CHAMP  [MOSIS LQFP128A package]
    3. Comments from Ed on software posted on blog   [link]
    4. Gary to bring back 25um MCP-PMT for testing with BLAB3/IRS ASICs
  2. Agenda for Electronics Review at ANL on October 6th  [summary from previous GPC]
    1. Refining Electronics needs:
      1. impact of SNR, analog BW, cost/performance trade-offs
      2. Project specific specifications
      3. Fabrication process options (besides IBM 130nm)
    2. ASIC Developments:
      1. Results and further testing plans for PSEC2
      2. Building block evaluation ASIC:  CHAMP
      3. PSEC3 design
    3. Integrated Design issues
      1. Simulation results for single photon detection
      2. Recent stripline anode readout simulations
      3. Readout boards (analog/digital cards for supermodule), links, architecture overview and plans
    4. Test and evaluation resources and requirements

  3. Update on CHAMP_eval schematics    [Gary]
    1. TQFP trial? 
    2. First pass at schematics  [PDF]
    3. Revised (closer) schematics  [PDF]
  4. Brief update on Sierra PSEC2 flip-chip progress  [Mircea]
    1. Blog posting  [link]
  5. Discussion on the UC Davis option:
    1. Stream of discussion in text format, message 1:  [txt]  and subsequent follow-ups  [txt]
    2. When to arrange a call?
    3. Use PSEC1 for first functional Au stud bond test?  
    4. A smaller test board?  (< 10cm x 10cm)
  6. What to do in the intermediate term?  [all]
    1. Decided to go with DRS4_eval boards for first testing
    2. BLAB3/IRS? 
      1. firmware needs work
      2. Much deeper sampling rate
      3. IRS has respectable bandwidth   [PDF]
    3. DRS4?
      1. Mircea has experience with board for this ASIC
      2. DRS4 known to work well
      3. input bandwidth is an issue -- have to use an external amp
    4. STURM2?
      1. Narrow sampling window 
      2. >= 10GSa/s possible (only 8x samples)
      3. Firmware work needed
  7. Presentation from Jacob on CSA input amp  [PDF]
  8. First Experimental runs at the UH xFEL (ps x-ray timing/beamline)   [link]   Exp. #2 direct  [link]
  9. AOB?

15-SEP-2010 Meeting Action Items

  1. Decide on PSEC3 & CHAMP packaging (need Henry and J-F consensus)   [next meeting]
  2. Continued study of existing linux acquisition code -- with an eye toward generic modules  [Ed]
    1. Posted comments  [link]
    2. Comments based upon the current code -- needs Kurtis' feedback  [txt]
  3. Ed encouraged getting one of the small MCP-PMTs to Hawaii for mating:
    1. with existing IRS/STURM ASICs
    2. test in the xFEL beamline (1ps jitter)
  4. Defer discussion on possible module electronics in medium term when Henry/J-F can participate

15-SEP-2010 Regular Weekly Meeting  (11am HST, 4pm CDT, 10pm CET?)

  1. Review of Action Items from last meeting
  2. Update on CHAMP_eval schematics (priority dropped due to CHAMP delivery update)   [Gary]
  3. Root-based version of simple USB readout -- further development plans?  [Gary/all]
  4. Update on Sierra progress  [Mircea]
    1. On schedule for delivery of 1x board  on time
    2. Expected ship date Sept 24
  5. Revision to test plans?  [all]
  6. Discuss package/footprint for packaged parts [all]
  7. What to do in the intermediate term?  [all]
    1. BLAB3/IRS?
    2. DRS4?
    3. STURM2?
  8. Presentation from Jacob on CSA input amp  (deferred until next time)
  9. Short report from xFEL (ps x-ray timing/beamline)   [PDF]
  10. AOB?

8-SEP-2010 Meeting Action Items

  1. Establish ES-Net connection for next meeting per Ed's instructions [Gary]   --  Done
  2. Send link to root-based version of simple USB readout [Gary]   --  Done
    1. Summary e-mail with various links  [linux_soft.txt]
  3. Update on Sierra progress next time [Mircea]
  4. Confirm package/footprint for packaged parts [Mircea/Eric]  --  Done
  5. Confirm how many die to be packaged versus bare die (for probing)  [Eric/J-F]  --  Done
    1. Re-iterate numbers:  to be decided for CHAMP?
  6. Response from CERN on revised ASIC delivery schedules [Jean-Francois]  --  Done
    1. Message from J-F, including information from CERN folk  [.txt]
    2. Bottom line:  should not expect to see until mid-December
    3. Specific reminders:
      1. J-F and Gary need to compare bonding wire vs. flip-chip notes (during review?)
      2. The bonding diagram for PSEC is fine with J-F
      3. MOSIS V05F (CHAMP) and V08B (PSEC3) both due mid December
      4. bare dies for CHAMP [Kostas to confirm how many] -- have to package ourselves
      5. 10 packaged, 30 bare dies for PSEC3
  7. Follow-up with Bob W. on SOW  [Gary]  --  Done
  8. Anything I missed?

8-SEP-2010 Regular Weekly Meeting

4pm CDT (Chicago), 11am HST (Honolulu)
(808) 956-2920  [ID Lab]

Proposed agenda:
  1. PSEC2 ASIC board firmware update [Eric]
  2. PSEC2 ASIC board software/data format [Eric]
  3. Board test plans discussion (Chicago & Hawaii?)  [all]
  4. Feedback/schedule update from Sierra [Mircea]
  5. CHAMP test schematics (Chicago) [Mircea/Eric]
    1. schematic file  [PDF]
  6. CHAMP test items (Hawaii) [Matt]
    1. CHAMP pinout/ownership spreadsheet  [link]
    2. Test board spreadsheet  [link]
    3. graphical pin assignment   [PDF]

  7. CHAMP test schematics (Hawaii) [Gary/Matt/Louie]
    1. Same basic FPGA + USB readout as on many eval boards
    2. LQPF128A packaging?  [needed for footprint]
    3. Placeholder schematics  [PDF]
  8. CHAMP eval board design review (Sept. 15?)  discussion [all]
  9. PSEC3 evaluation board plans [Mircea/Eric]
  10. Update on ASIC deliveries (from Europe)  [Jean-Francois]
    1. Tried to make contact via e-mail/phone --> will advise when hears something
    2. Currently working on memo about transmission line readout
  11. Noise discussion/plot for TDR?  [Henry]
  12. Brief update on single p.e. (CSA, low-noise) amplifier  [next time -- Jacob]
  13. AOB ?

Archival:

27-AUG-2010 Flip-chip board design review

Link to manufacturing drawings   [here]

The proposed agenda includes:
- module functions,
- schematics,
- layout,
- manufacturing and cost,
- delivery schedule.
We will do this over the phone: 808-957-8610   passcode  1414

CHAMP board (regular LAPPD Electronics subgroup) Discussion

Agenda items:

  1. ETA on CHAMP ASIC
  2. Detailed design plans and task sharing for CHAMP test card
  3. Lessons learned from IRS/BLAB3
  4. BLAB3A plans
  5. status of sending test board to Hawaii (?)
  6. Preparation for design review Friday
  7. AOB



10-MAY-2010 Hervé update [txt] (for 9am HST phone call)

Reference Information:

16-JUN-2010 ASIC#2 being shipped from MOSIS

Note from Matt on USB programming [link]

10-MAY-2010 Hervé update [txt] (for 9am HST phone call)

Reference Information:


5-MAY-2010 Agenda:

  1. Discussion on status of integration
  2. Review of items below
  3. Plans/schedule prior to 17-MAY

Follow-up:

1) Other ASIC acronym suggestions?  [responses]



2) Does IBM offer scripts for the end user to perform metal fill operations which IBM does not automatically perform?

Hervé's response:

We did it by hand last time, it takes relatively a lot of time (around one day to do it) and has to be done for the last three
levels of metals; MA, E1 and LY.

For this three metals you need to fulfill the local and global density checks. A script would save us a lot of time
and difficulties for sure.

IMPORTANT REMARK : in the previous submissions we always had issues with these local and global density checks,
and our design had to go back and forth between us and Mosis to fulfill them.

    Follow-up question:  did anyone ask MOSIS/CERN/IBM if such a script exists?


3) Hawaii is using the IBM 1.6.2.5 design kit provided to MOSIS. Does this match with Chicago and CERN? -- DONE

Hervé confirms it is the same.

4) Will Chicago complete the pad ring with their components and ship the design to Hawaii?

5) Additional layers/options Hawaii is using (this will need to get checked with Matt, Kurtis, Larry -- To be done
6) Parasitic extraction [Hervé] -- DONE

Link is [here]
 
7) Footprint for probe pads [J-F] -- To be done
 
8) Allowed to use dual mimCAP?  -- DONE

Yes.  Kostas confirms this option (29-APR-10)

9) Implementing MC spreads in simulation [Eric] -- DONE

Eric sent out message and link is [here]


21-APR-2010 Meeting:   Agenda [txt]

We prepare preliminary dimensions and I/O pads for our blocks:

- PLL
- Timing generator (new version) with variable sampling windows
= RO (based on the new timing generator delay cell) + divider
- Phase comparator + charge pump
- Transmission line
- Resistors (we still do not know)

and a tentative floorplanning of say 3.24 x 3.24/2 (unless you need more ?)

For the delay generator, we have actually 256 cells of 12 microns each, so
3072 microns, we plan for 3.15mm maximum that fit the 3.24mm

128 pads is just perfect !

Jean-Francois

On Tue, 20 Apr 2010, Gary S. Varner wrote:

The agenda from our side:


1) Mike : LVDS Rx/Tx
2) Larry : small storage array
3) Wei : Charge Sensitive Amp
4) Kurtis: fast, differential storage cell
5) Matt : ring oscillators & DFFs
6) Gary : DAC & OTA/ABUF

Recent items:

  1. TDR working directory [draft]
  2. Link to Electronics Godparent committee page

Reference docs

  1. IRS analog bandwidth measurement  [PDF]
  2. Simulated TQFP input coupling  [PDF]
  3. UH "DC card" (psTDC01 eval) software [Larry]
  4. UH "DC card" (psTDC01 eval) RevDv01 firmware [Larry]
  5. UH "DC card" (psTDC01 eval) RevD v2 schematics [Larry]
  6. 3 technical reports on Detector, ASIC, DAQ [Gary, all]


Reference links:

  1. Main picosecond page
  2. blog
  3. Electronics blog



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Last modified: 3/8/2014 -- GSV