LAPPD
Electronics Microgroup (ID Lab page)
Meetings/Agendas now hosted on the UChicago [TRAC]
Dial-in information: (866) 740-1260 (toll free USA,
Canada)
0800 94
2408 (Toll free Int'l [France])
Access code: 8147808 (followed by "#")
Current
TDR page:
[link]
Weekly
Meeting
(10:00
am HST, 2:00 pm CST,
9:00 pm CET)
Summary of
where Sergey got to with IRS3B-based ceramic tile readout [doc]
08-FEB-2012
Meeting
(10:00
am HST, 2:00 pm CST,
9:00 pm CET)
PSEC-4:
System/card statuses (Analog/Digital/Central)
Any updates from APS testing?
Further results with PSEC-4 eval [elec.
blog link] (Joachim)
Timing calibration updates [pdf] (Kurtis)
PSEC-3 paper - godparent committee set
Merging Hawaii digitizers with Chicago boards
Discussion - switch agendas to [TRAC] ?
AOB?
Deferred?
Anode paper progress? Draft still ongoing?
01-FEB-2012
Meeting
(10:00
am HST, 2:00 pm CST,
9:00 pm CET)
PSEC-4:
System/card status
Analog card (Eric)
Digital card (Craig)
Central card (Mircea)
Further results with PSEC-4 eval (Joachim)
Timing calibration results [pdf] (Kurtis)
PSEC-3 paper (Eric, Herve)
Merging Hawaii digitizers with Chicago boards
Discussion on hardware/firmware/software issues
Discussion on using TRAC to
streamline efforts.
AOB?
Deferred?
Anode paper progress? Draft still ongoing?
25-JAN-2012
Meeting
(10:00
am HST, 2:00 pm CST,
9:00 pm CET)
Anode progress / paper [link
from Tue. mtg] (Herve, Razib)
PSEC-4:
System/card status
Test results with PSEC-4 eval [elec
blog link] (Joachim)
Plans/schedule for timing cal. (Kurtis)
PSEC-3 paper (Eric, Herve)
AOB?
19-JAN-2012
Meeting + Central Card
Design Review
(10:30
am HST, 2:30 pm CST,
9:30 pm CET)
PSEC-4:
System/card status
Analog card (Eric)
Digital card (Craig) - updates since design review?
Central card (Mircea) - design review today (see
below)
Test results with PSEC-4 eval [link]
(Joachim)
PSEC-3 paper updates (Eric, Herve)
Anode progress / paper (Herve, Razib)
Relevant experience from T-1019 [link] (Kurtis,
Matt, Gary)
AOB?
Central card design review [link
to schematics/layout]
13-JAN-2012
Digital Card Design
Review Part 2: The
Layout Strikes Back
(10:30
am HST, 2:30 pm CST,
9:30 pm CET)
12-JAN-2012
Digital Card Design
Review
(9am
HST, 1pm CST, 8pm CET)
Digital card information [link]
11-JAN-2012
Meeting
(10am
HST, 2pm CST, 9pm CET)
PSEC-4:
System/card status
Analog card (Eric)
Digital card (Craig) - design review tomorrow, please
review material in advance [link]
Central card (Mircea) - schematics from blog, as of
Dec. 21 [link]
Test results with PSEC-4 eval [link]
(Joachim)
PSEC-3 paper updates (Eric)
Anode progress / paper (Herve, Razib)
Relevant experience from T-1019 (Kurtis, Matt, Gary)
AOB?
7-DEC-2011
Meeting
(10am
HST, 2pm CST, 9pm CET)
PSEC-4:
System/card status
Debugging progress with PSEC-4 eval (Joachim)
Next timing & calibration measurement - some
initial results (Kurtis) [pdf]
PSEC-3 paper updates (Eric)
Firmware/software tables for collab. meeting (Ed) [elec.
blog
link]
AOB?
Deferred action items from previous meetings:
Discuss stripline with other RF specialists at Fermilab
(Dave M. replacement)
PSEC4 eval to Herve after check-out (no rush as he's
busy and can't test right away)
Universal_eval with IRS2 DC to Chicago when available
RF pocket pulser to Chicago when available
30-NOV-2011
Meeting
(10am
HST, 2pm CST, 9pm CET)
PSEC-4:
System/card status
Debugging progress with PSEC-4 eval (Joachim)
Next timing & calibration measurement plans?
PSEC-3 paper updates (Eric)
AOB?
Deferred action items from previous meetings:
Discuss stripline with other RF specialists at Fermilab
(Dave M. replacement)
PSEC4 eval to Herve after check-out (no rush as he's
busy and can't test right away)
Universal_eval with IRS2 DC to Chicago when available
RF pocket pulser to Chicago when available
23-NOV-2011
Meeting
(10am
HST, 2pm CST, 9pm CET)
PSEC-4:
System/card status
Debugging progress with PSEC-4 eval (Joachim)
Next timing & calibration measurement plans?
PSEC-3 paper updates (Eric)
Timing resolution simulations (J.F.) - [blog
link]
Action items from last few weeks:
Calculate/estimate power consumption for various cards
--> guide where to do power regulation
Discuss stripline with other RF specialists at Fermilab
(Dave M. replacement)
PSEC4 eval to Herve after check-out (no rush as he's
busy and can't test right away)
Universal_eval with IRS2 DC to Chicago when available
RF pocket pulser to Chicago when available
AOB?
16-NOV-2011
Meeting
(9am
HST, 1pm CST, 8pm CET)
PSEC4:
System/card status
Next timing measurement plans?
PSEC3 paper updates (Eric)
Action items from last couple weeks - all handled?:
NSS proceedings for LAPPD - submitted (Jean-Francois)
Eric will finish/post Analog card schematics in advance
of next week, for review
Calculate/estimate power consumption for various cards
--> guide where to do power regulation
Discuss stripline with other RF specialists at Fermilab
(Dave M. replacement)
PSEC4 eval to Herve after check-out (no rush as he's
busy and can't test right away)
Universal_eval with IRS2 DC to Chicago when available
RF pocket pulser to Chicago when available
AOB?
9-NOV-2011
Meeting
(9am
HST, 1pm CST, 8pm CET)
PSEC4:
Further comments on LAPPD NSS draft (Jean-Francois)?
PSEC3 paper updates (Eric)
Action items from last week - all handled?:
Eric will finish/post Analog card schematics in advance
of next week, for review
Calculate/estimate power consumption for various cards
--> guide where to do power regulation
Discuss stripline with other RF specialists at Fermilab
(Dave M. replacement)
PSEC4 eval to Herve after check-out (no rush as he's
busy and can't test right away)
Universal_eval with IRS2 DC to Chicago when available
RF pocket pulser to Chicago when available
AOB?
2-NOV-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC4:
Eval card in France? (Eric/Herve)
Testing:
Further testing or testing requests in Chicago
(Eric)
Hawaii testing status report (Joachim)
System/card status
Firmware development -- who is doing what?
Software development -- who is doing what?
Update on stripline development
"RF pocket pulser" design for fast signal injection
(Gary)
Design reference page [link]
Measured performance [pdf]
Additional batch (239) IRS2 received [analog card + ?]
PSEC3: close the book?
Updated fun with (Daniel)-Boone [link]
Action items:
Eric will finish/post Analog card schematics in advance
of next week, for review
Calculate/estimate power consumption for various cards
--> guide where to do power regulation
Discuss stripline with other RF specialists at Fermilab
(Dave M. replacement)
PSEC4 eval to Herve after check-out (no rush as he's
busy and can't test right away)
Universal_eval with IRS2 DC to Chicago when available
RF pocket pulser to Chicago when available
AOB?
26-OCT-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC4:
Eval card arrival dates: Hawaii (10/26
[arrived]); France (later)
Updated: [firmware]
and
[software]
and
has an oscilloscope function that uses gnuplot
Testing:
Report on timing analysis & calibration [pdf] (Kurtis)
Further Chicago testing (Eric/Joachim)
PSEC3: close the book?
Fun with (Daniel)-Boone [link]
AOB?
19-OCT-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC4:
Testing:
Report on timing analysis & calibration [pdf] (Kurtis)
Chicago/Hawaii testing (Eric/Joachim)
PSEC4-eval to Hawaii - shipping today?
PSEC3: close the book?
IRS2/3 Analog card (Gary)
Code to simulate PLL-based timing generation [main
blog link] (Jean-Francois)
AOB? [link]
12-OCT-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC4:
Testing plans
Timing calibration (Kurtis)
Detailed discussion deferred until Eric returns
Nonlinearity correction required? [pdf]
Chicago/Hawaii testing (Eric/Joachim)
PSEC4-eval to Hawaii?
PSEC3: close the book?
IRS2/3 Analog card (Gary)
Update on Flip chip?
Timing resolution for many sampling rates [png] (Jean-Francois)
AOB? [link]
5-OCT-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
System Readout Discussion [link]
Analog-digital card connection?
Signalling/power cabling?
Cost structure discussion (action item from last week)
PSEC4:
further Updates [link]
sawtooth/alignment plot (Eric) [jpg]
bondwire inductance matching (Gary) [PDF]
further die request? (Nov. 7 submission?)
Readout cards development:
Analog -- Eric
Digital -- Craig
Central -- Mircea
What needed for (daniel) Boone?
Firmware update? (Eric)
Testing plans
Timing calibration (Kurtis)
Chicago/Hawaii testing (Eric/Joachim)
PSEC3: close the book?
IRS2/3 Analog card (Gary)
Update on Flip chip?
AOB? [link]
28-SEP-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC4:
further Updates (Eric)
yesterday's presentation [link]
any issues?
further die request?
Eval, analog, digital card availability (Mircea)
Firmware status and software requests? (Eric)
Testing plans discussion (all)
Timing calibration (Kurtis)
Chicago/Hawaii testing (Joachim)
PSEC3:
Complete testing/write-up [full NIM paper]
Other PSEC3
Status of TIPP drafts [Karen's
link
to current versions]
AOB?
14-SEP-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC3:
PSEC3 timing calibration [pdf] (Kurtis)
Cross-talk measurement [png]
(Daniel)
Flip chip summary from Davis [jpg]
[jpg]
[jpg]
Other PSEC3
PSEC4 preparations
Status of TIPP drafts [Karen's
link
to current versions]
AOB?
7-SEP-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC3:
Received new calibration sets - will process ASAP
Pulser data study on cross-talk (Daniel, away)
Other?
PSEC4 preparations
Analog card, digital card, & new design tools
Status of TIPP drafts
AOB?
31-AUGUST-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC3:
Calibration data analysis [pdf] (Kurtis)
Pulser data study "[pdf]
(Daniel)
Ready to ship PSEC3 eval back to UChicago?
PSEC4 preparations
Status of TIPP drafts
AOB?
23-AUGUST-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC3:
Calibration data analysis w/ new (final?) dataset [pdf] (Kurtis)
PSEC4 preparations
Status of TIPP drafts
AOB?
18-AUGUST-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Discussion on preparations for larger DAQ systems,
DAQ/firmware interfaces
PSEC3:
New calibration data to run in Hawaii?
Flip chip updates from Davis?
PSEC4 preparations
AOB?
20-JULY-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Dial-in information: (866) 740-1260 (toll free USA,
Canada)
0800 94
2408 (Toll free Int'l [France])
Access code: 8147808 (followed by "#")
Godparent review followup:
Draft responses [link]
Can Eric or Herve give numbers for item 9?
Any other objections/corrections?
PSEC3:
Other tests/cross-checks
Some explanation of current timing results w/ psec3 [pdf] (Kurtis)
Timing analysis of PSEC3 w/ stripline MCP-PMT [pdf] (Daniel)
Flip chip updates from Davis?
Anode update [Tue.
presentation link] [calculation
details link] (Herve)
Algorithms/Data Processing:
VHDL for pulse processing [link]
(Tyler)
AOB?
13-JULY-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Godparent review followup:
Godparent review report [link]
Draft responses [pdf]
and remaining items:
Major objections/changes?
TDR update implications okay?
Table for item 2? This one? [link]
Better resolution picture of MCP bandwidth?
PSEC3:
Bandwidth measurement cross check in Hawaii [pdf] (Daniel)
Flip chip updates from Davis?
Anode update (Herve)
Software reorganization - summary from last week's meeting?
AOB?
06-JULY-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Godparent review followup:
Godparent review report [link]
Draft responses, remaining questions (Kurtis, Gary[away])
GP recommendation 1: What is definition of success?
GP recommendation 4: Updated milestones?
Reorganization of software/simulation/etc. web archive [link] (Ed, all)
PSEC3:
Flip chip updates from Davis?
Anodes:
Herve's discussion of plans [pdf]
Paper outline [pdf]
Further CHAMP testing
Daniel's measurements of ring oscillator and delay line
measurements [pdf]
Eric's measurements of ring oscillator [png]
AOB?
29-JUN-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Godparent review:
Godparent review report [link]
Plan for follow up?
PSEC3 related:
Coordinating measurements & Hawaii cross-checks
Any more calibration data needing processing?
AOB?
22-JUN-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Godparent review related:
Godparent review report [link]
Plan for drafting responses?
Mock tile related:
Updates on striplines, fanout board
PSEC3 related:
CHAMP related:
Any further testing of CHAMP?
AOB?
1-JUN-2011
Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Post-godparent review items:
Draft godparent review report [link]
MCP-PMT bandwidth (Jean-Francois) [txt] [png]
PSEC3 related:
New PSEC3 eval software posted at software page: [link]
18-MAY-2011
post submission
meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Preparations for Electronics godparent review, Friday May 20th @ ANL
Overview slides (for comment) [Gary] [PDF]
Link to Indico website: [link]
Other preliminary slides:
PSEC Beam Test Readout System [Mircea] [PDF]
CHAMP and alternative ASIC options - still in
outline/sketch phase [Kurtis]
[PDF]
Calibration / online feature extraction / data archiving -
to be posted [Kurtis]
[PDF]
TDR Update
List of action items [Gary]
Preparations for DOE review
@ ANL May 24-25
Kurtis's ROOT script to draw pad ring [tar.gz]
11-MAY-2011
post submission
meeting
(9am
HST, 2pm CDT, 9pm
CEST)
Preparations for Electronics godparent review:
Very preliminary draft Overview slides (for discussion) [Gary] [PDF]
Link to Indico website: [link]
TDR Update
List of action items [Gary]
Preparations for DOE review
@ ANL May 24-25
.
04-MAY-2011
Short Weekly Meeting
for May 9 submission last
minute
questions/issues
(9am
HST, 2pm CDT, 9pm
CEST)
Dial-in information: (866) 740-1260 (toll free USA,
Canada)
0800 94
2408 (Toll free Int'l [France])
Access code: 8147808 (followed by "#")
Short meeting this week focused on issues related to May 9
submission:
Chicago ASIC Submission - PSEC3A
Possible change to channel addressing for non-parallel
operation [Eric]
Other PSEC3A issues?
Hawaii ASIC Submission - RITC
Timing generation status/questions [Kurtis]
Other RITC issues?
Other items deferred until next week, post-submission.
20-APR-2011
Regular Weekly Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC3
CHAMP
PCB designs
All tray hardware in-hand
Other ASIC related
PSEC4 design/layout, in-progress [Herve]
PSEC4 pricing [Eric]
Parasitic extractions now working in Hawaii
Software/DAQ issues?
Repository at Chicago - updated [link] [Ed]
Coordination for PSEC3_eval GUI [Andrew, Eric]
GUI data format - desired
metadata [Ed, others]
Uploaded current version to Chicago web - needs link on
Code.php page [Kurtis]
Status of general USB read/write firmware & linux
software - given as part of CHAMP package, is it working? [Kurtis]
Next TDR updates [Gary,
Kurtis]
AOB?
Deferred
Stripline PMT results from Hawaii - ideally incorporate with
timing calibration TIPP results
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Flip-chip board status - deferred until QFP fully tested [Mircea]
Alternative ASICs [link]
13-APR-2011
Regular Weekly MeetinG
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC3
Status on testing with mezzanine card? [Eric, Hervé]
Next: Further testing w/ PSEC3 eval board, now in Hawaii.
[Andrew]
Anode testing
CHAMP
CHAMP_EVAL
Wrote several versions of test firmware to measure
performance of HI structures (including ucf file with
pin mappings) [Matt,
Kurtis]
Tested VCRO (ring oscillator), VCDL (delay lines), DAC
and WFS (waveform sampler) [pdf] [Matt, Kurtis]
Finished soldering 2 CHAMP_EVALs (one encapsulated;
one open cavity) and shipped them to Chicago Tuesday
morning [Matt]
CHAMP_eval schematics, as fabbed [pdf]
- will type up notes on corrections to rev A schematic
that were needed and post them here [Matt]
Bare die CHAMP tests - still waiting on network analyzer?
[Hervé]
Found a couple more bare die CHAMP photos on Chicago blog
- CHAMP
and PSEC3 and CHAMP
with coplanar waveguide probe [Hervé]
Had a conference call Tuesday morning with Ghassan Zamat
at IBM's microelectronics division and Roy Albano and Wailun
?? from Endicott Technologies about packaging options for
future 130nm IBM ASICs [Matt,
Kurtis]
PCB designs
Mezzanine card & Rev. B Digitizer - test results /
updates?
Status of flip-chip mezzanine card, analog card, other tray
hardware [documentation]
[Mircea]
Software/DAQ issues? [Ed,
Kurtis, others]
Coordination for simple GUI - Andrew performing testing in
HI [Andrew, Eric]
Status of general USB read/write firmware & linux
software [Kurtis]
Software repository location - on Chicago's repository [link]
TIPP Abstracts (deadline extended to April 15)
Mircea - LAPPD DAQ system [full abstract]
(submitted, trigger and DAQ systems track)
Eric & Hervé - PSEC3 [full abstract]
(submitted, front-end electronics track)
Mike & others (all CHAMP designers) - structures on
CHAMP [full abstract]
(submitted, front-end electronics track)
Kurtis & Andres - Timing calibration and application to
stripline prototype [full
abstract] (submitted, Front-end electronics track)
Next TDR updates [Gary,
Kurtis]
AOB?
Deferred
Stripline PMT results from Hawaii - ideally incorporate with
timing calibration TIPP results
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Flip-chip board status - deferred until QFP fully tested [Mircea]
Alternative ASICs [link]
6-APR-2011 Regular
Weekly Meeting
(9am
HST, 2pm CDT, 9pm
CEST)
PSEC3 updates
Testing with mezzanine card? [Eric, Hervé]
Timing calibrations w/ control sample (Tektronix data) [pdf] [Kurtis]
Next: Further testing w/ PSEC3 eval board, now in Hawaii.
Anode testing
CHAMP:
30 packaged CHAMPs arrived last night.
Populating the remainder of CHAMP eval today.
Would Chicago prefer open cavity or sealed?
Firmware issues:
Eval board uses a Xilinx Spartan-3. Can Chicago
program it?
CHAMP_eval user constraint file [txt]
CHAMP_eval schematics, as fabbed [pdf]
Bare die CHAMP tests - [pics
on elec. blog] - waiting on network analyzer?
100+ more CHAMP dice shipped from CERN.
Card designs:
Mezzanine card & Rev. B Digitizer - received back [blog
pics]
Status of flip-chip mezzanine card, analog card, other tray
hardware [documentation]
[Mircea]
Software/DAQ issues? [Ed,
Kurtis,others]
Coordination for simple GUI - Andrew performing testing here
[Andrew, Eric]
Status of general USB read/write firmware & linux
software [Kurtis]
Software repository location?
TIPP Abstracts (deadline extended to April 15):
Mircea - LAPPD DAQ system [full abstract]
(submitted, trigger and DAQ systems track)
Eric & Hervé - PSEC3 [full abstract]
(submitted, front-end electronics track)
Mike & others (all CHAMP designers) - structures on
CHAMP [full abstract]
(submitted, Front-end electronics track)
Kurtis & Andres - Timing calibration and application to
stripline prototype [full
abstract] (submitted, Front-end electronics track)
Next TDR updates [Gary,
Kurtis]
AOB?
30-MAR-2011
Regular Weekly Meeting
(9am
HST, 2pm CDT, 8pm CET)
PSEC3 updates
Further test results? [Hervé,
Eric]
Timing calibrations w/ larger data set provided by Eric [pdf]
[Kurtis]
To Do: Process Tektronix data for comparison
To Do: Further testing w/ PSEC3 eval board en route to
Hawaii.
CHAMP:
Packaging
Die received by Majelac, bonding diagram and orientation
were provided 3/29.
Packaging begins today, 3/30.
Expect to receive packaged CHAMP in ~1 week.
Bare die CHAMP received in Chicago
Card designs:
Mezzanine card & Rev. B Digitizer - due back ~end of
month
Status of flip-chip mezzanine card, analog card, other tray
hardware [documentation]
[Mircea]
Software/DAQ issues? [Ed,
Kurtis,others]
Coordination for simple GUI - Andrew to test w/ PSEC3 eval
here in Hawaii, when received [Andrew, Eric]
TIPP Abstracts (deadline extended to April 15):
Next TDR updates [Gary,
Kurtis]
AOB?
Deferred
Stripline PMT results from Hawaii - ideally incorporate with
timing calibration TIPP results
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Flip-chip board status - deferred until QFP fully tested [Mircea]
23-MAR-2011
Regular Weekly Meeting
(9am
HST, 2pm CDT, 8pm CET)
PSEC3 updates
Interface status from main LAPPD meeting [blog
pdf] [Hervé]
Bandwidth measurements [blog
pdf] [Hervé]
Timing calibrations - Eric has sent more data, still working
on processing it [Kurtis
away]
Also will process Tektronix data for comparison
PSEC3 eval board to Hawaii?
CHAMP:
Packaging PO processed (Majelac) and 32 CHAMP die have
been shipped
Expect to receive packaged CHAMP in ~1.5 - 2 weeks.
Bare die CHAMP received in Chicago - testing
results/schedule?
Card designs:
Mezzanine card & Rev. B Digitizer - due back ~end of
month
Status of flip-chip mezzanine card, analog card, other tray
hardware [documentation]
[Mircea]
Software/DAQ issues? [Ed,
Kurtis,others]
Ed's DAQ summary from main LAPPD meeting [blog
pdf]
Coordination for simple GUI - Andrew sent, any feedback? [Andrew, Eric]
TIPP Abstracts (submitter - informal topic):
Mircea - LAPPD DAQ system
Mike - structures on CHAMP
Kurtis - Timing calibration and application to stripline
prototype
Others?
Will try to make "pre-final" or "final" text available on
this page by Friday.
AOB?
Deferred
Stripline PMT results from Hawaii - ideally incorporate with
timing calibration TIPP results
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Flip-chip board status - deferred until QFP fully tested [Mircea]
Older & Perpetual items
Overall software/DAQ approach / protocol
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
Tray assembly status [pptx]
[Mircea]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
ASIC options for large channel count [link]
16-MAR-2011
Regular Weekly Meeting
(TIME
CHANGE FOR CHICAGO:
9am HST, 2pm CDT, 8pm
CET)
PSEC3 updates?
First attempt timing calibrations with data from Eric [pdf]
[Kurtis]
CHAMP:
Anode tests [blog
link] [Hervé]
Mezzanine card & Rev. B Digitizer, submitted? (and how
many?) [Eric]
Software/DAQ issues? [Ed,
Kurtis,others]
Coordination for simple GUI - Andrew to send preliminary
version [Andrew, Eric]
AOB?
Deferred
Stripline PMT results from Hawaii
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Flip-chip board status - deferred until QFP fully tested [Mircea]
Older & Perpetual items
Overall software/DAQ approach / protocol
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
Tray assembly status [pptx]
[Mircea]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
ASIC options for large channel count [link]
9-MAR-2011
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
Dial-in information: (866) 740-1260 (toll free USA,
Canada)
0800 94
2408 (Toll free Int'l [France])
Access code: 8147808 (followed by "#")
PSEC3 updates?
Growing PSEC3 documentation (from electronics blog):
Eric sent calibration data, first timing calibrations? [pdf]
[Kurtis]
ASIC options for large channel count [link]
CHAMP:
Design reviews - follow-up? [Mircea]
Mezzanine card & Rev. B Digitizer, submitted?
Flip-chip update - defer until QFP is tested?
Software/DAQ issues? [Ed,
Kurtis,others]
Coordination for simple GUI [Andrew, Eric]
Discussion of TIPP Submissions?
AOB?
Deferred
Stripline PMT results from Hawaii
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Older & Perpetual items
Overall software/DAQ approach / protocol
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
2-MAR-2011
Regular Weekly
Meeting
Henry won't be able to make it -- though posted a summary of
ASIC options [link]
Design reviews -- follow-up?? [Mircea]
PSEC3 updates?
Documentation on PSEC3 by Eric (from electronics blog) [pdf]
PSEC3 pinout graphic (from electronics blog) [png]
Calibration / sine wave data exchange?
Discussion on PSEC3(a) higher quantity prices / ASIC options
Flip-chip update?
CHAMP:
Software/DAQ issues? [Ed,
Kurtis,others]
Ed's Matlab/Octave waveform viewer for Tek .wfm files [link]
AOB?
Deferred
Stripline PMT results from Hawaii
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Older & Perpetual items
Overall software/DAQ approach / protocol
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
23-FEB-2011
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
Gary on an airplane (SLAC --> Hawaii), Kurtis at Lake
Louise, will try to call in.
Design reviews [Mircea]
Mezzanine card documentation [link]
Rev. B Digitizer:
schematics [link]
layout [link]
PSEC3 updates?
Flip-chip update?
CHAMP update?
CHAMP
flyer
Software/DAQ issues? [Ed,
Kurtis,others]
AOB?
Deferred
Stripline PMT results from Hawaii
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Older & Perpetual items
Overall software/DAQ approach / protocol
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
16-FEB-2011
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
Gary away, returns later today
PSEC3
Some assorted updates [blog
post] from [Hervé]
Requested 64-bit Cypress [driver] ,
from "Cypress Suite USB 3.4.2" [Kurtis]
Previously discussed calibrations
Initial [undocumented
/ uncommented code] (needs ROOT libraries to compile)
Give documentation & example [Kurtis]
Is PSEC3 sine wave data available somewhere? [Eric?]
Other updates/plans?
CHAMP
Arrived in Hawaii Jan. 14, 71 total pieces, 69 available
Die [photo(s)]
(large, 1.2 MB)
Hawaii to coordinate packaging [Matt]
How many to package? Can we package and still
maintain access to probe pads? Wire bonding ourselves
does not seem to seem to be an option due to required
14mmx14mm QFP.
CHAMP_eval - other parts have been ordered
After packaging, assembly queue: 2 for Chicago, 2 for
Hawaii
Software/DAQ issues [Ed,
Kurtis,others]
USB reference design, stuck on some Cypress issues [Kurtis]
Updating/porting previous Matlab code to Octave [Ed]
AOB?
Deferred
Stripline PMT results from Hawaii
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
Older & Perpetual items
Overall software/DAQ approach / protocol
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
09-FEB-2011
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
PSEC3
PSEC3 summary report from main LAPPD meeting [pdf]
[Eric]
(Hopefully relevant) Hawaii calibration approaches &
past experience [pdf]
[Kurtis]
Analog bandwidth considerations [ppt
from blog] [Jean-Francois]
Notes from discussion with Klaus [blog
post] [Hervé]
CHAMP
To arrive in Hawaii "soon" - no further updates since Jan.
24
Hawaii to coordinate packaging [Matt]
CHAMP_eval - other parts have been / are being ordered
Total: 2 for Chicago, 2 for Hawaii
Future ASIC plans - Jean-Francois visiting Chicago, Gary to
call Chicago later to discuss
Software/DAQ issues [Ed,
Kurtis,others]
USB reference design still in progress [Kurtis]
Updating/porting previous Matlab code to Octave [Ed]
Stripline PMT results from Hawaii
General trends seem okay (e.g., timing resolution vs. %
transmission of neutral density filter) [pdf]
Planning to take more data w/ more filters, better
amplifiers (previously 20 dB only). [Kurtis]
AOB?
Older & Perpetual items
Overall software/DAQ approach / protocol
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
02-FEB-2011
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
Matt & Gary away; Chicago under blizzard!
PSEC3
Report from main LAPPD meeting [pdf]
[Eric]
Any other PSEC report?
Regarding linearity discussions, some experience w/ BLAB3: [Kurtis]
BLAB3 linearity & sine wave histogram [pdf]
Note: above uses
very compact comparator [schematic
pdf]
CHAMP
To arrive in Hawaii soon(?)
Hawaii to coordinate packaging [Matt, once back]
CHAMP_eval - other parts have been ordered
Software/DAQ issues [Ed,
Kurtis,others]
Working on USB sample/reference design... more
details/documentation soon. [Kurtis]
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
AOB?
Deferred today
Stripline PMT results from Hawaii
More data was taken - analysis still underway [Kurtis]
Previous test results: [Second
round, PDF] [First
round, PDF]
Older & Perpetual items
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
26-JAN-2011
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
Kurtis back; Matt & Gary away
PSEC3
Bandwidth-related: [pdf
presentation from blog] [png
Bode plot] [Hervé]
Smith chart assistance request? [Hervé]
Report on results of trying to remove ripple delay errors? [Eric]
CHAMP
Currently being diced, to be shipped to Hawaii
Hawaii to coordinate packaging [Matt?]
CHAMP_eval - how many needed, populated, for each group?
Jean-Francois to visit Chicago early February - confirm?
Stripline PMT results from Hawaii
More data was taken - analysis still underway [Kurtis]
Previous test results: [Second
round, PDF] [First
round, PDF]
Software/DAQ issues [Ed,
Kurtis,others]
Working on USB sample/reference design... more
details/documentation soon. [Kurtis]
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
AOB?
Older & Perpetual items
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
19-JAN-2011
(Short) Regular Weekly
Meeting
(9am
HST, 1pm CDT, 8pm CET)
Kurtis away - items for next week & summary of meeting,
courtesy of Hervé
PSEC3
Report next week on results of trying to remove ripple delay
errors [Eric]
Bandwidth - Trying to plot Smith chart in Matlab... anyone
have experience? [Hervé]
BLAB3
Board redesign needed to confirm/test amplifier stability
[Gary]
Other
Jean-Francois to visit Chicago in early February, to be
confirmed.
12-JAN-2011
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
Dial-in information: (866) 740-1260 (toll free USA,
Canada)
0800 94
2408 (Toll free Int'l [France])
Access code: 8147808 (followed by "#")
Reports from picosecond timing workshop in Krakow [Jean-Francois]
Jean-Francois's report: [Part
2b] [Part
2c]
Full report series: [Part
1] [Part
2a] [Part
2b] [Part
2c]
[Full
Meeting INDICO]
Testing results
Stripline anodes passed
off to ANL for further testing w/ MCPs
Stripline PMT results from Hawaii
More data was taken - still need to analyze [Kurtis]
Previous test results: [Second
round, PDF] [First
round, PDF]
CHAMP
CHAMP - expected late January. [email]
from Kostas, as forwarded by Eric
CHAMP packaging - follow-up on what we expect to
receive? [Eric]
CHAMP_eval - received 9 total
PSEC3
Results reported at yesterday's main LAPPD meeting [pdf]
[Eric/Hervé]
Previously reported results:
Eric's report from Jan-05 main LAPPD meeting [ppt]
Lots of results available on the [electronics
blog]
Test of board input bandwidth [blog
post]
Software/DAQ issues [Ed,
Kurtis,others]
Continuing email discussions: [Ed
Jan-05-2011] [Henry
Jan-05-2011]
Previous record of discussion: [Ed
Nov-18-2010] [Kurtis
Dec-08-2010] [Ed
Dec-17-2010]
AOB?
Older & Perpetual items
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
05-JAN-2011
First Regular Weekly
Meeting
(9am
HST, 1pm CDT, 8pm CET)
Reports from Krakow [Jean-Francois]
Jean-Francois's report: [Part
2b] [Part
2c]
Full report series: [Part
1] [Part
2a] [Part
2b] [Part
2c]
[Full
Meeting INDICO]
Testing results
Stripline anodes passed
off to ANL for further testing w/ MCPs
Stripline PMT results from Hawaii [Kurtis - away]
More data was taken, to be discussed when Kurtis returns
next week
Previous test results: [Second
round, PDF] [First
round, PDF]
CHAMP
CHAMP - expected late January. [email]
from Kostas, as forwarded by Eric
CHAMP packaging - follow-up on what we expect to
receive? [Eric]
CHAMP_eval - received 9 total
PSEC3 - Lots of new test results!
Eric's report from main LAPPD meeting [ppt] [Eric]
Lots of resluts listed on the [electronics
blog] [Eric]
Test of board input bandwidth [blog
post] [Hervé]
Tray assembly status [pptx]
[Mircea]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
Software/DAQ issues [Ed,
Kurtis - away]
Postpone until next week when Kurtis returns, or continue by
email
Record of discussion: [Ed's
suggestions] [Kurtis's
thoughts / proposal] [Ed's
response]
AOB?
Older / Perpetual items
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
15-DEC-2010
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
Reports from Krakow? [Meeting
INDICO] [Gary,
Jean-Francois, Hervé]
Jean-Francois's next report: [Part
2a]
Testing results
Anode testing plans -
anodes passed off to ANL for testing with MCPs [Eric]
Stripline PMT results from Hawaii [Kurtis]
More data taken: [PDF,
analysis-in-progress]
Previous test results: [PDF]
CHAMP
CHAMP - expected late January. [email]
from Kostas, as forwarded by Eric
CHAMP packaging - follow-up on what we expect to
receive? [Eric?]
CHAMP_eval - received 9 total
PSEC3
Received by Chicago!
Test schedule / results - more on electronics blog and to be
discussed next meeting
BLAB3A
Very preliminary analog bandwidth [results]
Flip-chip board status [Mircea]
Follow-ups with Davis, outside company, [Fraunhofer
institute]
Software/DAQ issues
Previous suggestions from Ed on software/DAQ [txt]
Proposed data format for IRS/BLAB3/TARGET-based readouts [pdf,
in-progress] [Kurtis]
Meeting schedule for holiday and New Year?
AOB?
Older / Perpetual items
TDR update [ZIP]
archive (Last update: 21-NOV-2010)
08-DEC-2010
Regular Weekly Meeting
TDR update [ZIP]
archive (21-NOV-2010)
Reports from Krakow? [Meeting
INDICO] [Gary,
Jean-Francois, Hervé]
Jean-Francois's report: [Part
1]
Testing results
Follow-up on testing of
existing anodes
Last week's first test
outline & results from Eric: [blog
link] [pdf]
Any new results or
plans?
Stripline PMT testing in Hawaii
Last week's first timing results: [PDF]
Corrected / updated results on number of p.e. in last
tests [PDF]
Future plans?
CHAMP
CHAMP_eval - submitted for fabrication (ordered 9 total),
shipped Friday, expected Dec. 8 (today!)
What are actually getting, and when? No reponse yet
from Kostas.
Any others with contacts at CERN that could be helpful in
such situations?
PSEC3 - 30 bare die, 10 in ceramic package, another 10 at
MOSIS for plastic packaging
What is being / has been received? 30 bare die, 10
cermaic package, another 10 plastic packaged?
PSEC3 test board (8 ordered) - shipped,
expected las Friday. Did it arrive?
Flip-chip board status [Mircea]
Possible follow-up with outside company. (Lower
priority...?)
Frauenhofer institute follow-up [email
from Klaus]
Software/DAQ issues
Previous suggestions from Ed on software/DAQ [txt]
Proposed data format for IRS/BLAB3/TARGET-based readouts [pdf,
in-progress] [Kurtis]
AOB?
01-DEC-2010
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
TDR update [ZIP]
archive (21-NOV-2010)
Follow-up on testing of
existing anodes - first test outline & results from Eric [blog
link] [pdf]
CHAMP_eval - submitted for fabrication (ordered 9 total),
expected to ship on Dec. 6
PSEC3 - 30 bare die, 10 in ceramic package, another 10 at
MOSIS for plastic packaging
PSEC3 received at Chicago?
PSEC3 test board (8 ordered) - shipped,
expected in Friday
Flip-chip board status follow-up [Mircea]
Sierra sent back dies & PCB, can't stud bump for us.
Possible follow-up with another company?
Suggestions from Ed on software/DAQ [txt]
Arrange special discussion on software/DAQ - will write up a
brief proposal on data formats to start discussion [Kurtis]
First stripline PMT results in Hawaii [PDF]
Next tests: add ampliers, try other same-strip timing
algorithms (cross-correlation)
AOB?
24-NOV-2010
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
TDR update [ZIP]
archive (21-NOV-2010)
Update on anode strip simulations [Jean-Francois]
Results discussed (but
not yet seen) during last week's meeting. [pdf]
[original]
N ew plots recently distributed [pdf]
Follow-up
from last week on testing of existing anodes?
CHAMP_eval layout
(10-NOV-2010) [Gary]
Posted... comment from
Mircea on thermal ties.
Any other comments?
Flip-chip board status follow-up [Mircea]
PSEC3 received at CERN, shipping to Chicago [email]
Mircea's hardware development scheduling
slides from Tuesday's LAPPD meeting
Ed's related [questions] (in PDF at the linked post)
Suggestions from Ed on software/DAQ [txt]
Arrange special discussion on software/DAQ [Kurtis]
Mircea's [request]
for optical link protocol and schematic
Protocol is Aurora from Xilinx
Schematic for an example board is [here]
(others
are available as well)
Here is an interesting
study of using Aurora to communicate between Xilinx and
Altera [PDF]
AOB?
After main meeting - discussion on working with stripline PMT
[Gary,
Matt, Kurtis, Ed, Jean-Francois]
17-NOV-2010
Regular Weekly Meeting
Firmware update [link]
[Eric]
Update on anode strip simulations [link]
[Jean-Francois]
Follow-up
from last week on testing of existing anodes?
CHAMP_eval layout
(10-NOV-2010) [Gary]
Posted... any comments?
Mircea's hardware development scheduling
slides from Tuesday's LAPPD meeting
Ed's related [questions]
Mircea's [request]
for optical link protocol and schematic
Protocol is Aurora from Xilinx
Schematic for an example board is [here]
(others
are available as well)
10-NOV-2010
Regular Weekly Meeting
(9am
HST, 1pm CDT, 8pm CET)
Firmware update [link]
[Eric]
Update on anode strip simulations [link]
[Jean-Francois]
Follow-up
from last week on testing of existing anodes?
CHAMP_eval layout
(10-NOV-2010) [Gary]
Layout files [gerber]
Layout files (independent layers) [PDF]
Final schematics [PDF]
PADS design files: [schematics]
[layout]
Follow-ups:
PSEC2 flip-chip status [Mircea]
Revised system drawings -- TDR update, update [Gary]
Update on shipping MCP-PMT [Ed]
Update on sending PSEC1 and previous boards to
UC-Davis [Eric]
More PSEC3 ASICs ? (a tray requires 160 channels = 40
chips) [Eric]
Packaging for CHAMP ASICs (quote once die back)
[Matt]
Review Action Items from last meeting
AOB?
3-NOV-2010
Regular Weekly Meeting
(9am
HST, 2pm CDT, 8pm CET)
Firmware update [link]
[Eric]
Report on response uniformity of the inside-out anode plane
versus strip terminations [link]
[Jean-Francois]
Hermetic Packaging Godparent Review (22-OCT-2010)
[link]
Urgent issue to understand LBNE needs [Henry??]
Electronics for commercially produced modules? [Henry??]
Follow-ups:
PSEC2 flip-chip status [Mircea]
Revised system drawings -- system overview talk [Gary]
Update on sending PSEC1 and previous boards to
UC-Davis [Eric]
More PSEC3 ASICs ? (a tray requires 160 channels = 40
chips) [Eric]
Packaging for CHAMP ASICs (quote once die back)
[Matt]
Review Action Items from last meeting
AOB?
Follow-up/Action
Items
from the
27-OCT-2010
Weekly Meeting
Review Godparent Committee Review report response
[Gary/all]
TDR updates as a result
Short/near term readout test bed needs [Ed]
Follow-up items on direct/indirect feedback from Hermetic
Packaging Review
Urgent issue to understand LBNE needs [Henry]
Electronics for commercially produced modules? [Henry]
Various specific item follow-ups:
Update on anode transmission line simulations [Jean-Francois]
MCP-PMT with anode readout ship to Hawaii? [Ed]
PSEC1/test board update to UC-Davis? [Eric]
PSEC2 flip-chip testing procedures/confirmation [Mircea]
Contact Kostas about additional batch(es) of 40 PSEC3
[Jean-Francois]
Minor change to PSEC3 eval board (protection diode) and
fabrication status [Mircea]
CHAMP Eval layout review [Gary]
Connector/cable options for digital card/master
interconnection [Mircea]
Power connector options and LV regulation scheme
[Mircea/all]
HV connectors, distribution and filtering? [all]
27-OCT-2010
Regular Weekly Meeting
(9am
HST, 2pm CDT, 9pm CET)
Review Action Items from last meeting
Hermetic Packaging Godparent Review (22-OCT-2010)
[link]
Urgent issue to understand LBNE needs [Henry??]
Electronics for commercially produced modules? [Henry??]
Follow-ups:
PSEC2 flip-chip PCB testing OK -- PO status? [Mircea]
Revised system drawings [Mircea]
Revised Tray [jpg]
and
descriptive
[txt]
and
further
refined
version
(Rev.
B)
[jpg]
Revised analog/digital card [jpg]
and
descriptive
[txt]
and further refined version (Rev. B) [jpg]
A possible cable family for board interconnect [PDF]
[link]
Update on sending PSEC1 and previous boards to
UC-Davis [Eric]
How many PSEC3 ASICs to package? (only will get 40 and
not 200) ?? [Eric]
More PSEC3 ASICs ?? (a tray requires 160 channels = 40
chips) [Eric]
Packaging for CHAMP ASICs ?? (same as STURM2?)
[Eric]
Report on response uniformity of the inside-out anode plane
versus strip terminations [Jean-Francois]
Final board design for PSEC3 Eval board [link]
[Mircea]
AOB?
Action
Items
from the
13-OCT-2010
Weekly Meeting
Begin
Drafting Response to: Godparent Electronics
Review recommendations [doc]
[PDF]
Not clear
integration and feedback/interaction with rest of project
Suggestion is to put
something on the agenda to permit
discussion/coordination
Concern about
electromechanical meshing, grounding, HV
Suggestion is to
emphasize/provide links to existing documents in the
blog Library
System aspects, such
as global clock distribution, weren't presented
Mircea did present some
aspects in his talk
Some of this information
was presented previously; though in retrospect that may
have been during Collaboration meeting and not repeated
to committee
Point is well taken that
core documentation (TDR) is missing an overall system
diagram. This will be added to TDR.
Comment to reinvolve John
Anderson in the design/system aspects of jitter cleaner
system
Calibration issues
weren't presented
The electronics group has
collective experience in this task and it seemed a bit
too nuts/bolts
Agree that the TDR should
have add a section on this task that can be referenced
Perhaps most serious
issue raised -- inverted versus "conventional" stripline
This item is still under
study and will be resolved upon completion of this task
Testing plan -- in
particular with integrated photodetector -- was not
presented. Not clear what test systems needed when.
Ed agreed to help refine
the requirements
A detailed description of
the text system for a "first article" will be added to
the TDR as documentation
Decoupling of
characterization of the electronics and the MCP/PC
module needs clarification
Manpower concerns
for developing a full readout system in Year 2
A data
processing/recording system based upon existing designs
and expertise at Chicago and Hawaii was subsequently
adopted (one of the highlights to come out of the
review). It will be detailed in the TDR.
Some initial figures illustrating the working concept:
Analog_Digital_card
[jpeg]
Tray_Clocks [jpeg]
Contingency
scenarios for PSEC3
While our priority is to
work hard and qualify the PSEC3 as the baseline readout
on the 3-6month timeline from now; should a show-stopper
be identified, the group is ready to implement an
interim solution based upon existing ASICs (DRS4 or
IRS2). While these devices represent compromises
on the ultimate performance parameters, they should be
adequate for the first round of integrated testing
Revised Electronics section of TDR [J-F/Gary]
Current working draft: [PDF]
Known corrections
needed:
Overview prior to section 5.1 -- very first suggestion...
Text on digital part
Revise: DAQ, Clock, Slow control part
System diagram Figure needed (Mircea's as starting
place)
Use FINESSE DSP figure rather than cPCI_DSP
Additional wording needed for section 5.12
Full source files: [tdr_20oct2010.zip]
Outstanding Action
Item from trip:
Gary to bring back 25um MCP-PMT for
testing with BLAB3/IRS ASICs
Instead
agreed: Ed
will ship to Hawaii . Gary provided address
via e-mail: 2505 Correa Road, Watanabe Hall Room 214,
Honolulu, HI 96822
Update on CHAMP_eval [Gary]
Updated schematics (11-OCT-2010 version) [PDF]
--> Design suggestion: don't tie Ref to VDD.
Agreed, changed:
Revised schematics (17-OCT-2010 version) [PDF]
Deferred until Nov.
3rd meeting
Update from PSEC3 tester board [Mircea]
Schematics posted [link]
-->
Design
change: add protection diodes from
Aeroflex/Metalics [link]
Part number: SMPN7320-SOT23\
Revised above
Status of UC Davis processing [Eric]
Receipt of PSEC1, test boards -->
via snail mail, Mani will receive this week -- follow-up
above
AOB:
Eric will get MOSIS Project ID/passwd for CHAMP from
Jean-Francois
13-OCT-2010
Regular Weekly Meeting
(9am
HST, 2pm CDT, 9pm CET)
Godparent Electronics Review recommendations [doc]
[PDF]
Revised Electronics section
of TDR [J-F/Gary]
Edited draft [PDF]
Original source
files: [TDR_Electronics.tex]
[TDR_shell.tex]
Outstanding Action
Items from trip:
Gary to bring back 25um MCP-PMT for
testing with BLAB3/IRS ASICs ??
Update on CHAMP_eval [Gary]
Updated schematics (11-OCT-2010 version) [PDF]
Preliminary placement [PDF]
Update from PSEC3 tester board [Mircea]
Finished schematics posted [link]
Status of UC Davis processing [Eric]
Receipt of PSEC1, test boards?
Schedule update?
AOB?
Electronics
Godparent
Review --
October 6th at
ANL
Agenda for Electronics Review at ANL on October 6th [summary
from previous GPC]
Link to Zikri's
ElectronicsGF page [here]
Introductory
Questions
to
guide
the
material
presented
[PDF]
[source
tex file]
Guiding questions
(from Henry with GSV tweaks): [PDF]
[source
tex file]
Origination
(draft) Agenda
A) Refining Electronics needs
1. impact of SNR, analog BW, cost/performance
trade-offs [J-F]
2. Project specific specifications (LHCb, JPARC, LBNE,
SuperB), PET, muon cooling ?) [J-F]
3. Fabrication process options (IBM 130nm and
others?) [Gary] [pptx]
[PDF]
B) ASIC Developments
1. Results and further testing plans for PSEC2 [Eric]
2. Building block evaluation ASIC: CHAMP design and
evaluation plans [Matt] [pptx]
[PDF]
3. PSEC3 design and evaluation plans
[Hervé]
C) Integrated Design issues
1. Simulation results for single photon detection [Jacob
Li] [PDF]
2. Recent stripline anode readout simulations [J-F]
3. Readout boards (analog/digital cards for supermodule),
links,
architecture overview and plans [Mircea?]
D) Test and evaluation resources and requirements [Gary]
[pptx]
[PDF]
Summary from previous GPC
[PDF]
Link to Zikri's
ElectronicsGF page [here]
Link to the latest version
of the TDR (v1.03) [PDF
link]
29-SEP-2010
Regular Weekly Meeting
(11am
HST, 4pm CDT, 11pm
CET)
Possible change of meeting time? (a more European
friendly time slot?)
Decided
to
move to 2pm CDT, 9pm CET, 9am HST
Review of Action
Items from last meeting, with follow-ups:
Follow-up
on phone meeting with UC Davis --> 2pm
PDT on Friday: meeting [link]
Consider TQFP packaging for
PSEC3, CHAMP [MOSIS LQFP128A package]
Comments from Ed on software
posted on blog [link]
Gary to bring back 25um MCP-PMT for
testing with BLAB3/IRS ASICs
Agenda for Electronics Review at ANL on October 6th [summary
from previous GPC]
Link to Zikri's
ElectronicsGF page [here]
Introductory
Questions
to
guide
the
material
presented
[PDF]
[source
tex file]
Refining Electronics needs:
impact of SNR, analog BW,
cost/performance trade-offs
Project specific
specifications
Fabrication process
options (besides IBM 130nm)
ASIC Developments:
Results and further
testing plans for PSEC2
Building block evaluation
ASIC: CHAMP
PSEC3 design
Integrated Design issues
Simulation results for
single photon detection
Recent stripline anode
readout simulations
Readout boards
(analog/digital cards for supermodule), links,
architecture overview and plans
Test and evaluation
resources and requirements
Other?
Revise Electronics section of
TDR: [TDR_Electronics.tex]
[TDR_shell.tex]
Update on CHAMP_eval [Gary]
TQFP chosen
Want at least 20 as bare die (some test circuits require
probe/internal wire bonding)
Updated schematics (29-SEP-2010 version) [PDF]
Preliminary placement [PDF]
Updates (via e-mail) from Mircea:
Received 1 PSEC2 Flip Chip PCB, Mark will stuff ASAP, should
test it this week
Finished PSEC3 module schematics posted [link]
BOM is also finished, posted
Further discussion on the UC Davis option?
Stream of discussion in text format, message 1: [txt]
and
subsequent
follow-ups
[txt]
When to arrange a call?
Use PSEC1 for first functional Au stud bond
test?
A smaller test board? (< 10cm x 10cm)
AOB?
22-SEP-2010
Regular Weekly Meeting
(11am
HST, 4pm CDT, 11pm
CET)
Review of Action
Items from last meeting, with follow-ups:
Henry
will
check on 3pm time on Friday for phone meeting with UC Davis
Consider seriously TQFP
packaging for PSEC3, CHAMP [MOSIS LQFP128A package]
Comments from Ed on
software posted on blog [link]
Gary to bring back 25um
MCP-PMT for testing with BLAB3/IRS ASICs
Agenda for Electronics
Review at ANL on October
6th
[summary
from previous GPC]
Refining Electronics needs:
impact of SNR, analog BW,
cost/performance trade-offs
Project specific
specifications
Fabrication process
options (besides IBM 130nm)
ASIC Developments:
Results and further
testing plans for PSEC2
Building block evaluation
ASIC: CHAMP
PSEC3 design
Integrated Design issues
Simulation results for
single photon detection
Recent stripline anode
readout simulations
Readout boards
(analog/digital cards for supermodule), links,
architecture overview and plans
Test and evaluation
resources and requirements
Update on CHAMP_eval schematics [Gary]
TQFP trial?
First pass at schematics [PDF]
Revised (closer) schematics [PDF]
Brief update on Sierra PSEC2 flip-chip progress [Mircea]
Blog posting [link]
Discussion on the UC Davis option:
Stream of discussion in text format, message 1: [txt]
and
subsequent
follow-ups
[txt]
When to arrange a call?
Use PSEC1 for first functional Au stud bond
test?
A smaller test board? (< 10cm x 10cm)
What to do in the intermediate term? [all]
Decided
to
go with DRS4_eval boards for first testing
BLAB3/IRS?
firmware needs work
Much deeper sampling rate
IRS has respectable bandwidth [PDF]
DRS4?
Mircea has experience with board for this ASIC
DRS4 known to work well
input bandwidth is an issue -- have to use an external amp
STURM2?
Narrow sampling window
>= 10GSa/s possible (only 8x samples)
Firmware work needed
Presentation from Jacob on CSA input amp [PDF]
First Experimental runs at the UH xFEL (ps x-ray
timing/beamline) [link]
Exp.
#2
direct
[link]
AOB?
15-SEP-2010
Meeting Action
Items
Decide on PSEC3 &
CHAMP packaging (need Henry and J-F consensus)
[next meeting]
Continued study of existing linux acquisition code -- with an
eye toward generic modules [Ed]
Posted comments [link]
Comments based upon the current code -- needs Kurtis'
feedback [txt]
Ed encouraged getting one of the small MCP-PMTs to Hawaii for
mating:
with existing IRS/STURM ASICs
test in the xFEL beamline (1ps jitter)
Defer discussion on possible module electronics in medium term
when Henry/J-F can participate
15-SEP-2010
Regular Weekly Meeting
(11am
HST, 4pm CDT, 10pm
CET?)
Review of Action
Items from last meeting
Update on CHAMP_eval schematics (priority dropped due to CHAMP
delivery update) [Gary]
Root-based version of simple USB readout -- further
development plans? [Gary/all]
Update on Sierra progress [Mircea]
On
schedule for delivery of 1x board on time
Expected
ship date Sept 24
Revision to test plans? [all]
Discuss package/footprint for packaged parts [all]
What to do in the intermediate term? [all]
BLAB3/IRS?
DRS4?
STURM2?
Presentation from Jacob on CSA input amp (deferred until
next time)
Short report from xFEL (ps x-ray timing/beamline) [PDF]
AOB?
8-SEP-2010
Meeting Action
Items
Establish ES-Net connection for next meeting per Ed's
instructions [Gary] -- Done
Send link to root-based version of simple USB readout
[Gary] -- Done
Summary
e-mail
with various links [linux_soft.txt]
Update on Sierra progress next time [Mircea]
Confirm package/footprint for packaged parts
[Mircea/Eric] -- Done
Confirm how many die to be packaged versus bare die (for
probing) [Eric/J-F] -- Done
Re-iterate
numbers: to be decided for CHAMP?
Response from CERN on revised ASIC delivery schedules
[Jean-Francois] -- Done
Message from J-F, including information from CERN folk
[.txt]
Bottom
line:
should not expect to see until mid-December
Specific reminders:
J-F and Gary need to compare bonding wire vs.
flip-chip notes (during review?)
The bonding diagram for
PSEC is fine with J-F
MOSIS V05F (CHAMP) and V08B
(PSEC3) both due mid December
bare dies for CHAMP [Kostas
to confirm how many] -- have to package ourselves
10 packaged, 30 bare dies
for PSEC3
Follow-up with Bob W. on SOW [Gary] --
Done
Anything I missed?
8-SEP-2010
Regular Weekly Meeting
4pm CDT (Chicago), 11am HST
(Honolulu)
(808) 956-2920 [ID Lab]
Proposed
agenda:
PSEC2 ASIC board firmware update [Eric]
PSEC2 ASIC board software/data format [Eric]
Board test plans discussion (Chicago & Hawaii?)
[all]
Feedback/schedule update from Sierra [Mircea]
CHAMP test schematics (Chicago) [Mircea/Eric]
schematic file [PDF]
CHAMP test items (Hawaii) [Matt]
CHAMP pinout/ownership spreadsheet [link]
Test board spreadsheet [link]
graphical pin assignment [PDF]
CHAMP test schematics (Hawaii) [Gary/Matt/Louie]
Same basic FPGA + USB readout as on many eval boards
LQPF128A packaging? [needed for footprint]
Placeholder schematics [PDF]
CHAMP eval board design review (Sept. 15?) discussion
[all]
PSEC3 evaluation board plans [Mircea/Eric]
Update on ASIC deliveries (from Europe) [Jean-Francois]
Tried to make contact via e-mail/phone --> will advise
when hears something
Currently working on memo about transmission line readout
Noise discussion/plot for TDR? [Henry]
Brief update on single p.e. (CSA, low-noise) amplifier
[next time -- Jacob]
AOB ?
Archival:
27-AUG-2010
Flip-chip
board design review
Link to manufacturing drawings [here]
The proposed agenda includes:
- module functions,
- schematics,
- layout,
- manufacturing and cost,
- delivery schedule.
We will do this over the phone: 808-957-8610 passcode
1414
CHAMP board (regular
LAPPD Electronics subgroup) Discussion
Agenda
items:
ETA on CHAMP ASIC
Detailed design plans and task sharing for CHAMP test card
Lessons learned from IRS/BLAB3
BLAB3A plans
status of sending test board to Hawaii (?)
Preparation for design review Friday
AOB
10-MAY-2010 Hervé
update [txt]
(for 9am HST phone call)
Reference
Information:
Message on pads/padring/protection location [txt]
Padring [revised] draft [PDF]
Padring/FP [xfig]
source
Google docs spreadsheet [link]
16-JUN-2010
ASIC#2 being shipped from MOSIS
Note from Matt on USB programming [link]
10-MAY-2010 Hervé
update [txt]
(for 9am HST phone call)
Reference
Information:
Message on pads/padring/protection location [txt]
Padring [revised] draft [PDF]
Padring/FP [xfig]
source
Google docs spreadsheet [link]
5-MAY-2010 Agenda:
Discussion on status of integration
Review of items below
Plans/schedule prior to 17-MAY
Follow-up:
1) Other ASIC acronym suggestions? [responses]
Chicago Hawaii ASIC, Multi-Purpose [CHAMP]
Chicago Hawaii ASIC for Study of I
2) Does IBM offer scripts for the end user to perform metal fill
operations which IBM does not automatically perform?
Hervé's response:
We did it by hand last time, it
takes relatively a lot of time (around one day to do it) and has
to be done for the last three
levels of metals; MA, E1 and
LY.
For this three metals you need
to fulfill the local and global density checks. A script would
save us a lot of time
and difficulties for sure.
IMPORTANT REMARK : in the
previous submissions we always had issues with these local and
global density checks,
and our design had to go back
and forth between us and Mosis to fulfill them.
Follow-up question: did anyone ask MOSIS/CERN/IBM if such a script exists?
3) Hawaii is using the IBM 1.6.2.5 design kit provided to MOSIS.
Does this match with Chicago and CERN? -- DONE
Hervé
confirms it is the same.
4) Will Chicago complete the pad ring with their components and ship
the design to Hawaii?
5) Additional layers/options Hawaii is using (this will need to get
checked with Matt, Kurtis, Larry -- To be done
Thin + thick oxide (2.5V I/O transistors)
Regular + Low Vt NFET
Regular + Low Vt PFET
Dual
MIM Cap
6) Parasitic extraction [Hervé] -- DONE
Link is [here]
7) Footprint for probe pads [J-F] -- To be done
8) Allowed to use dual mimCAP? -- DONE
Yes.
Kostas confirms this option (29-APR-10)
9) Implementing MC spreads in simulation [Eric] -- DONE
Eric sent out message and link is [here]
21-APR-2010 Meeting:
Agenda [txt]
We prepare preliminary dimensions and I/O pads for our blocks: - PLL - Timing generator (new version) with variable sampling windows = RO (based on the new timing generator delay cell) + divider - Phase comparator + charge pump - Transmission line - Resistors (we still do not know) and a tentative floorplanning of say 3.24 x 3.24/2 (unless you need more ?) For the delay generator, we have actually 256 cells of 12 microns each, so 3072 microns, we plan for 3.15mm maximum that fit the 3.24mm 128 pads is just perfect ! Jean-Francois On Tue, 20 Apr 2010, Gary S. Varner wrote: The agenda from our side: 1) Mike : LVDS Rx/Tx 2) Larry : small storage array 3) Wei : Charge Sensitive Amp 4) Kurtis: fast, differential storage cell 5) Matt : ring oscillators & DFFs 6) Gary : DAC & OTA/ABUF
Recent items:
TDR working directory [draft]
Link to Electronics
Godparent
committee page
Reference docs
IRS analog bandwidth measurement [PDF]
Simulated TQFP input coupling [PDF]
UH
"DC card" (psTDC01 eval) software [Larry]
UH
"DC card" (psTDC01 eval) RevDv01 firmware [Larry]
UH
"DC card" (psTDC01 eval) RevD v2 schematics [Larry]
3 technical reports on Detector, ASIC, DAQ [Gary, all]
Reference links:
Main picosecond page
blog
Electronics
blog
Return
to scheduling page
Last modified: 3/8/2014
-- GSV