MCP_MAINv02 Project Status
Project File:	MCP_MAINv02.ise	Current State:	Programming File Generated
Module Name:	TOP	Errors:	No Errors
Target Device:	xc2vp2-5fg256	Warnings:	266 Warnings
Product Version:	ISE 10.1.03 - Foundation Simulator	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

 

MCP_MAINv02 Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	651	2,816	23%
Number of 4 input LUTs	775	2,816	27%
Logic Distribution
Number of occupied Slices	699	1,408	49%
Number of Slices containing only related logic	699	699	100%
Number of Slices containing unrelated logic	0	699	0%
Total Number of 4 input LUTs	958	2,816	34%
Number used as logic	775
Number used as a route-thru	183
Number of bonded IOBs
Number of bonded	109	140	77%
IOB Master Pads	14
IOB Slave Pads	14
Number of BUFGMUXs	7	16	43%
Number of DCMs	1	4	25%
Number of GTs	1	4	25%
Number of RPM macros	2

 

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri Apr 16 10:30:25 2010	0	245 Warnings	37 Infos
Translation Report	Current	Fri Apr 16 10:30:32 2010	0	1 Warning	0
Map Report	Current	Fri Apr 16 10:30:37 2010	0	17 Warnings	7 Infos
Place and Route Report	Current	Fri Apr 16 10:30:52 2010	0	3 Warnings	1 Info
Static Timing Report	Current	Fri Apr 16 10:30:57 2010	0	1 Warning	2 Infos
Bitgen Report	Current	Fri Apr 16 10:31:05 2010	0	2 Warnings	1 Info

Date Generated: 04/16/2010 - 11:31:58