We prepare preliminary dimensions and I/O pads for our blocks: - PLL - Timing generator (new version) with variable sampling windows = RO (based on the new timing generator delay cell) + divider - Phase comparator + charge pump - Transmission line - Resistors (we still do not know) and a tentative floorplanning of say 3.24 x 3.24/2 (unless you need more ?) For the delay generator, we have actually 256 cells of 12 microns each, so 3072 microns, we plan for 3.15mm maximum that fit the 3.24mm 128 pads is just perfect ! Jean-Francois On Tue, 20 Apr 2010, Gary S. Varner wrote: The agenda from our side: 1) Mike : LVDS Rx/Tx 2) Larry : small storage array 3) Wei : Charge Sensitive Amp 4) Kurtis: fast, differential storage cell 5) Matt : ring oscillators & DFFs 6) Gary : DAC & OTA/ABUF