CAP3 PROJeCT
CAP3 CHARACTERISTICS and DOCUMENTATION (NEW!!!!!)
CAP3 is a particle detector based in pixel structure. Each pixel has a size of 22.5x22.5 um^2. The total size of complete sensor is based in a 928 columns x 128 rows (2.088cm x 0.288 cm)
The detector structure is based in a 3T, using a reset transistor with tunable gate voltage (controlled by Areset), a source follower and a current bias(controlled by Refbias).
Every single pixel has 10 storage cells, divided in 2 different paths (controlled by signals s0 and s1 for the pre-trigger sampling and the post-trigger sampling, see schematics). There are 5 storage cell in every stage, controlled by signals ssx(0-4) and cpsx(0-4). The initial signal ssx controls the storage of the signal in a capacitance formed at the gate of a transistor. The second signal cpsx allows the readout in the common bus line. The readout architecture is based in a common source configuration using a current-source load. The current source load is shared for all the line. Every single pixel will have 2 output lines (coming form s0/s1)
To read out the signal there are a few importAnt signals:
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Every output line is connected to all rows (928 pixels) with 5 storage cells per pixel.
The 5 storage cells are controlled by cpsx.
The pixel transimitting the information is done because every cpsx pixel column is generated using a
shifting register and a periodic signal, which assigns a time frame to every pixel.
It corresponds to 25us per pixel.
This signal is RstClk
-
The result of this lines are 128x2 lines (one coming from s0/s1) and they go to a 8x1 MUX, ending in 16x2 lines.
These are the lines that go to the pads(32 output analog values).
- A complete schematics description of CAP3, can be found at the pdf
- See detail of the pad output PDF
CAP3 BEAM TEST BOARD (NEW!!!)
The information related to the beamtest board is the following:
- Schematics pdf
- Board Layout pdf
- Schematics pdf
- Board Layout pdf
ANALOG VALUES USED
Vdd=2.5V
The values defining the performance of the sensor is Areset, Obias.
In case of August 2006:
- Areset: 1.218V
- Obias: 1.254V
- Refbias: 418mV
TOM ZIMMERMANN TEST ANALYSIS MARCH 2006
- Close sample and readout switches
Using Refbias:0.42V (1uA) and just analyzing the output of 1 storage cell the inverting curve shows that
the swiching point takes place between the Areset values of 920mV to 980mv, with a gain of 53 at the linear
region.
- Cell to Cell analysis
Transistor mismatch (and layout ??) causes cells to be at the rails. Mreset and Msource_follower are smallest
geometry and bigger contributors Tens of mV Vgs variation.
Between storage cell0 from s0/s1 there is a sistematic output mismatch of 500mV (layout!!!!)
Mcommon_source and Mcurrent_source_load offset contribution of a few mV.
- Pixel capacitance and Leakage current
Switching the Areset signal and measuring directly through a channel a Cpixel~3fF (using simulation).
Looking at the output slope while Areset=0, Leakage current measured of 1.5fA. It shows HIGH dependence with Vdd:
- Vdd=2.5V - I=60fA
- Vdd=2.3V - I=20fA
- Sample and Read Out
Considering the following circuit the agin Vout/VAreset=3.3